Generated by Sigasi 4.13.0.qualifier
Revision 2021-06-08
This projects has 449 design units.
This design unit is implemented in top_earlgrey_asic.sv
This file depends on: pinmux_reg_pkg.sv, entropy_src_pkg.sv, ast.sv, top_pkg.sv, clkmgr_pkg.sv, sensor_ctrl_reg_pkg.sv, jtag_mux.sv, otp_ctrl_pkg.sv, top_earlgrey_pkg.sv, tlul_pkg.sv, prim_usb_diff_rx.sv, pwrmgr_pkg.sv, top_earlgrey.sv, ast_pkg.sv, rstmgr_pkg.sv, padring.sv, edn_pkg.sv, aes_pkg.sv, lc_ctrl_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumIOs | int | pinmux_reg_pkg::NMioPads + pinmux_reg_pkg::NDioPads | |
| TieOffValues | [NumIOs-1:0] logic | NumIOs'(1'b1 << ( pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb)) | This specifies the tie-off values of the muxed MIO/DIOs when the JTAG is active. SPI CSB is active low. |
| Name | Direction | Type | Description |
|---|---|---|---|
| POR_N | inout | logic | Clock and Reset |
| SPI_HOST_D0 | inout | logic | Bank A (VIOA domain) |
| SPI_HOST_D1 | inout | logic | |
| SPI_HOST_D2 | inout | logic | |
| SPI_HOST_D3 | inout | logic | |
| SPI_HOST_CLK | inout | logic | |
| SPI_HOST_CS_L | inout | logic | |
| SPI_DEV_D0 | inout | logic | |
| SPI_DEV_D1 | inout | logic | |
| SPI_DEV_D2 | inout | logic | |
| SPI_DEV_D3 | inout | logic | |
| SPI_DEV_CLK | inout | logic | |
| SPI_DEV_CS_L | inout | logic | |
| IOA0 | inout | logic | MIO 0 |
| IOA1 | inout | logic | MIO 1 |
| IOA2 | inout | logic | MIO 2 |
| IOA3 | inout | logic | MIO 3 |
| IOA4 | inout | logic | MIO 4 |
| IOA5 | inout | logic | MIO 5 |
| IOB0 | inout | logic | MIO 6 |
| IOB1 | inout | logic | MIO 7 |
| IOB2 | inout | logic | MIO 8 |
| IOB3 | inout | logic | MIO 9 |
| IOB4 | inout | logic | MIO 10 |
| IOB5 | inout | logic | MIO 11 |
| IOB6 | inout | logic | MIO 12 |
| IOB7 | inout | logic | MIO 13 |
| IOB8 | inout | logic | MIO 14 |
| IOB9 | inout | logic | MIO 15 |
| IOB10 | inout | logic | MIO 16 |
| IOB11 | inout | logic | MIO 17 |
| IOC0 | inout | logic | MIO 18 |
| IOC1 | inout | logic | MIO 19 |
| IOC2 | inout | logic | MIO 20 |
| IOC3 | inout | logic | MIO 21 |
| IOC4 | inout | logic | MIO 22 |
| IOC5 | inout | logic | MIO 23 |
| IOC6 | inout | logic | MIO 24 |
| IOC7 | inout | logic | MIO 25 |
| IOC8 | inout | logic | MIO 26 |
| IOC9 | inout | logic | MIO 27 |
| IOC10 | inout | logic | MIO 28 |
| IOC11 | inout | logic | MIO 29 |
| IOR0 | inout | logic | MIO 30 |
| IOR1 | inout | logic | MIO 31 |
| IOR2 | inout | logic | MIO 32 |
| IOR3 | inout | logic | MIO 33 |
| IOR4 | inout | logic | MIO 34 |
| IOR5 | inout | logic | MIO 35 |
| IOR6 | inout | logic | MIO 36 |
| IOR7 | inout | logic | MIO 37 |
| IOR8 | inout | logic | MIO 38 |
| IOR9 | inout | logic | MIO 39 |
| IOR10 | inout | logic | MIO 40 |
| IOR11 | inout | logic | MIO 41 |
| IOR12 | inout | logic | MIO 42 |
| IOR13 | inout | logic | MIO 43 |
| CC1 | inout | logic | DCD (VCC domain) |
| CC2 | inout | logic | |
| USB_P | inout | logic | USB (VCC domain) |
| USB_N | inout | logic | |
| FLASH_TEST_MODE | inout | [3:0] logic | FLASH |
| FLASH_TEST_VOLT | inout | logic |
TODO: this is a temporary solution. JTAG will eventually be selected and qualified inside the pinmux, based on strap and lifecycle state. Parameterizeable JTAG overlay mux. Unaffected indices are just passed through.
This design unit is implemented in aes_pkg.sv
This design unit is implemented in ast.sv
This file depends on: adc.sv, io_clk.sv, uvm_pkg.sv, rglts_pdm_3p3v.sv, pinmux_pkg.sv, aon_clk.sv, tlul_pkg.sv, rng.sv, entropy.sv, usb_clk.sv, ana_pkg.sv, ast_pkg.sv, gen_pok.sv, ast_reg_top.sv, edn_pkg.sv, sys_clk.sv, alert.sv, lc_ctrl_pkg.sv, ast_reg_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AdcChannels | int | 2 | |
| AdcDataWidth | int | 10 | |
| EntropyStreams | int | 4 | |
| Ast2PadOutWidth | int | 16 | TODO:final size |
| Pad2AstInWidth | int | 16 | TODO:final size |
| UsbCalibWidth | int | 16 | TODO:final size |
| EntropyRateWidth | int | 4 | Entropy (Always ON) |
| Name | Direction | Type | Description |
|---|---|---|---|
| tl_i | in | tl_h2d_t | TLUL H2D |
| tl_o | out | tl_d2h_t | TLUL D2H |
| clk_ast_adc_i | in | logic | Buffered AST ADC Clock |
| rst_ast_adc_ni | in | logic | Buffered AST ADC Reset |
| clk_ast_alert_i | in | logic | Buffered AST Alert Clock |
| rst_ast_alert_ni | in | logic | Buffered AST Alert Reset |
| clk_ast_es_i | in | logic | Buffered AST Entropy Source Clock |
| rst_ast_es_ni | in | logic | Buffered AST Entropy Source Reset |
| clk_ast_rng_i | in | logic | Buffered AST RNG Clock |
| rst_ast_rng_ni | in | logic | Buffered AST RNG Reset |
| clk_ast_tlul_i | in | logic | Buffered AST TLUL Clock |
| rst_ast_tlul_ni | in | logic | Buffered AST TLUL Reset |
| clk_ast_usb_i | in | logic | Buffered AST USB Clock |
| rst_ast_usb_ni | in | logic | Buffered AST USB Reset |
| clk_ast_ext_i | in | logic | Buffered AST External Clock |
| por_ni | in | logic | Power ON Reset |
| vcc_supp_i | in | logic | VCC Supply Test for OS FPGA |
| vcaon_supp_i | in | logic | VCAON Supply Test for OS FPGA |
| vcmain_supp_i | in | logic | VCMAIN Supply Test for OS FPGA |
| vioa_supp_i | in | logic | VIOA Rail Supply Test for OS FPGA |
| viob_supp_i | in | logic | VIOB Rail Supply Test for OS FPGA |
| vcaon_pok_o | out | logic | VCAON Power OK |
| vcmain_pok_o | out | logic | VCMAIN Power OK |
| vioa_pok_o | out | logic | VIOA Rail Power OK |
| viob_pok_o | out | logic | VIOB Rail Power OK |
| main_pd_ni | in | logic | MAIN Regulator Power Down |
| main_iso_en_i | in | logic | Isolation enable for main core power (VCMAIN). |
| flash_power_down_h_o | out | logic | Flash Power Down |
| flash_power_ready_h_o | out | logic | Flash Power Ready |
| otp_power_seq_i | in | [1:0] logic | MMR0,24 in (VDD) |
| otp_power_seq_h_o | out | [1:0] logic | MMR0,24 masked by PDM, out (VCC) |
| clk_src_sys_en_i | in | logic | SYS Source Clock Enable |
| clk_src_sys_jen_i | in | logic | SYS Source Clock Jitter Enable |
| clk_src_sys_o | out | logic | SYS Source Clock |
| clk_src_sys_val_o | out | logic | SYS Source Clock Valid |
| clk_src_aon_o | out | logic | AON Source Clock |
| clk_src_aon_val_o | out | logic | AON Source Clock Valid |
| clk_src_io_en_i | in | logic | IO Source Clock Enable |
| clk_src_io_o | out | logic | IO Source Clock |
| clk_src_io_val_o | out | logic | IO Source Clock Valid |
| usb_ref_pulse_i | in | logic | USB Reference Pulse |
| usb_ref_val_i | in | logic | USB Reference Valid |
| clk_src_usb_en_i | in | logic | USB Source Clock Enable |
| clk_src_usb_o | out | logic | USB Source Clock |
| clk_src_usb_val_o | out | logic | USB Source Clock Valid |
| usb_io_pu_cal_o | out | [UsbCalibWidth-1:0] logic | USB IO Pull-up Calibration Setting |
| adc_pd_i | in | logic | ADC Power Down |
| adc_a0_ai | in | logic | ADC A0 Analog Input |
| adc_a1_ai | in | logic | ADC A1 Analog Input |
| adc_chnsel_i | in | [AdcChannels-1:0] logic | ADC Channel Select |
| adc_d_o | out | [AdcDataWidth-1:0] logic | ADC Digital (per channel) |
| adc_d_val_o | out | logic | ADC Digital Valid |
| rng_en_i | in | logic | RNG Enable |
| rng_val_o | out | logic | RNG Valid |
| rng_b_o | out | [EntropyStreams-1:0] logic | RNG Bit(s) |
| entropy_rsp_i | in | edn_rsp_t | Entropy Response |
| entropy_req_o | out | edn_req_t | Entropy Request |
| as_alert_trig_i | in | ast_dif_t | Active Shield Alert Trigger |
| as_alert_ack_i | in | ast_dif_t | Active Shield Alert Acknowledge |
| as_alert_o | out | ast_dif_t | Active Shield Alert |
| cg_alert_trig_i | in | ast_dif_t | Clock Glitch Alert Trigger |
| cg_alert_ack_i | in | ast_dif_t | Clock Glitch Alert Acknowledge |
| cg_alert_o | out | ast_dif_t | Clock Glitch Alert |
| gd_alert_trig_i | in | ast_dif_t | Glitch Detect Alert Trigger |
| gd_alert_ack_i | in | ast_dif_t | Glitch Detect Alert Acknowledge |
| gd_alert_o | out | ast_dif_t | Glitch Detect Alert |
| ts_alert_hi_trig_i | in | ast_dif_t | Temp Sense High Alert Trigger |
| ts_alert_hi_ack_i | in | ast_dif_t | Temp Sense High Alert Acknowledge |
| ts_alert_hi_o | out | ast_dif_t | Temp Sense High Alert Positive |
| ts_alert_lo_trig_i | in | ast_dif_t | Temp Sense Low Alert Trigger |
| ts_alert_lo_ack_i | in | ast_dif_t | Temp Sense Low Alert Acknowledge |
| ts_alert_lo_o | out | ast_dif_t | Temp Sense Low Alert |
| ls_alert_trig_i | in | ast_dif_t | Light Sense Alert Trigger |
| ls_alert_ack_i | in | ast_dif_t | Light Sense Alert Acknowledge |
| ls_alert_o | out | ast_dif_t | Light Sense Alert |
| ot_alert_trig_i | in | ast_dif_t | OTher Alert Trigger |
| ot_alert_ack_i | in | ast_dif_t | OTher Alert Acknowledge |
| ot_alert_o | out | ast_dif_t | OTher Alert |
| dft_strap_test_i | in | dft_strap_test_req_t | DFT Straps |
| lc_dft_en_i | in | lc_tx_t | DFT enable (secure bus) |
| padmux2ast_i | in | [Pad2AstInWidth-1:0] logic | IO_2_DFT Input Signals |
| ast2padmux_o | out | [Ast2PadOutWidth-1:0] logic | DFT_2_IO Output Signals |
| pad2ast_t0_ai | in | logic | PAD_2_AST Analog T0 Input Signal |
| pad2ast_t1_ai | in | logic | PAD_2_AST Analog T1 Input Signal |
| ast2pad_t0_ao | out | logic | AST_2_PAD Analog T0 Output Signal |
| ast2pad_t1_ao | out | logic | AST_2_PAD Analog T1 Output Signal |
| lc_clk_byp_req_i | in | lc_tx_t | External clock mux override for OTP bootstrap |
| lc_clk_byp_ack_o | out | lc_tx_t | Switch clocks to External clock |
| flash_bist_en_o | out | lc_tx_t | Flush BIST (TAP) Enable |
| dpram_rmf_o | out | dpm_rm_t | Dual Port RAM Read-write Margin Fast |
| dpram_rml_o | out | dpm_rm_t | Dual Port RAM Read-write Margin sLow |
| spram_rm_o | out | spm_rm_t | Single Port RAM Read-write Margin |
| sprgf_rm_o | out | spm_rm_t | Single Port Reg-File Read-write Margin |
| sprom_rm_o | out | spm_rm_t | Single Port ROM Read-write Margin |
| dft_scan_md_o | out | lc_tx_t | Scan Mode output |
| scan_shift_en_o | out | logic | Scan Shift Enable output |
| scan_reset_no | out | logic | Scan Reset output |
Regulators & PDM Logic (VCC)
System Clock (Always ON)
USB Clock (Always ON)
AON Clock (Always ON)
IO Clock (Always ON)
RNG (Always ON)
This design unit is implemented in ast_pkg.sv
This file depends on: top_pkg.sv
of ast_pkg
This design unit is implemented in clkmgr_pkg.sv
clkmgr_pkg
This design unit is implemented in edn_pkg.sv
This file depends on: entropy_src_pkg.sv
This design unit is implemented in entropy_src_pkg.sv
This design unit is implemented in jtag_mux.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumIOs | int | 32 | |
| TieOffValues | [NumIOs-1:0] logic | '0 | |
| JtagEnIdx | int | 0 | Pin to enable JTAG. This is only sampled but not fully muxed. |
| JtagEnPolarity | bit | 1'b1 | |
| TckIdx | int | 0 | These signals are fully muxed and tied off if not in use. |
| TmsIdx | int | 0 | |
| TrstIdx | int | 0 | |
| SrstIdx | int | 0 | |
| TdiIdx | int | 0 | |
| TdoIdx | int | 0 | |
| UsbDpPuIdx | int | 0 | Indices for USB breakout (this is a Bronze workaround) |
| UsbDnPuIdx | int | 0 | |
| UsbDIdx | int | 0 | |
| ConnectUSB | bit | 0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| jtag_tck_o | out | logic | To JTAG inside core |
| jtag_tms_o | out | logic | |
| jtag_trst_no | out | logic | |
| jtag_srst_no | out | logic | |
| jtag_tdi_o | out | logic | |
| jtag_tdo_i | in | logic | |
| out_core_i | in | [NumIOs-1:0] logic | To core side |
| oe_core_i | in | [NumIOs-1:0] logic | |
| in_core_o | out | [NumIOs-1:0] logic | |
| out_padring_o | out | [NumIOs-1:0] logic | To padring side |
| oe_padring_o | out | [NumIOs-1:0] logic | |
| in_padring_i | in | [NumIOs-1:0] logic | |
| usb_pullup_p_en_o | out | logic | USB breakouts for bronze |
| usb_pullup_n_en_o | out | logic | |
| usb_diff_input_i | in | logic |
This design unit is implemented in lc_ctrl_pkg.sv
This file depends on: lc_ctrl_state_pkg.sv, prim_util_pkg.sv
This design unit is implemented in otp_ctrl_pkg.sv
This file depends on: lc_ctrl_state_pkg.sv, prim_util_pkg.sv, otp_ctrl_reg_pkg.sv
This design unit is implemented in padring.sv
This file depends on: pinmux_reg_pkg.sv, prim_pad_wrapper.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| ConnectClk | bit | 1 | This allows to selectively connect Pad instances. unconnected inputs are tied to 0, unconnected outputs are high-z. |
| ConnectRst | bit | 1 | |
| ConnectCc | [1:0] bit | '1 | |
| ConnectMioIn | [NMioPads-1:0] bit | '1 | |
| ConnectMioOut | [NMioPads-1:0] bit | '1 | |
| ConnectDioIn | [NDioPads-1:0] bit | '1 | |
| ConnectDioOut | [NDioPads-1:0] bit | '1 | |
| MioPadVariant | [1:0] [NMioPads-1:0] bit | '0 | 0: bidir, 1: input, 2: tolerant, 3: open drain |
| DioPadVariant | [1:0] [NDioPads-1:0] bit | '0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_pad_i | in | logic | pad input |
| rst_pad_ni | in | logic | |
| clk_o | out | logic | to clocking/reset infrastructure |
| rst_no | out | logic | |
| cc1_i | in | logic | pads for dcd. |
| cc2_i | in | logic | |
| mio_pad_io | inout | [NMioPads-1:0] logic | pads |
| dio_pad_io | inout | [NDioPads-1:0] logic | |
| mio_in_o | out | [NMioPads-1:0] logic | muxed IO signals coming from pinmux |
| mio_out_i | in | [NMioPads-1:0] logic | |
| mio_oe_i | in | [NMioPads-1:0] logic | |
| dio_in_o | out | [NDioPads-1:0] logic | dedicated IO signals coming from peripherals |
| dio_out_i | in | [NDioPads-1:0] logic | |
| dio_oe_i | in | [NDioPads-1:0] logic | |
| mio_attr_i | in | [AttrDw-1:0] [NMioPads-1:0] logic | pad attributes from top level instance |
| dio_attr_i | in | [AttrDw-1:0] [NDioPads-1:0] logic |
This design unit is implemented in pinmux_reg_pkg.sv
This design unit is implemented in prim_usb_diff_rx.sv
This file depends on: prim_generic_usb_diff_rx.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| CalibW | int | 32 |
| Name | Direction | Type | Description |
|---|---|---|---|
| input_pi | in | logic | differential input |
| input_ni | in | logic | differential input |
| input_en_i | in | logic | input buffer enable |
| core_pok_i | in | logic | core power indication at VCC level |
| pullup_p_en_i | in | logic | pullup enable for P |
| pullup_n_en_i | in | logic | pullup enable for N |
| calibration_i | in | [CalibW-1:0] logic | calibration input |
| input_o | out | logic | output of differential input buffer |
This design unit is implemented in pwrmgr_pkg.sv
This file depends on: pwrmgr_reg_pkg.sv
pwrmgr_pkg
This design unit is implemented in rstmgr_pkg.sv
rstmgr_pkg
This design unit is implemented in sensor_ctrl_reg_pkg.sv
This design unit is implemented in tlul_pkg.sv
This file depends on: top_pkg.sv
This design unit is implemented in top_earlgrey.sv
This file depends on: usbdev_pkg.sv, csrng.sv, uvm_pkg.sv, otp_ctrl_pkg.sv, flash_ctrl.sv, tlul_pkg.sv, otp_ctrl.sv, flash_phy.sv, aon_timer.sv, ibex_pkg.sv, rv_core_ibex.sv, keymgr_pkg.sv, rstmgr.sv, clkmgr.sv, dm_pkg.sv, gpio.sv, rv_core_ibex_pkg.sv, tl_main_pkg.sv, otp_ctrl_part_pkg.sv, rv_dm.sv, xbar_main.sv, prim_ram_1p_scr.sv, tlul_adapter_sram.sv, pwrmgr.sv, xbar_peri.sv, aes.sv, keymgr.sv, edn.sv, aes_pkg.sv, edn_pkg.sv, alert_handler.sv, otbn_pkg.sv, pinmux_reg_pkg.sv, entropy_src_pkg.sv, csrng_pkg.sv, jtag_pkg.sv, uart.sv, usbdev.sv, alert_pkg.sv, pinmux.sv, pwrmgr_pkg.sv, prim_rom_adv.sv, otbn.sv, sensor_ctrl.sv, kmac.sv, rstmgr_pkg.sv, spi_device.sv, top_earlgrey_rnd_cnst_pkg.sv, entropy_src.sv, lc_ctrl_pkg.sv, rv_plic.sv, hmac.sv, prim_esc_pkg.sv, aes_reg_pkg.sv, sram_ctrl_pkg.sv, top_pkg.sv, clkmgr_pkg.sv, spi_host.sv, pattgen.sv, ast_pkg.sv, i2c.sv, rv_timer.sv, flash_ctrl_pkg.sv, prim_alert_pkg.sv, sram_ctrl.sv, lc_ctrl.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| SramCtrlRetAonInstrExec | bit | 1 | Auto-inferred parameters |
| AesMasking | bit | 1'b1 | |
| AesSBoxImpl | sbox_impl_e | aes_pkg::SBoxImplDom | |
| SecAesStartTriggerDelay | int | 0 | |
| SecAesAllowForcingMasks | bit | 1'b0 | |
| KmacEnMasking | bit | 0 | |
| KmacReuseShare | int | 0 | |
| CsrngSBoxImpl | sbox_impl_e | aes_pkg::SBoxImplCanright | |
| SramCtrlMainInstrExec | bit | 1 | |
| OtbnRegFile | regfile_e | otbn_pkg::RegFileFF | |
| IbexRegFile | regfile_e | ibex_pkg::RegFileFF | Manually defined parameters |
| IbexICache | bit | 1 | |
| IbexPipeLine | bit | 0 | |
| BootRomInitFile | unknown | "" | |
| JTAG_IDCODE | [31:0] logic | { 4'h0, 16'h4F54, 11'h426, 1'b1 } | JTAG IDCODE for development versions of this code. Manufacturers of OpenTitan chips must replace this code with one of their own IDs. Field structure as defined in the IEEE 1149.1 (JTAG) specification, section 12.1.1. |
| Name | Direction | Type | Description |
|---|---|---|---|
| rst_ni | in | logic | Reset, clocks defined as part of intermodule |
| jtag_tck_i | in | logic | JTAG interface |
| jtag_tms_i | in | logic | |
| jtag_trst_ni | in | logic | |
| jtag_tdi_i | in | logic | |
| jtag_tdo_o | out | logic | |
| mio_in_i | in | [43:0] logic | Multiplexed I/O |
| mio_out_o | out | [43:0] logic | |
| mio_oe_o | out | [43:0] logic | |
| dio_in_i | in | [20:0] logic | Dedicated I/O |
| dio_out_o | out | [20:0] logic | |
| dio_oe_o | out | [20:0] logic | |
| mio_attr_o | out | [pinmux_reg_pkg::AttrDw-1:0] [pinmux_reg_pkg::NMioPads-1:0] logic | pad attributes to padring |
| dio_attr_o | out | [pinmux_reg_pkg::AttrDw-1:0] [pinmux_reg_pkg::NDioPads-1:0] logic | |
| clk_main_i | in | logic | Inter-module Signal External type |
| clk_io_i | in | logic | |
| clk_usb_i | in | logic | |
| clk_aon_i | in | logic | |
| clk_main_jitter_en_o | out | logic | |
| pwrmgr_ast_req_o | out | pwr_ast_req_t | |
| pwrmgr_ast_rsp_i | in | pwr_ast_rsp_t | |
| sensor_ctrl_ast_alert_req_i | in | ast_alert_req_t | |
| sensor_ctrl_ast_alert_rsp_o | out | ast_alert_rsp_t | |
| sensor_ctrl_ast_status_i | in | ast_status_t | |
| usbdev_usb_ref_val_o | out | logic | |
| usbdev_usb_ref_pulse_o | out | logic | |
| ast_tl_req_o | out | tl_h2d_t | |
| ast_tl_rsp_i | in | tl_d2h_t | |
| otp_ctrl_otp_ast_pwr_seq_o | out | otp_ast_req_t | |
| otp_ctrl_otp_ast_pwr_seq_h_i | in | otp_ast_rsp_t | |
| flash_bist_enable_i | in | lc_tx_t | |
| flash_power_down_h_i | in | logic | |
| flash_power_ready_h_i | in | logic | |
| flash_test_mode_a_i | in | [3:0] logic | |
| flash_test_voltage_h_i | in | logic | |
| es_rng_req_o | out | entropy_src_rng_req_t | |
| es_rng_rsp_i | in | entropy_src_rng_rsp_t | |
| lc_clk_byp_req_o | out | lc_tx_t | |
| lc_clk_byp_ack_i | in | lc_tx_t | |
| ast_edn_edn_req_i | in | edn_req_t | |
| ast_edn_edn_rsp_o | out | edn_rsp_t | |
| clks_ast_o | out | clkmgr_ast_out_t | |
| rsts_ast_o | out | rstmgr_ast_out_t | |
| scan_rst_ni | in | logic | reset used for test mode |
| scan_en_i | in | logic | |
| scanmode_i | in | lc_tx_t | lc_ctrl_pkg::On for Scan |
processor core
TL-UL Crossbar
This design unit is implemented in top_earlgrey_pkg.sv
This design unit is implemented in top_pkg.sv
This design unit is implemented in adc.sv
This file depends on: ana_pkg.sv, uvm_pkg.sv
of adc
| Name | Type | Default Value | Description |
|---|---|---|---|
| AdcCnvtClks | int | 22 | JL TODO: Update to actual convertion clock |
| AdcChannels | int | 2 | ADC number of Channels |
| AdcDataWidth | int | 10 |
| Name | Direction | Type | Description |
|---|---|---|---|
| adc_a0_ai | in | logic | ADC A0 Analog Input |
| adc_a1_ai | in | logic | ADC A1 Analog Input |
| adc_chnsel_i | in | [AdcChannels-1:0] logic | Onehot value only for selection |
| adc_pd_i | in | logic | ADC Power Down |
| clk_adc_i | in | logic | ADC Clock (aon_clk - 200KHz) |
| rst_adc_ni | in | logic | ADC Reset active low |
| adc_d_o | out | [AdcDataWidth-1:0] logic | ADC 10-bit Data Output |
| adc_d_val_o | out | logic | ADC Data Valid Output |
This design unit is implemented in aes.sv
This file depends on: aes_reg_top.sv, uvm_pkg.sv, tlul_pkg.sv, prim_alert_pkg.sv, aes_pkg.sv, prim_alert_sender.sv, aes_core.sv, aes_reg_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AES192Enable | bit | 1 | Can be 0 (disable), or 1 (enable). |
| Masking | bit | 0 | Can be 0 (no masking), or 1 (first-order masking) of the cipher core. Masking requires the use of a masked S-Box, see SBoxImpl parameter. Note: currently, constant masks are used, this is of course not secure. |
| SBoxImpl | sbox_impl_e | SBoxImplLut | See aes_pkg.sv |
| SecStartTriggerDelay | int | 0 | Manual start trigger delay, useful for SCA measurements. A value of e.g. 40 allows the processor to go into sleep before AES starts operation. |
| SecAllowForcingMasks | bit | 0 | Allow forcing masks to 0 using FORCE_ZERO_MASK bit in Control Register. Useful for SCA only. |
| AlertAsyncOn | [NumAlerts-1:0] logic | {NumAlerts{1'b1}} | |
| RndCnstClearingLfsrSeed | clearing_lfsr_seed_t | RndCnstClearingLfsrSeedDefault | |
| RndCnstClearingLfsrPerm | clearing_lfsr_perm_t | RndCnstClearingLfsrPermDefault | |
| RndCnstMaskingLfsrSeed | masking_lfsr_seed_t | RndCnstMaskingLfsrSeedDefault | |
| RndCnstMskgChunkLfsrPerm | mskg_chunk_lfsr_perm_t | RndCnstMskgChunkLfsrPermDefault |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| idle_o | out | logic | Idle indicator for clock manager |
| tl_i | in | tl_h2d_t | Bus interface |
| tl_o | out | tl_d2h_t | |
| alert_rx_i | in | [NumAlerts-1:0] alert_rx_t | Alerts |
| alert_tx_o | out | [NumAlerts-1:0] alert_tx_t |
This design unit is implemented in aes_reg_pkg.sv
This design unit is implemented in alert.sv
This file depends on: ast_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| alert_in_i | in | ast_dif_t | |
| alert_trig_i | in | ast_dif_t | |
| alert_ack_i | in | ast_dif_t | |
| alert_req_o | out | ast_dif_t |
This design unit is implemented in alert_handler.sv
This file depends on: prim_esc_sender.sv, uvm_pkg.sv, alert_handler_class.sv, prim_edn_req.sv, alert_pkg.sv, tlul_pkg.sv, alert_handler_accu.sv, prim_alert_receiver.sv, alert_handler_esc_timer.sv, alert_handler_ping_timer.sv, prim_alert_pkg.sv, edn_pkg.sv, alert_handler_reg_wrap.sv, prim_esc_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RndCnstLfsrSeed | lfsr_seed_t | RndCnstLfsrSeedDefault | Compile time random constants, to be overriden by topgen. |
| RndCnstLfsrPerm | lfsr_perm_t | RndCnstLfsrPermDefault |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clk_edn_i | in | logic | |
| rst_edn_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface (device) |
| tl_o | out | tl_d2h_t | |
| intr_classa_o | out | logic | Interrupt Requests |
| intr_classb_o | out | logic | |
| intr_classc_o | out | logic | |
| intr_classd_o | out | logic | |
| crashdump_o | out | alert_crashdump_t | State information for HW crashdump |
| edn_o | out | edn_req_t | Entropy Input |
| edn_i | in | edn_rsp_t | |
| alert_tx_i | in | [NAlerts-1:0] alert_tx_t | Alert Sources |
| alert_rx_o | out | [NAlerts-1:0] alert_rx_t | |
| esc_rx_i | in | [N_ESC_SEV-1:0] esc_rx_t | Escalation outputs |
| esc_tx_o | out | [N_ESC_SEV-1:0] esc_tx_t |
This module pings for entropy excessively at the moment, but this will be addressed later using a refresh rate
This design unit is implemented in alert_pkg.sv
This file depends on: alert_handler_reg_pkg.sv
This design unit is implemented in ana_pkg.sv
of ana_pkg
This design unit is implemented in aon_clk.sv
This file depends on: aon_osc.sv
of aon_clk
| Name | Type | Default Value | Description |
|---|---|---|---|
| AON_EN_RDLY | time | 5us |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_src_aon_en_i | in | logic | AON Source Clock Enable |
| clk_aon_pd_ni | in | logic | AON Clock Power-down |
| rst_aon_clk_ni | in | logic | AON Clock Logic reset |
| vcore_pok_h_i | in | logic | VCORE POK @3.3V (for OSC) |
| clk_src_aon_o | out | logic | AON Source Clock |
| clk_src_aon_val_o | out | logic | AON Source Clock Valid |
This design unit is implemented in aon_timer.sv
This file depends on: aon_timer_reg_pkg.sv, prim_lc_sync.sv, aon_timer_reg_top.sv, aon_timer_core.sv, prim_pulse_sync.sv, prim_intr_hw.sv, tlul_pkg.sv, prim_fifo_async.sv, lc_ctrl_pkg.sv, prim_sync_slow_fast.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AON_WKUP | int | 0 | |
| AON_WDOG | int | 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| clk_aon_i | in | logic | |
| rst_ni | in | logic | |
| rst_aon_ni | in | logic | |
| tl_i | in | tl_h2d_t | TLUL interface on clk_i domain |
| tl_o | out | tl_d2h_t | |
| lc_escalate_en_i | in | lc_tx_t | clk_i domain |
| intr_wkup_timer_expired_o | out | logic | |
| intr_wdog_timer_bark_o | out | logic | |
| sleep_mode_i | in | logic | TODO where will this come from? |
| aon_timer_wkup_req_o | out | logic | |
| aon_timer_rst_req_o | out | logic |
Register read values sampled into clk_i domain. These are sampled with a special slow to fast synchronizer which captures the value on the negative edge of the slow clock.
wkup_ctrl
wkup_thold
wkup_count
wdog_ctrl
wdog_bark_thold
wdog_bite_thold
wdog_count
registers instantiation
Lifecycle sync
Synchronize the interrupt pulses from the counters into the clk_i domain.
This design unit is implemented in ast_reg_pkg.sv
This design unit is implemented in ast_reg_top.sv
This file depends on: prim_subreg.sv, uvm_pkg.sv, tlul_adapter_reg.sv, tlul_pkg.sv, ast_reg_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 4 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | ast_reg2hw_t | Write |
| hw2reg | in | ast_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Ffield0: 0:0
Ffield1: 1:1
Ffield4: 4:4
Ffield15_8: 15:8
This design unit is implemented in clkmgr.sv
This file depends on: uvm_pkg.sv, prim_lc_sync.sv, clkmgr_pkg.sv, tlul_pkg.sv, prim_clock_gating.sv, clkmgr_reg_top.sv, prim_clock_gating_sync.sv, pwrmgr_pkg.sv, prim_lc_sender.sv, prim_flop_2sync.sv, prim_clock_div.sv, clkmgr_reg_pkg.sv, lc_ctrl_pkg.sv, prim_clock_buf.sv
clkmgr
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Primary module control clocks and resets This drives the register interface |
| rst_ni | in | logic | |
| clk_main_i | in | logic | System clocks and resets These are the source clocks for the system |
| rst_main_ni | in | logic | |
| clk_io_i | in | logic | |
| rst_io_ni | in | logic | |
| clk_usb_i | in | logic | |
| rst_usb_ni | in | logic | |
| clk_aon_i | in | logic | |
| rst_io_div2_ni | in | logic | Resets for derived clocks clocks are derived locally |
| rst_io_div4_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface |
| tl_o | out | tl_d2h_t | |
| pwr_i | in | pwr_clk_req_t | pwrmgr interface |
| pwr_o | out | pwr_clk_rsp_t | |
| scanmode_i | in | lc_tx_t | dft interface |
| idle_i | in | [3:0] logic | idle hints |
| ast_clk_bypass_ack_i | in | lc_tx_t | clock bypass control |
| lc_clk_bypass_ack_o | out | lc_tx_t | |
| jitter_en_o | out | logic | jittery enable |
| clocks_ast_o | out | clkmgr_ast_out_t | clock output interface |
| clocks_o | out | clkmgr_out_t |
Feed through clocks Feed through clocks do not actually need to be in clkmgr, as they are completely untouched. The only reason they are here is for easier bundling management purposes through clocks_o
Sync clkmgr domain for feedback to pwrmgr. Since the signal is combo / converged on the other side, de-bounce the signal prior to output
This design unit is implemented in csrng.sv
This file depends on: csrng_pkg.sv, entropy_src_pkg.sv, csrng_reg_top.sv, uvm_pkg.sv, csrng_core.sv, tlul_pkg.sv, prim_alert_pkg.sv, aes_pkg.sv, csrng_reg_pkg.sv, lc_ctrl_pkg.sv, prim_alert_sender.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| SBoxImpl | sbox_impl_e | aes_pkg::SBoxImplLut | |
| AlertAsyncOn | [NumAlerts-1:0] logic | {NumAlerts{1'b1}} | |
| NHwApps | int | 2 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Tilelink Bus Interface |
| tl_o | out | tl_d2h_t | |
| efuse_sw_app_enable_i | in | logic | Efuse Interface |
| lc_hw_debug_en_i | in | lc_tx_t | Lifecycle broadcast inputs |
| entropy_src_hw_if_o | out | entropy_src_hw_if_req_t | Entropy Interface |
| entropy_src_hw_if_i | in | entropy_src_hw_if_rsp_t | |
| csrng_cmd_i | in | [NHwApps-1:0] csrng_req_t | Application Interfaces |
| csrng_cmd_o | out | [NHwApps-1:0] csrng_rsp_t | |
| alert_rx_i | in | [NumAlerts-1:0] alert_rx_t | Alerts |
| alert_tx_o | out | [NumAlerts-1:0] alert_tx_t | |
| intr_cs_cmd_req_done_o | out | logic | Interrupts |
| intr_cs_entropy_req_o | out | logic | |
| intr_cs_hw_inst_exc_o | out | logic | |
| intr_cs_fatal_err_o | out | logic |
This design unit is implemented in csrng_pkg.sv
This file depends on: entropy_src_pkg.sv
This design unit is implemented in dm_pkg.sv
This design unit is implemented in edn.sv
This file depends on: csrng_pkg.sv, edn_core.sv, uvm_pkg.sv, edn_reg_top.sv, edn_reg_pkg.sv, tlul_pkg.sv, prim_alert_pkg.sv, edn_pkg.sv, prim_alert_sender.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumEndPoints | int | 4 | |
| AlertAsyncOn | [NumAlerts-1:0] logic | {NumAlerts{1'b1}} | |
| BootInsCmd | int | 32'h0000_0001 | |
| BootGenCmd | int | 32'h0000_3003 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Tilelink Bus registers |
| tl_o | out | tl_d2h_t | |
| edn_i | in | [NumEndPoints-1:0] edn_req_t | EDN interfaces |
| edn_o | out | [NumEndPoints-1:0] edn_rsp_t | |
| csrng_cmd_o | out | csrng_req_t | CSRNG Application Interface |
| csrng_cmd_i | in | csrng_rsp_t | |
| alert_rx_i | in | [NumAlerts-1:0] alert_rx_t | Alerts |
| alert_tx_o | out | [NumAlerts-1:0] alert_tx_t | |
| intr_edn_cmd_req_done_o | out | logic | Interrupts |
| intr_edn_fatal_err_o | out | logic |
This design unit is implemented in entropy.sv
This file depends on: prim_generic_flop_2sync.sv, edn_pkg.sv, prim_packer_fifo.sv
of entropy
| Name | Type | Default Value | Description |
|---|---|---|---|
| EntropyRateWidth | int | 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| entropy_rsp_i | in | edn_rsp_t | Entropy Response |
| entropy_rate_i | in | [EntropyRateWidth-1:0] logic | Entropy Rate |
| clk_ast_es_i | in | logic | Entropy Clock |
| rst_ast_es_ni | in | logic | Entropy Reset |
| clk_src_sys_en_i | in | logic | System Source Clock Enable |
| clk_src_sys_jen_i | in | logic | System Source Clock Jitter Enable |
| entropy_req_o | out | edn_req_t | Entropy Request |
This design unit is implemented in entropy_src.sv
This file depends on: entropy_src_pkg.sv, entropy_src_reg_top.sv, uvm_pkg.sv, entropy_src_reg_pkg.sv, tlul_pkg.sv, prim_alert_pkg.sv, prim_alert_sender.sv, entropy_src_core.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AlertAsyncOn | [NumAlerts-1:0] logic | {NumAlerts{1'b1}} | |
| EsFifoDepth | int | 2 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface |
| tl_o | out | tl_d2h_t | |
| efuse_es_sw_reg_en_i | in | logic | Efuse Interface |
| entropy_src_hw_if_i | in | entropy_src_hw_if_req_t | Entropy Interface |
| entropy_src_hw_if_o | out | entropy_src_hw_if_rsp_t | |
| entropy_src_rng_o | out | entropy_src_rng_req_t | RNG Interface |
| entropy_src_rng_i | in | entropy_src_rng_rsp_t | |
| entropy_src_xht_o | out | entropy_src_xht_req_t | External Health Test Interface |
| entropy_src_xht_i | in | entropy_src_xht_rsp_t | |
| alert_rx_i | in | [NumAlerts-1:0] alert_rx_t | Alerts |
| alert_tx_o | out | [NumAlerts-1:0] alert_tx_t | |
| intr_es_entropy_valid_o | out | logic | Interrupts |
| intr_es_health_test_failed_o | out | logic | |
| intr_es_fatal_err_o | out | logic |
This design unit is implemented in flash_ctrl.sv
This file depends on: jtag_pkg.sv, uvm_pkg.sv, top_pkg.sv, prim_lc_sync.sv, flash_ctrl_reg_top.sv, prim_lfsr.sv, flash_mp.sv, otp_ctrl_pkg.sv, tlul_pkg.sv, flash_ctrl_rd.sv, prim_alert_sender.sv, pwrmgr_pkg.sv, tlul_adapter_sram.sv, prim_flop.sv, flash_ctrl_erase.sv, flash_ctrl_info_cfg.sv, flash_ctrl_arb.sv, flash_ctrl_prog.sv, flash_ctrl_pkg.sv, prim_fifo_sync.sv, prim_alert_pkg.sv, flash_ctrl_reg_pkg.sv, lc_ctrl_pkg.sv, flash_ctrl_lcmgr.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AlertAsyncOn | logic | 1'b1 | |
| RndCnstAddrKey | flash_key_t | RndCnstAddrKeyDefault | |
| RndCnstDataKey | flash_key_t | RndCnstDataKeyDefault | |
| RndCnstLfsrSeed | lfsr_seed_t | RndCnstLfsrSeedDefault | |
| RndCnstLfsrPerm | lfsr_perm_t | RndCnstLfsrPermDefault | |
| InfoBits | int | $bits(info_page_cfg_t) * InfosPerBank |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clk_otp_i | in | logic | |
| rst_otp_ni | in | logic | |
| lc_creator_seed_sw_rw_en_i | in | lc_tx_t | life cycle interface |
| lc_owner_seed_sw_rw_en_i | in | lc_tx_t | |
| lc_iso_part_sw_rd_en_i | in | lc_tx_t | |
| lc_iso_part_sw_wr_en_i | in | lc_tx_t | |
| lc_seed_hw_rd_en_i | in | lc_tx_t | |
| tl_i | in | tl_h2d_t | Bus Interface |
| tl_o | out | tl_d2h_t | |
| flash_i | in | flash_rsp_t | Flash Interface |
| flash_o | out | flash_req_t | |
| otp_o | out | flash_otp_key_req_t | otp/lc/pwrmgr/keymgr Interface |
| otp_i | in | flash_otp_key_rsp_t | |
| rma_req_i | in | lc_tx_t | |
| rma_seed_i | in | lc_flash_rma_seed_t | |
| rma_ack_o | out | lc_tx_t | |
| pwrmgr_i | in | pwr_flash_req_t | |
| pwrmgr_o | out | pwr_flash_rsp_t | |
| keymgr_o | out | keymgr_flash_t | |
| cio_tck_i | in | logic | IOs |
| cio_tms_i | in | logic | |
| cio_tdi_i | in | logic | |
| cio_tdo_en_o | out | logic | |
| cio_tdo_o | out | logic | |
| intr_prog_empty_o | out | logic | Program fifo is empty |
| intr_prog_lvl_o | out | logic | Program fifo is empty |
| intr_rd_full_o | out | logic | Read fifo is full |
| intr_rd_lvl_o | out | logic | Read fifo is full |
| intr_op_done_o | out | logic | Requested flash operation (wr/erase) done |
| alert_rx_i | in | [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_rx_t | Alerts |
| alert_tx_o | out | [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_t |
Register module
synchronize enables into local domain
flash control arbitration between softawre / harware interfaces
hardware interface
tlul adapter represents software's access interface to flash
Read handler is consumer of rd_fifo
Erase handler does not consume fifo
Flash memory Properties Memory property is page based and thus should use phy addressing This should move to flash_phy long term
This design unit is implemented in flash_ctrl_pkg.sv
This file depends on: jtag_pkg.sv, top_pkg.sv, prim_util_pkg.sv, tlul_pkg.sv, flash_ctrl_reg_pkg.sv, edn_pkg.sv
This design unit is implemented in flash_phy.sv
This file depends on: jtag_pkg.sv, flash_phy_core.sv, prim_flash.sv, prim_lc_sync.sv, flash_ctrl_pkg.sv, prim_fifo_sync.sv, flash_phy_pkg.sv, flash_ctrl_reg_pkg.sv, lc_ctrl_pkg.sv, flash_mp_data_region_sel.sv
flash_phy
| Name | Type | Default Value | Description |
|---|---|---|---|
| FlashMacroOustanding | int | 1 | Flash macro outstanding refers to how many reads we allow a macro to move ahead of an in order blocking read. Since the data cannot be returned out of order, this simply does the reads in advance and store them in a FIFO |
| SeqFifoDepth | int | FlashMacroOustanding * NumBanks | |
| TotalRegions | int | MpRegions + 1 | Generate host scramble_en indication, broadcasted to all banks |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| host_req_i | in | logic | |
| host_addr_i | in | [BusAddrW-1:0] logic | |
| host_req_rdy_o | out | logic | |
| host_req_done_o | out | logic | |
| host_rdata_o | out | [BusWidth-1:0] logic | |
| host_rderr_o | out | logic | |
| flash_ctrl_i | in | flash_req_t | |
| flash_ctrl_o | out | flash_rsp_t | |
| scanmode_i | in | lc_tx_t | |
| scan_en_i | in | logic | |
| scan_rst_ni | in | logic | |
| flash_power_ready_h_i | in | logic | |
| flash_power_down_h_i | in | logic | |
| flash_test_mode_a_i | in | [3:0] logic | |
| flash_test_voltage_h_i | in | logic | |
| flash_bist_enable_i | in | lc_tx_t | |
| lc_nvm_debug_en_i | in | lc_tx_t |
This fifo holds the expected return order
the region decode only accepts page address
This design unit is implemented in gen_pok.sv
of gen_pok
| Name | Type | Default Value | Description |
|---|---|---|---|
| POK_RDLY | time | 3us | |
| POK_FDLY | time | 500ns |
| Name | Direction | Type | Description |
|---|---|---|---|
| gen_pok_o | out | logic |
This design unit is implemented in gpio.sv
This file depends on: gpio_reg_pkg.sv, uvm_pkg.sv, gpio_reg_top.sv, prim_intr_hw.sv, tlul_pkg.sv, prim_filter_ctr.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| cio_gpio_i | in | [31:0] logic | |
| cio_gpio_o | out | [31:0] logic | |
| cio_gpio_en_o | out | [31:0] logic | |
| intr_gpio_o | out | [31:0] logic |
instantiate interrupt hardware primitive
Register module
This design unit is implemented in hmac.sv
This file depends on: tlul_adapter_sram.sv, hmac_reg_top.sv, uvm_pkg.sv, hmac_pkg.sv, hmac_reg_pkg.sv, prim_intr_hw.sv, prim_fifo_sync.sv, sha2.sv, tlul_pkg.sv, prim_packer.sv, hmac_core.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | |
| tl_o | out | tl_d2h_t | |
| intr_hmac_done_o | out | logic | |
| intr_fifo_empty_o | out | logic | |
| intr_hmac_err_o | out | logic | |
| idle_o | out | logic |
instantiate interrupt hardware primitive
TL ADAPTER SRAM
This design unit is implemented in i2c.sv
This file depends on: i2c_reg_pkg.sv, uvm_pkg.sv, i2c_core.sv, i2c_reg_top.sv, tlul_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface |
| tl_o | out | tl_d2h_t | |
| cio_scl_i | in | logic | Generic IO |
| cio_scl_o | out | logic | |
| cio_scl_en_o | out | logic | |
| cio_sda_i | in | logic | |
| cio_sda_o | out | logic | |
| cio_sda_en_o | out | logic | |
| intr_fmt_watermark_o | out | logic | Interrupts |
| intr_rx_watermark_o | out | logic | |
| intr_fmt_overflow_o | out | logic | |
| intr_rx_overflow_o | out | logic | |
| intr_nak_o | out | logic | |
| intr_scl_interference_o | out | logic | |
| intr_sda_interference_o | out | logic | |
| intr_stretch_timeout_o | out | logic | |
| intr_sda_unstable_o | out | logic | |
| intr_trans_complete_o | out | logic | |
| intr_tx_empty_o | out | logic | |
| intr_tx_nonempty_o | out | logic | |
| intr_tx_overflow_o | out | logic | |
| intr_acq_overflow_o | out | logic | |
| intr_ack_stop_o | out | logic | |
| intr_host_timeout_o | out | logic |
This design unit is implemented in ibex_pkg.sv
Package with constants used by Ibex
This design unit is implemented in io_clk.sv
This file depends on: io_osc.sv
of io_clk
| Name | Type | Default Value | Description |
|---|---|---|---|
| IO_EN_RDLY | time | 5us |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_src_io_en_i | in | logic | IO Source Clock Enable |
| clk_io_pd_ni | in | logic | IO Clock Power-down |
| rst_io_clk_ni | in | logic | IO Clock Logic reset |
| vcore_pok_h_i | in | logic | VCORE POK @3.3V (for OSC) |
| clk_src_io_o | out | logic | IO Source Clock |
| clk_src_io_val_o | out | logic | IO Source Clock Valid |
Clock Oscilator
This design unit is implemented in jtag_pkg.sv
This design unit is implemented in keymgr.sv
This file depends on: keymgr_input_checks.sv, keymgr_reseed_ctrl.sv, uvm_pkg.sv, prim_lc_sync.sv, keymgr_reg_pkg.sv, prim_lfsr.sv, otp_ctrl_pkg.sv, keymgr_cfg_en.sv, otp_ctrl_part_pkg.sv, prim_intr_hw.sv, tlul_pkg.sv, prim_alert_sender.sv, keymgr_kmac_if.sv, keymgr_pkg.sv, flash_ctrl_pkg.sv, prim_alert_pkg.sv, keymgr_ctrl.sv, edn_pkg.sv, keymgr_reg_top.sv, lc_ctrl_pkg.sv, keymgr_sideload_key_ctrl.sv
keymgr
| Name | Type | Default Value | Description |
|---|---|---|---|
| AlertAsyncOn | logic | 1'b1 | |
| RndCnstLfsrSeed | lfsr_seed_t | RndCnstLfsrSeedDefault | |
| RndCnstLfsrPerm | lfsr_perm_t | RndCnstLfsrPermDefault | |
| RndCnstRandPerm | rand_perm_t | RndCnstRandPermDefault | |
| RndCnstRevisionSeed | seed_t | RndCnstRevisionSeedDefault | |
| RndCnstCreatorIdentitySeed | seed_t | RndCnstCreatorIdentitySeedDefault | |
| RndCnstOwnerIntIdentitySeed | seed_t | RndCnstOwnerIntIdentitySeedDefault | |
| RndCnstOwnerIdentitySeed | seed_t | RndCnstOwnerIdentitySeedDefault | |
| RndCnstSoftOutputSeed | seed_t | RndCnstSoftOutputSeedDefault | |
| RndCnstHardOutputSeed | seed_t | RndCnstHardOutputSeedDefault | |
| RndCnstNoneSeed | seed_t | RndCnstNoneSeedDefault | |
| RndCnstAesSeed | seed_t | RndCnstAesSeedDefault | |
| RndCnstHmacSeed | seed_t | RndCnstHmacSeedDefault | |
| RndCnstKmacSeed | seed_t | RndCnstKmacSeedDefault | |
| AdvLfsrCopies | int | AdvDataWidth / 32 | Number of times the lfsr output fits into the inputs |
| IdLfsrCopies | int | IdDataWidth / 32 | |
| GenLfsrCopies | int | GenDataWidth / 32 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clk_edn_i | in | logic | |
| rst_edn_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface |
| tl_o | out | tl_d2h_t | |
| aes_key_o | out | hw_key_req_t | key interface to crypto modules |
| hmac_key_o | out | hw_key_req_t | |
| kmac_key_o | out | hw_key_req_t | |
| kmac_data_o | out | kmac_data_req_t | data interface to/from crypto modules |
| kmac_data_i | in | kmac_data_rsp_t | |
| lc_keymgr_en_i | in | lc_tx_t | the following signals should eventually be wrapped into structs from other modules |
| lc_keymgr_div_i | in | lc_keymgr_div_t | |
| otp_key_i | in | otp_keymgr_key_t | |
| otp_hw_cfg_i | in | otp_hw_cfg_t | |
| flash_i | in | keymgr_flash_t | |
| edn_o | out | edn_req_t | connection to edn |
| edn_i | in | edn_rsp_t | |
| intr_op_done_o | out | logic | interrupts and alerts |
| alert_rx_i | in | [keymgr_reg_pkg::NumAlerts-1:0] alert_rx_t | |
| alert_tx_o | out | [keymgr_reg_pkg::NumAlerts-1:0] alert_tx_t |
key manager registers cannot be changed once an operation starts
software clears the enable hardware restores it upon successful advance
Side load key storage
This design unit is implemented in keymgr_pkg.sv
This file depends on: edn_pkg.sv
This design unit is implemented in kmac.sv
This file depends on: kmac_reg_pkg.sv, uvm_pkg.sv, sha3.sv, kmac_keymgr.sv, kmac_staterd.sv, prim_edn_req.sv, prim_intr_hw.sv, tlul_pkg.sv, kmac_entropy.sv, kmac_core.sv, tlul_adapter_sram.sv, kmac_msgfifo.sv, kmac_pkg.sv, sha3_pkg.sv, keymgr_pkg.sv, kmac_reg_top.sv, edn_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| EnMasking | bit | 1 | EnMasking: Enable masking security hardening inside keccak_round If it is enabled, the result digest will be two set of 1600bit. |
| ReuseShare | bit | 0 | ReuseShare: If set, keccak_round logic only consumes small portion of
entropy, not 1600bit of entropy at every round. It uses adjacent shares
as entropy inside Domain-Oriented Masking AND logic.
This parameter only affects when |
| Share | int | (EnMasking) ? 2 : 1 | Parameters // |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clk_edn_i | in | logic | |
| rst_edn_ni | in | logic | |
| tl_i | in | tl_h2d_t | |
| tl_o | out | tl_d2h_t | |
| keymgr_key_i | in | hw_key_req_t | KeyMgr sideload (secret key) interface |
| keymgr_kdf_i | in | kmac_data_req_t | KeyMgr KDF data path |
| keymgr_kdf_o | out | kmac_data_rsp_t | |
| entropy_o | out | edn_req_t | EDN interface |
| entropy_i | in | edn_rsp_t | |
| intr_kmac_done_o | out | logic | interrupts |
| intr_fifo_empty_o | out | logic | |
| intr_kmac_err_o | out | logic | |
| idle_o | out | logic | Idle signal |
Hash process absorbed interrupt
KMAC core
SHA3 hashing engine
TL Adapter
KeyMgr Mux/Demux
Message FIFO
State (Digest) reader
Register top
This design unit is implemented in lc_ctrl.sv
This file depends on: jtag_pkg.sv, dmi_jtag.sv, uvm_pkg.sv, top_pkg.sv, prim_esc_receiver.sv, prim_lc_sync.sv, lc_ctrl_reg_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, tlul_pkg.sv, prim_alert_sender.sv, pwrmgr_pkg.sv, prim_flop_2sync.sv, lc_ctrl_fsm.sv, lc_ctrl_reg_top.sv, lc_ctrl_state_pkg.sv, prim_clock_mux2.sv, prim_alert_pkg.sv, lc_ctrl_pkg.sv, dm_pkg.sv, prim_esc_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AlertAsyncOn | [NumAlerts-1:0] logic | {NumAlerts{1'b1}} | Enable asynchronous transitions on alerts. |
| IdcodeValue | [31:0] logic | 32'h00000001 | Idcode value for the JTAG. |
| RndCnstLcKeymgrDivInvalid | lc_keymgr_div_t | LcKeymgrDivWidth'(0) | Random netlist constants |
| RndCnstLcKeymgrDivTestDevRma | lc_keymgr_div_t | LcKeymgrDivWidth'(1) | |
| RndCnstLcKeymgrDivProduction | lc_keymgr_div_t | LcKeymgrDivWidth'(2) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface (device) |
| tl_o | out | tl_d2h_t | |
| jtag_i | in | jtag_req_t | JTAG TAP. |
| jtag_o | out | jtag_rsp_t | |
| scanmode_i | in | lc_tx_t | This bypasses the clock inverter inside the JTAG TAP for scanmmode. |
| alert_rx_i | in | [NumAlerts-1:0] alert_rx_t | Alert outputs. |
| alert_tx_o | out | [NumAlerts-1:0] alert_tx_t | |
| esc_wipe_secrets_tx_i | in | esc_rx_t | Escalation inputs (severity 1 and 2). These need not be synchronized since the alert handler is in the same clock domain as the LC controller. |
| esc_wipe_secrets_rx_o | out | esc_tx_t | |
| esc_scrap_state_tx_i | in | esc_rx_t | |
| esc_scrap_state_rx_o | out | esc_tx_t | |
| pwr_lc_i | in | pwr_lc_req_t | Power manager interface (inputs are synced to lifecycle clock domain). |
| pwr_lc_o | out | pwr_lc_rsp_t | |
| lc_otp_program_o | out | lc_otp_program_req_t | Life cycle transition command interface. No sync required since LC and OTP are in the same clock domain. |
| lc_otp_program_i | in | lc_otp_program_rsp_t | |
| lc_otp_token_o | out | lc_otp_token_req_t | Life cycle hashing interface for raw unlock No sync required since LC and OTP are in the same clock domain. |
| lc_otp_token_i | in | lc_otp_token_rsp_t | |
| otp_lc_data_i | in | otp_lc_data_t | OTP broadcast outputs No sync required since LC and OTP are in the same clock domain. |
| lc_dft_en_o | out | lc_tx_t | Life cycle broadcast outputs (all of them are registered). |
| lc_nvm_debug_en_o | out | lc_tx_t | |
| lc_hw_debug_en_o | out | lc_tx_t | |
| lc_cpu_en_o | out | lc_tx_t | |
| lc_creator_seed_sw_rw_en_o | out | lc_tx_t | |
| lc_owner_seed_sw_rw_en_o | out | lc_tx_t | |
| lc_iso_part_sw_rd_en_o | out | lc_tx_t | |
| lc_iso_part_sw_wr_en_o | out | lc_tx_t | |
| lc_seed_hw_rd_en_o | out | lc_tx_t | |
| lc_keymgr_en_o | out | lc_tx_t | |
| lc_escalate_en_o | out | lc_tx_t | |
| lc_check_byp_en_o | out | lc_tx_t | |
| lc_clk_byp_req_o | out | lc_tx_t | Request and feedback to/from clock manager and AST. The ack is synced to the lc clock domain using prim_lc_sync. |
| lc_clk_byp_ack_i | in | lc_tx_t | |
| lc_flash_rma_seed_o | out | lc_flash_rma_seed_t | Request and feedback to/from flash controller. The ack is synced to the lc clock domain using prim_lc_sync. |
| lc_flash_rma_req_o | out | lc_tx_t | |
| lc_flash_rma_ack_i | in | lc_tx_t | |
| lc_keymgr_div_o | out | lc_keymgr_div_t | State group diversification value for keymgr. |
| otp_hw_cfg_i | in | otp_hw_cfg_t | Hardware config input, needed for the DEVICE_ID field. |
This design unit is implemented in lc_ctrl_state_pkg.sv
This file depends on: prim_util_pkg.sv
Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0
Life cycle state encoding definition.
DO NOT EDIT THIS FILE DIRECTLY. It has been generated with $ ./util/design/gen-lc-state-enc.py --seed 10167336684108184581
This design unit is implemented in otbn.sv
This file depends on: uvm_pkg.sv, top_pkg.sv, prim_edn_req.sv, prim_intr_hw.sv, tlul_pkg.sv, prim_util_pkg.sv, otbn_reg_pkg.sv, prim_alert_sender.sv, otbn_core.sv, tlul_adapter_sram.sv, prim_ram_1p_adv.sv, otbn_reg_top.sv, prim_alert_pkg.sv, edn_pkg.sv, otbn_pkg.sv
OpenTitan Big Number Accelerator (OTBN)
| Name | Type | Default Value | Description |
|---|---|---|---|
| RegFile | regfile_e | RegFileFF | |
| AlertAsyncOn | [NumAlerts-1:0] logic | {NumAlerts{1'b1}} | |
| ImemSizeByte | int | int'(otbn_reg_pkg::OTBN_IMEM_SIZE) | The OTBN_*_SIZE parameters are auto-generated by regtool and come from the bus window sizes; they are given in bytes and must be powers of two. |
| DmemSizeByte | int | int'(otbn_reg_pkg::OTBN_DMEM_SIZE) | |
| ImemAddrWidth | int | vbits(ImemSizeByte) | |
| DmemAddrWidth | int | vbits(DmemSizeByte) | |
| ImemSizeWords | int | ImemSizeByte / 4 | |
| ImemIndexWidth | int | vbits(ImemSizeWords) | |
| DmemSizeWords | int | DmemSizeByte / (WLEN / 8) | |
| DmemIndexWidth | int | vbits(DmemSizeWords) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | |
| tl_o | out | tl_d2h_t | |
| idle_o | out | logic | Inter-module signals |
| intr_done_o | out | logic | Interrupts |
| alert_rx_i | in | [NumAlerts-1:0] alert_rx_t | Alerts |
| alert_tx_o | out | [NumAlerts-1:0] alert_tx_t | |
| clk_edn_i | in | logic | EDN clock and interface |
| rst_edn_ni | in | logic | |
| edn_o | out | edn_req_t | |
| edn_i | in | edn_rsp_t |
This synchronizes the data coming from EDN and stacks the 32bit EDN words to achieve an internal entropy width of 256 bit.
This design unit is implemented in otbn_pkg.sv
This design unit is implemented in otp_ctrl.sv
This file depends on: uvm_pkg.sv, prim_edn_req.sv, otp_ctrl_pkg.sv, otp_ctrl_lci.sv, otp_ctrl_reg_pkg.sv, tlul_pkg.sv, prim_alert_sender.sv, otp_ctrl_lfsr_timer.sv, prim_arbiter_tree.sv, pwrmgr_pkg.sv, otp_ctrl_dai.sv, otp_ctrl_reg_top.sv, prim_flop_2sync.sv, otp_ctrl_scrmbl.sv, otp_ctrl_part_buf.sv, prim_arbiter_fixed.sv, lc_ctrl_state_pkg.sv, prim_fifo_sync.sv, lc_ctrl_pkg.sv, prim_lc_sync.sv, otp_ctrl_part_unbuf.sv, otp_ctrl_part_pkg.sv, prim_intr_hw.sv, prim_util_pkg.sv, tlul_adapter_sram.sv, prim_otp.sv, otp_ctrl_kdi.sv, prim_alert_pkg.sv, prim_otp_pkg.sv, edn_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AlertAsyncOn | [NumAlerts-1:0] logic | {NumAlerts{1'b1}} | Enable asynchronous transitions on alerts. |
| RndCnstLfsrSeed | lfsr_seed_t | RndCnstLfsrSeedDefault | Compile time random constants, to be overriden by topgen. |
| RndCnstLfsrPerm | lfsr_perm_t | RndCnstLfsrPermDefault | |
| MemInitFile | unknown | "" | Hexfile file to initialize the OTP macro. Note that the hexdump needs to account for ECC. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | OTP clock |
| rst_ni | in | logic | |
| clk_edn_i | in | logic | EDN clock and interface |
| rst_edn_ni | in | logic | |
| edn_o | out | edn_req_t | |
| edn_i | in | edn_rsp_t | |
| tl_i | in | tl_h2d_t | Bus Interface (device) |
| tl_o | out | tl_d2h_t | |
| intr_otp_operation_done_o | out | logic | Interrupt Requests |
| intr_otp_error_o | out | logic | |
| alert_rx_i | in | [NumAlerts-1:0] alert_rx_t | Alerts |
| alert_tx_o | out | [NumAlerts-1:0] alert_tx_t | |
| otp_ast_pwr_seq_o | out | otp_ast_req_t | Macro-specific power sequencing signals to/from AST. |
| otp_ast_pwr_seq_h_i | in | otp_ast_rsp_t | |
| pwr_otp_i | in | pwr_otp_req_t | Power manager interface (inputs are synced to OTP clock domain) |
| pwr_otp_o | out | pwr_otp_rsp_t | |
| lc_otp_program_i | in | lc_otp_program_req_t | Lifecycle transition command interface |
| lc_otp_program_o | out | lc_otp_program_rsp_t | |
| lc_otp_token_i | in | lc_otp_token_req_t | Lifecycle hashing interface for raw unlock |
| lc_otp_token_o | out | lc_otp_token_rsp_t | |
| lc_creator_seed_sw_rw_en_i | in | lc_tx_t | Lifecycle broadcast inputs |
| lc_seed_hw_rd_en_i | in | lc_tx_t | |
| lc_dft_en_i | in | lc_tx_t | |
| lc_escalate_en_i | in | lc_tx_t | |
| lc_check_byp_en_i | in | lc_tx_t | |
| otp_lc_data_o | out | otp_lc_data_t | OTP broadcast outputs |
| otp_keymgr_key_o | out | otp_keymgr_key_t | |
| flash_otp_key_i | in | flash_otp_key_req_t | Scrambling key requests |
| flash_otp_key_o | out | flash_otp_key_rsp_t | |
| sram_otp_key_i | in | [NumSramKeyReqSlots-1:0] sram_otp_key_req_t | |
| sram_otp_key_o | out | [NumSramKeyReqSlots-1:0] sram_otp_key_rsp_t | |
| otbn_otp_key_i | in | otbn_otp_key_req_t | |
| otbn_otp_key_o | out | otbn_otp_key_rsp_t | |
| otp_hw_cfg_o | out | otp_hw_cfg_t | Hardware config bits |
This synchronizes the data coming from EDN and stacks the 32bit EDN words to achieve an internal entropy width of 64bit.
The OTP interface is arbitrated on a per-cycle basis, meaning that back-to-back transactions can be completely independent.
We can have up to two OTP commands in flight, hence we size this to be 2 deep. The partitions can unconditionally sink requested data.
Note that arbiter decisions do not change when backpressured. Hence, the idx_o signal is guaranteed to remain stable until ack'ed.
This design unit is implemented in otp_ctrl_part_pkg.sv
This file depends on: otp_ctrl_pkg.sv, prim_util_pkg.sv, otp_ctrl_reg_pkg.sv, lc_ctrl_pkg.sv
This design unit is implemented in otp_ctrl_reg_pkg.sv
This design unit is implemented in pattgen.sv
This file depends on: pattgen_reg_top.sv, uvm_pkg.sv, pattgen_core.sv, tlul_pkg.sv, pattgen_reg_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | |
| tl_o | out | tl_d2h_t | |
| cio_pda0_tx_o | out | logic | |
| cio_pcl0_tx_o | out | logic | |
| cio_pda1_tx_o | out | logic | |
| cio_pcl1_tx_o | out | logic | |
| cio_pda0_tx_en_o | out | logic | |
| cio_pcl0_tx_en_o | out | logic | |
| cio_pda1_tx_en_o | out | logic | |
| cio_pcl1_tx_en_o | out | logic | |
| intr_done_ch0_o | out | logic | |
| intr_done_ch1_o | out | logic |
This design unit is implemented in pinmux.sv
This file depends on: pinmux_reg_pkg.sv, jtag_pkg.sv, usbdev_pkg.sv, uvm_pkg.sv, usbdev_aon_wake.sv, pinmux_reg_top.sv, pinmux_pkg.sv, pinmux_wkup.sv, tlul_pkg.sv, lc_ctrl_pkg.sv, pinmux_strap_sampling.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AlignedMuxSize | int | (NMioPads + 2 > NDioPads) ? 2**$clog2(NMioPads + 2) : 2**$clog2(NDioPads) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clk_aon_i | in | logic | Slow always-on clock |
| rst_aon_ni | in | logic | |
| aon_wkup_req_o | out | logic | Wakeup request, running on clk_aon_i |
| usb_wkup_req_o | out | logic | |
| sleep_en_i | in | logic | Sleep enable and strap sample enable from pwrmgr, running on clk_i TODO(#5198): figure out the connections. |
| strap_en_i | in | logic | |
| lc_dft_en_i | in | lc_tx_t | LC signals for TAP qualification |
| lc_hw_debug_en_i | in | lc_tx_t | |
| dft_strap_test_o | out | dft_strap_test_req_t | Sampled values for DFT straps |
| lc_jtag_o | out | jtag_req_t | Qualified JTAG signals for TAPs |
| lc_jtag_i | in | jtag_rsp_t | |
| rv_jtag_o | out | jtag_req_t | |
| rv_jtag_i | in | jtag_rsp_t | |
| dft_jtag_o | out | jtag_req_t | |
| dft_jtag_i | in | jtag_rsp_t | |
| usb_out_of_rst_i | in | logic | Direct USB connection |
| usb_aon_wake_en_i | in | logic | |
| usb_aon_wake_ack_i | in | logic | |
| usb_suspend_i | in | logic | |
| usb_state_debug_o | out | awk_state_t | |
| tl_i | in | tl_h2d_t | Bus Interface (device) |
| tl_o | out | tl_d2h_t | |
| periph_to_mio_i | in | [NMioPeriphOut-1:0] logic | Muxed Peripheral side |
| periph_to_mio_oe_i | in | [NMioPeriphOut-1:0] logic | |
| mio_to_periph_o | out | [NMioPeriphIn-1:0] logic | |
| periph_to_dio_i | in | [NDioPads-1:0] logic | Dedicated Peripheral side |
| periph_to_dio_oe_i | in | [NDioPads-1:0] logic | |
| dio_to_periph_o | out | [NDioPads-1:0] logic | |
| mio_attr_o | out | [AttrDw-1:0] [NMioPads-1:0] logic | Pad side MIOs |
| mio_out_o | out | [NMioPads-1:0] logic | |
| mio_oe_o | out | [NMioPads-1:0] logic | |
| mio_in_i | in | [NMioPads-1:0] logic | |
| dio_attr_o | out | [AttrDw-1:0] [NDioPads-1:0] logic | DIOs |
| dio_out_o | out | [NDioPads-1:0] logic | |
| dio_oe_o | out | [NDioPads-1:0] logic | |
| dio_in_i | in | [NDioPads-1:0] logic |
Dedicated Peripheral side
This design unit is implemented in pinmux_pkg.sv
This design unit is implemented in prim_alert_pkg.sv
This design unit is implemented in prim_esc_pkg.sv
This design unit is implemented in prim_generic_usb_diff_rx.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| CalibW | int | 32 |
| Name | Direction | Type | Description |
|---|---|---|---|
| input_pi | in | logic | differential input |
| input_ni | in | logic | differential input |
| input_en_i | in | logic | input buffer enable |
| core_pok_i | in | logic | core power indication at VCC level |
| pullup_p_en_i | in | logic | pullup enable for P |
| pullup_n_en_i | in | logic | pullup enable for N |
| calibration_i | in | [CalibW-1:0] logic | calibration input |
| input_o | out | logic | output of differential input buffer |
This design unit is implemented in prim_pad_wrapper.sv
This file depends on: prim_xilinx_pad_wrapper.sv, prim_generic_pad_wrapper.sv, prim_pkg.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| Variant | int | 0 | currently ignored |
| AttrDw | int | 10 | |
| WarlOnly | bit | 0 | If set to 1, no pad is instantiated and only warl_o is driven |
| Impl | impl_e | prim_pkg::ImplGeneric |
| Name | Direction | Type | Description |
|---|---|---|---|
| inout_io | inout | logic | bidirectional pad |
| in_o | out | logic | input data |
| ie_i | in | logic | input enable |
| out_i | in | logic | output data |
| oe_i | in | logic | output enable |
| attr_i | in | [AttrDw-1:0] logic | additional attributes |
| warl_o | out | [AttrDw-1:0] logic |
This design unit is implemented in prim_ram_1p_scr.sv
This file depends on: uvm_pkg.sv, prim_ram_1p_adv.sv, prim_util_pkg.sv, prim_subst_perm.sv, prim_prince.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Depth | int | 16*1024 | Needs to be a power of 2 if NumAddrScrRounds > 0. |
| Width | int | 32 | Needs to be byte aligned if byte parity is enabled. |
| DataBitsPerMask | int | 8 | Needs to be set to 8 in case of byte parity. |
| EnableParity | bit | 1 | Enable byte parity. |
| CfgWidth | int | 8 | WTC, RTC, etc |
| NumPrinceRoundsHalf | int | 2 | Scrambling parameters. Note that this needs to be low-latency, hence we have to keep the amount of cipher rounds low. PRINCE has 5 half rounds in its original form, which corresponds to 2*5 + 1 effective rounds. Setting this to 2 halves this to approximately 5 effective rounds. Number of PRINCE half rounds, can be 1..5 |
| NumDiffRounds | int | 2 | Number of extra diffusion rounds. Setting this to 0 to disable diffusion. |
| DiffWidth | int | DataBitsPerMask | This parameter governs the block-width of additional diffusion layers. For intra-byte diffusion, set this parameter to 8. Note that DataBitsPerMask must be a multiple of this parameter. |
| NumAddrScrRounds | int | 2 | Number of address scrambling rounds. Setting this to 0 disables address scrambling. |
| ReplicateKeyStream | bit | 1'b0 | If set to 1, the same 64bit key stream is replicated if the data port is wider than 64bit. If set to 0, the cipher primitive is replicated, and together with a wider nonce input, a unique keystream is generated for the full data width. |
| AddrWidth | int | prim_util_pkg::vbits(Depth) | Derived parameters |
| NumParScr | int | (ReplicateKeyStream) ? 1 : (Width + 63) / 64 | Depending on the data width, we need to instantiate multiple parallel cipher primitives to create a keystream that is wide enough (PRINCE has a block size of 64bit) |
| NumParKeystr | int | (ReplicateKeyStream) ? (Width + 63) / 64 : 1 | |
| DataKeyWidth | int | 128 | This is given by the PRINCE cipher primitive. All parallel cipher modules use the same key, but they use a different IV |
| NonceWidth | int | 64 * NumParScr | Each 64 bit scrambling primitive requires a 64bit IV |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| key_valid_i | in | logic | Key interface. Memory requests will not be granted if key_valid is set to 0. |
| key_i | in | [DataKeyWidth-1:0] logic | |
| nonce_i | in | [NonceWidth-1:0] logic | |
| req_i | in | logic | Interface to TL-UL SRAM adapter |
| gnt_o | out | logic | |
| write_i | in | logic | |
| addr_i | in | [AddrWidth-1:0] logic | |
| wdata_i | in | [Width-1:0] logic | |
| wmask_i | in | [Width-1:0] logic | Needs to be byte-aligned for parity |
| rdata_o | out | [Width-1:0] logic | |
| rvalid_o | out | logic | Read response (rdata_o) is valid |
| rerror_o | out | [1:0] logic | Bit1: Uncorrectable, Bit0: Correctable |
| raddr_o | out | [31:0] logic | Read address for error reporting. |
| cfg_i | in | [CfgWidth-1:0] logic | config |
This design unit is implemented in prim_rom_adv.sv
This file depends on: uvm_pkg.sv, prim_rom.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 32 | Parameters passed on the the ROM primitive. |
| Depth | int | 2048 | 8kB default |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| CfgW | int | 8 | WTC, RTC, etc |
| Aw | int | $clog2(Depth) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | logic | |
| addr_i | in | [Aw-1:0] logic | |
| rvalid_o | out | logic | |
| rdata_o | out | [Width-1:0] logic | |
| cfg_i | in | [CfgW-1:0] logic |
This design unit is implemented in prim_util_pkg.sv
Utility functions
This design unit is implemented in pwrmgr.sv
This file depends on: uvm_pkg.sv, prim_esc_receiver.sv, pwrmgr_cdc.sv, pwrmgr_reg_top.sv, pwrmgr_fsm.sv, pwrmgr_wake_info.sv, prim_intr_hw.sv, tlul_pkg.sv, pwrmgr_reg_pkg.sv, pwrmgr_slow_fsm.sv, pwrmgr_pkg.sv, prim_esc_pkg.sv
pwrmgr
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_slow_i | in | logic | Clocks and resets |
| clk_i | in | logic | |
| rst_slow_ni | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface |
| tl_o | out | tl_d2h_t | |
| pwr_ast_i | in | pwr_ast_rsp_t | AST interface |
| pwr_ast_o | out | pwr_ast_req_t | |
| pwr_rst_i | in | pwr_rst_rsp_t | rstmgr interface |
| pwr_rst_o | out | pwr_rst_req_t | |
| pwr_clk_o | out | pwr_clk_req_t | clkmgr interface |
| pwr_clk_i | in | pwr_clk_rsp_t | |
| pwr_otp_i | in | pwr_otp_rsp_t | otp interface |
| pwr_otp_o | out | pwr_otp_req_t | |
| pwr_lc_i | in | pwr_lc_rsp_t | life cycle interface |
| pwr_lc_o | out | pwr_lc_req_t | |
| pwr_flash_o | out | pwr_flash_req_t | flash interface |
| pwr_flash_i | in | pwr_flash_rsp_t | |
| pwr_cpu_i | in | pwr_cpu_t | processor interface |
| wakeups_i | in | [NumWkups-1:0] logic | peripherals wakeup and reset requests |
| rstreqs_i | in | [NumRstReqs-1:0] logic | |
| esc_rst_tx_i | in | esc_tx_t | escalation interface |
| esc_rst_rx_o | out | esc_rx_t | |
| intr_wakeup_o | out | logic |
This interrupt is asserted whenever the fast FSM transitions into active state. However, it does not assert during POR
This design unit is implemented in pwrmgr_reg_pkg.sv
This design unit is implemented in rglts_pdm_3p3v.sv
This file depends on: ast_pkg.sv, gen_pok.sv
of rglts_pdm_3p3v
| Name | Type | Default Value | Description |
|---|---|---|---|
| MRVCC_RDLY | time | 5us | |
| MRVCC_FDLY | time | 100ns | |
| MRPD_RDLY | time | 50us | |
| MRPD_FDLY | time | 1us |
| Name | Direction | Type | Description |
|---|---|---|---|
| vcc_pok_h_i | in | logic | VCC (3.3V) Exist @3.3v |
| vcmain_pok_h_i | in | logic | VCMAIN (1.1v) Exist @3.3v |
| clk_src_aon_h_i | in | logic | AON Clock @3.3v |
| main_pd_h_ni | in | logic | VCMAIN/Regulator Power Down @3.3v |
| otp_power_seq_h_i | in | [1:0] logic | MMR0,24 in @3.3v |
| vcaon_pok_h_o | out | logic | VCAON (1.1v) Exist @3.3v |
| main_pwr_dly_o | out | logic | For modeling only. |
| flash_power_down_h_o | out | logic | |
| flash_power_ready_h_o | out | logic | |
| otp_power_seq_h_o | out | [1:0] logic | MMR0,24 masked by PDM, out (VCC) |
This design unit is implemented in rng.sv
This file depends on: rng_osc.sv
of rng
| Name | Type | Default Value | Description |
|---|---|---|---|
| RNG_EN_RDLY | time | 5us | |
| EntropyStreams | int | 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| vcaon_pok_i | in | logic | |
| rng_en_i | in | logic | |
| rng_b_o | out | [EntropyStreams-1:0] logic | |
| rng_val_o | out | logic |
For FPGA, it can be replace with clk_src_aon_o/4 (200K/4=50K)
This design unit is implemented in rstmgr.sv
This file depends on: uvm_pkg.sv, rv_core_ibex_pkg.sv, prim_lc_sync.sv, rstmgr_por.sv, rstmgr_ctrl.sv, alert_pkg.sv, tlul_pkg.sv, pwrmgr_pkg.sv, rstmgr_reg_pkg.sv, prim_flop_2sync.sv, prim_subreg.sv, rstmgr_reg_top.sv, prim_clock_mux2.sv, rstmgr_pkg.sv, lc_ctrl_pkg.sv, rstmgr_crash_info.sv
rstmgr
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Primary module clocks |
| rst_ni | in | logic | this is connected to the top level reset |
| clk_aon_i | in | logic | |
| clk_io_div4_i | in | logic | |
| clk_main_i | in | logic | |
| clk_io_i | in | logic | |
| clk_io_div2_i | in | logic | |
| clk_usb_i | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface |
| tl_o | out | tl_d2h_t | |
| pwr_i | in | pwr_rst_req_t | pwrmgr interface |
| pwr_o | out | pwr_rst_rsp_t | |
| cpu_i | in | rstmgr_cpu_t | cpu related inputs |
| alert_dump_i | in | alert_crashdump_t | Interface to alert handler |
| cpu_dump_i | in | crashdump_t | Interface to cpu crash dump |
| scan_rst_ni | in | logic | dft bypass |
| scanmode_i | in | lc_tx_t | |
| resets_ast_o | out | rstmgr_ast_out_t | reset outputs |
| resets_o | out | rstmgr_out_t |
lc reset sources
sys reset sources
This design unit is implemented in rv_core_ibex.sv
This file depends on: rv_core_ibex_pkg.sv, top_pkg.sv, prim_esc_receiver.sv, prim_lc_sync.sv, ibex_tracer.sv, tlul_pkg.sv, ibex_core.sv, tlul_fifo_sync.sv, prim_flop_2sync.sv, tlul_adapter_host.sv, ibex_pkg.sv, lc_ctrl_pkg.sv, prim_esc_pkg.sv
Ibex RISC-V core
32 bit RISC-V core supporting the RV32I + optionally EMC instruction sets.
Instruction and data bus are 32 bit wide TileLink-UL (TL-UL).
| Name | Type | Default Value | Description |
|---|---|---|---|
| PMPEnable | bit | 1'b0 | |
| PMPGranularity | int | 0 | |
| PMPNumRegions | int | 4 | |
| MHPMCounterNum | int | 10 | |
| MHPMCounterWidth | int | 32 | |
| RV32E | bit | 0 | |
| RV32M | rv32m_e | ibex_pkg::RV32MSingleCycle | |
| RV32B | rv32b_e | ibex_pkg::RV32BNone | |
| RegFile | regfile_e | ibex_pkg::RegFileFF | |
| BranchTargetALU | bit | 1'b1 | |
| WritebackStage | bit | 1'b1 | |
| ICache | bit | 1'b0 | |
| ICacheECC | bit | 1'b0 | |
| BranchPredictor | bit | 1'b0 | |
| DbgTriggerEn | bit | 1'b1 | |
| SecureIbex | bit | 1'b0 | |
| DmHaltAddr | int | 32'h1A110800 | |
| DmExceptionAddr | int | 32'h1A110808 | |
| PipeLine | bit | 1'b0 | |
| FifoPass | bit | PipeLine ? 1'b0 : 1'b1 | if pipeline=1, do not allow pass through and always break the path if pipeline is 0, passthrough the fifo completely |
| FifoDepth | int | PipeLine ? 2 : 0 | |
| NumOutstandingReqs | int | ICache ? 8 : 2 | ICache creates more outstanding transactions |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock and Reset |
| rst_ni | in | logic | |
| clk_esc_i | in | logic | Clock domain for escalation receiver |
| rst_esc_ni | in | logic | |
| test_en_i | in | logic | enable all clock gates for testing |
| hart_id_i | in | [31:0] logic | |
| boot_addr_i | in | [31:0] logic | |
| tl_i_o | out | tl_h2d_t | Instruction memory interface |
| tl_i_i | in | tl_d2h_t | |
| tl_d_o | out | tl_h2d_t | Data memory interface |
| tl_d_i | in | tl_d2h_t | |
| irq_software_i | in | logic | Interrupt inputs |
| irq_timer_i | in | logic | |
| irq_external_i | in | logic | |
| esc_tx_i | in | esc_tx_t | Escalation input for NMI |
| esc_rx_o | out | esc_rx_t | |
| debug_req_i | in | logic | Debug Interface |
| crash_dump_o | out | crashdump_t | Crash dump information |
| fetch_enable_i | in | lc_tx_t | CPU Control Signals |
| core_sleep_o | out | logic |
This design unit is implemented in rv_core_ibex_pkg.sv
This file depends on: top_pkg.sv
This design unit is implemented in rv_dm.sv
This file depends on: jtag_pkg.sv, dm_sba.sv, tlul_adapter_sram.sv, uvm_pkg.sv, tlul_adapter_host.sv, prim_lc_sync.sv, dm_csrs.sv, dm_mem.sv, tlul_pkg.sv, lc_ctrl_pkg.sv, dm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NrHarts | int | 1 | |
| IdcodeValue | [31:0] logic | 32'h 0000_0001 | |
| BusWidth | int | 32 | Currently only 32 bit busses are supported by our TL-UL IP |
| SelectableHarts | [NrHarts-1:0] logic | {NrHarts{1'b1}} | all harts have contiguous IDs |
| DebugHartInfo | hartinfo_t | '{ zero1: '0, nscratch: 2, zero0: 0, dataaccess: 1'b1, datasize: dm::DataCount, dataaddr: dm::DataAddr } | static debug hartinfo |
| AddressWidthWords | int | BusWidth - $clog2(BusWidth/8) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | clock |
| rst_ni | in | logic | asynchronous reset active low, connect PoR |
| hw_debug_en_i | in | lc_tx_t | |
| scanmode_i | in | lc_tx_t | |
| ndmreset_o | out | logic | non-debug module reset |
| dmactive_o | out | logic | debug module is active |
| debug_req_o | out | [NrHarts-1:0] logic | async debug request |
| unavailable_i | in | [NrHarts-1:0] logic | communicate whether the hart is unavailable |
| tl_d_i | in | tl_h2d_t | bus device with debug memory, for an execution based technique |
| tl_d_o | out | tl_d2h_t | |
| tl_h_o | out | tl_h2d_t | bus host, for system bus accesses |
| tl_h_i | in | tl_d2h_t | |
| jtag_req_i | in | jtag_req_t | |
| jtag_rsp_o | out | jtag_rsp_t |
This design unit is implemented in rv_plic.sv
This file depends on: rv_plic_reg_top.sv, rv_plic_gateway.sv, rv_plic_target.sv, uvm_pkg.sv, rv_plic_reg_pkg.sv, tlul_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| SRCW | int | $clog2(NumSrc) | derived parameter |
| MAX_PRIO | int | 3 | |
| PRIOW | int | $clog2(MAX_PRIO+1) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface (device) |
| tl_o | out | tl_d2h_t | |
| intr_src_i | in | [NumSrc-1:0] logic | Interrupt Sources |
| irq_o | out | [NumTarget-1:0] logic | Interrupt notification to targets |
| irq_id_o | out | [SRCW-1:0] logic [NumTarget] | |
| msip_o | out | [NumTarget-1:0] logic |
Gateways //
Register interface //
Limitation of register tool prevents the module from having flexibility to parameters So, signals are manually tied at the top.
This design unit is implemented in rv_timer.sv
This file depends on: rv_timer_reg_pkg.sv, timer_core.sv, uvm_pkg.sv, prim_intr_hw.sv, tlul_pkg.sv, rv_timer_reg_top.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| N_HARTS | int | 1 | |
| N_TIMERS | int | 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | |
| tl_o | out | tl_d2h_t | |
| intr_timer_expired_0_0_o | out | logic |
Register module
This design unit is implemented in sensor_ctrl.sv
This file depends on: ast_pkg.sv, sensor_ctrl_reg_pkg.sv, sensor_ctrl_reg_top.sv, sensor_ctrl_pkg.sv, tlul_pkg.sv, prim_alert_pkg.sv, prim_alert_sender.sv
sensor_ctrl
| Name | Type | Default Value | Description |
|---|---|---|---|
| AsyncOn | logic | 1'b0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Primary module clocks |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface |
| tl_o | out | tl_d2h_t | |
| ast_alert_i | in | ast_alert_req_t | Interface from AST |
| ast_alert_o | out | ast_alert_rsp_t | |
| ast_status_i | in | ast_status_t | |
| alert_rx_i | in | [NumAlerts-1:0] alert_rx_t | Alerts |
| alert_tx_o | out | [NumAlerts-1:0] alert_tx_t |
This design unit is implemented in spi_device.sv
This file depends on: spi_device_reg_pkg.sv, uvm_pkg.sv, prim_lc_sync.sv, prim_sram_arbiter.sv, spi_device_pkg.sv, tlul_pkg.sv, spi_fwmode.sv, prim_clock_inv.sv, prim_fifo_async.sv, spi_fwm_txf_ctrl.sv, tlul_adapter_sram.sv, prim_flop_2sync.sv, prim_clock_mux2.sv, prim_pulse_sync.sv, spi_fwm_rxf_ctrl.sv, spi_p2s.sv, prim_ram_2p_adv.sv, lc_ctrl_pkg.sv, spi_s2p.sv, prim_clock_buf.sv, spi_device_reg_top.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| FifoWidth | int | $bits(spi_byte_t) | |
| FifoDepth | int | 8 | 2 DWords |
| SDW | int | $clog2(SramDw/FifoWidth) | |
| PtrW | int | SramAw + 1 + SDW | |
| AsFifoDepthW | int | $clog2(FifoDepth+1) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Register interface |
| tl_o | out | tl_d2h_t | |
| cio_sck_i | in | logic | SPI Interface |
| cio_csb_i | in | logic | |
| cio_sd_o | out | [3:0] logic | |
| cio_sd_en_o | out | [3:0] logic | |
| cio_sd_i | in | [3:0] logic | |
| intr_rxf_o | out | logic | RX FIFO Full |
| intr_rxlvl_o | out | logic | RX FIFO above level |
| intr_txlvl_o | out | logic | TX FIFO below level |
| intr_rxerr_o | out | logic | RX Frame error |
| intr_rxoverflow_o | out | logic | RX Async FIFO Overflow |
| intr_txunderflow_o | out | logic | TX Async FIFO Underflow |
| scan_clk_i | in | logic | DFT related controls |
| scan_rst_ni | in | logic | |
| scanmode_i | in | lc_tx_t |
rxf_overflow Could trigger lint error for input clock. It's unavoidable due to the characteristics of SPI intf
txf_underflow Could trigger lint error for input clock. It's unavoidable due to the characteristics of SPI intf
FW Mode //
FIFO: Connecting FwMode to SRAM CTRLs
RX Fifo control (FIFO Read port --> SRAM request)
TX Fifo control (SRAM read request --> FIFO write)
Arbiter for FIFOs : Connecting between SRAM Ctrls and SRAM interface
SRAM Wrapper
Register module
This design unit is implemented in spi_host.sv
This file depends on: spi_host_reg_top.sv, spi_host_reg_pkg.sv, tlul_pkg.sv, lc_ctrl_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| scanmode_i | in | lc_tx_t | |
| tl_i | in | tl_h2d_t | Register interface |
| tl_o | out | tl_d2h_t | |
| cio_sck_o | out | logic | SPI Interface |
| cio_sck_en_o | out | logic | |
| cio_csb_o | out | logic | |
| cio_csb_en_o | out | logic | |
| cio_sd_o | out | [3:0] logic | |
| cio_sd_en_o | out | [3:0] logic | |
| cio_sd_i | in | [3:0] logic |
Register module
This design unit is implemented in sram_ctrl.sv
This file depends on: prim_sync_reqack_data.sv, sram_ctrl_pkg.sv, uvm_pkg.sv, prim_lc_sync.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, tlul_pkg.sv, prim_alert_pkg.sv, sram_ctrl_reg_pkg.sv, sram_ctrl_reg_top.sv, lc_ctrl_pkg.sv, prim_alert_sender.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AlertAsyncOn | [NumAlerts-1:0] logic | {NumAlerts{1'b1}} | Enable asynchronous transitions on alerts. |
| InstrExec | bit | 1 | |
| RndCnstSramKey | sram_key_t | RndCnstSramKeyDefault | Random netlist constants |
| RndCnstSramNonce | sram_nonce_t | RndCnstSramNonceDefault |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | SRAM Clock |
| rst_ni | in | logic | |
| clk_otp_i | in | logic | OTP Clock (for key interface) |
| rst_otp_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface (device) for CSRs |
| tl_o | out | tl_d2h_t | |
| alert_rx_i | in | [NumAlerts-1:0] alert_rx_t | Alert outputs. |
| alert_tx_o | out | [NumAlerts-1:0] alert_tx_t | |
| lc_escalate_en_i | in | lc_tx_t | Life-cycle escalation input (scraps the scrambling keys) |
| lc_hw_debug_en_i | in | lc_tx_t | |
| otp_hw_cfg_i | in | otp_hw_cfg_t | Otp configuration for sram execution |
| sram_otp_key_o | out | sram_otp_key_req_t | Key request to OTP (running on clk_fixed) |
| sram_otp_key_i | in | sram_otp_key_rsp_t | |
| sram_scr_o | out | sram_scr_req_t | Interface with SRAM scrambling wrapper |
| sram_scr_i | in | sram_scr_rsp_t | |
| en_ifetch_o | out | tl_instr_en_e | Interface with corresponding tlul adapters |
This design unit is implemented in sram_ctrl_pkg.sv
This file depends on: otp_ctrl_pkg.sv
This design unit is implemented in sys_clk.sv
This file depends on: sys_osc.sv
of sys_clk
| Name | Type | Default Value | Description |
|---|---|---|---|
| SYS_EN_RDLY | time | 5us |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_src_sys_en_i | in | logic | System Source Clock Enable |
| clk_src_sys_jen_i | in | logic | System Source Clock Jitter Enable |
| clk_sys_pd_ni | in | logic | System Clock Power-down |
| rst_sys_clk_ni | in | logic | System Clock Logic reset |
| vcore_pok_h_i | in | logic | VCORE POK @3.3V (for OSC) |
| clk_src_sys_o | out | logic | System Source Clock |
| clk_src_sys_val_o | out | logic | System Source Clock Valid |
Clock Oscilator
This design unit is implemented in tl_main_pkg.sv
This design unit is implemented in tlul_adapter_sram.sv
This file depends on: tlul_err.sv, uvm_pkg.sv, top_pkg.sv, prim_fifo_sync.sv, tlul_pkg.sv, prim_util_pkg.sv
Tile-Link UL adapter for SRAM-like devices
Intentionally omitted BaseAddr in case of multiple memory maps are used in a SoC,
it means that aliasing can happen if target device size in TL-UL crossbar is bigger
than SRAM size
| Name | Type | Default Value | Description |
|---|---|---|---|
| SramAw | int | 12 | |
| SramDw | int | 32 | Must be multiple of the TL width |
| Outstanding | int | 1 | Only one request is accepted |
| ByteAccess | bit | 1 | 1: true, 0: false |
| ErrOnWrite | bit | 0 | 1: Writes not allowed, automatically error |
| ErrOnRead | bit | 0 | 1: Reads not allowed, automatically error |
| SramByte | int | SramDw/8 | |
| DataBitWidth | int | prim_util_pkg::vbits(SramByte) | |
| WidthMult | int | SramDw / top_pkg::TL_DW | |
| WoffsetWidth | int | (SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW) | |
| SramReqFifoWidth | int | $bits(sram_req_t) | |
| ReqFifoWidth | int | $bits(req_t) | |
| RspFifoWidth | int | $bits(rsp_t) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | TL-UL interface |
| tl_o | out | tl_d2h_t | |
| en_ifetch_i | in | tl_instr_en_e | control interface |
| req_o | out | logic | SRAM interface |
| gnt_i | in | logic | |
| we_o | out | logic | |
| addr_o | out | [SramAw-1:0] logic | |
| wdata_o | out | [SramDw-1:0] logic | |
| wmask_o | out | [SramDw-1:0] logic | |
| rdata_i | in | [SramDw-1:0] logic | |
| rvalid_i | in | logic | |
| rerror_i | in | [1:0] logic | 2 bit error 1: Uncorrectable, 0: Correctable |
Notes: The oustanding+1 allows the reqfifo to absorb back to back transactions without any wait states. Alternatively, the depth can be kept as oustanding as long as the outgoing ready is qualified with the acceptance of the response in the same cycle. Doing so however creates a path from ready_i to ready_o, which may not be desireable.
sramreqfifo: While the ReqFIFO holds the request until it is sent back via TL-UL, the sramreqfifo only needs to hold the mask and word offset until the read data returns from memory.
Rationale having #Outstanding depth in response FIFO. In normal case, if the host or the crossbar accepts the response data, response FIFO isn't needed. But if in any case it has a chance to be back pressured, the response FIFO should store the returned data not to lose the data from the SRAM interface. Remember, SRAM interface doesn't have back-pressure signal such as read_ready.
This design unit is implemented in top_earlgrey_rnd_cnst_pkg.sv
This file depends on: keymgr_pkg.sv, otp_ctrl_pkg.sv, alert_pkg.sv, flash_ctrl_pkg.sv, lc_ctrl_pkg.sv
This design unit is implemented in uart.sv
This file depends on: uvm_pkg.sv, uart_core.sv, uart_reg_pkg.sv, uart_reg_top.sv, tlul_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface |
| tl_o | out | tl_d2h_t | |
| cio_rx_i | in | logic | Generic IO |
| cio_tx_o | out | logic | |
| cio_tx_en_o | out | logic | |
| intr_tx_watermark_o | out | logic | Interrupts |
| intr_rx_watermark_o | out | logic | |
| intr_tx_empty_o | out | logic | |
| intr_rx_overflow_o | out | logic | |
| intr_rx_frame_err_o | out | logic | |
| intr_rx_break_err_o | out | logic | |
| intr_rx_timeout_o | out | logic | |
| intr_rx_parity_err_o | out | logic |
This design unit is implemented in usb_clk.sv
This file depends on: usb_osc.sv
of usb_clk
| Name | Type | Default Value | Description |
|---|---|---|---|
| USB_EN_RDLY | time | 5us | |
| USB_VAL_RDLY | time | 50ms | |
| USB_VAL_FDLY | time | 80ns |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_src_usb_en_i | in | logic | USB Source Clock Enable |
| usb_ref_pulse_i | in | logic | USB Reference Pulse |
| usb_ref_val_i | in | logic | USB Reference (Pulse) Valid |
| clk_usb_pd_ni | in | logic | USB Clock Power-down |
| rst_usb_clk_ni | in | logic | USB Clock Logic reset |
| vcore_pok_h_i | in | logic | VCORE POK @3.3V (for OSC) |
| clk_src_usb_o | out | logic | USB Source Clock |
| clk_src_usb_val_o | out | logic | USB Source Clock Valid |
Clock Oscilator
This design unit is implemented in usbdev.sv
This file depends on: usbdev_pkg.sv, usbdev_reg_pkg.sv, usbdev_iomux.sv, prim_intr_hw.sv, tlul_pkg.sv, prim_fifo_async.sv, prim_ram_2p_async_adv.sv, tlul_adapter_sram.sv, prim_flop_2sync.sv, prim_pulse_sync.sv, usbdev_reg_top.sv, usbdev_flop_2syncpulse.sv, usbdev_usbif.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| SramDw | int | 32 | Places packing bytes to SRAM assume this |
| SramDepth | int | 512 | 2kB, SRAM Width is DW |
| MaxPktSizeByte | int | 64 | |
| SramAw | int | $clog2(SramDepth) | |
| SizeWidth | int | $clog2(MaxPktSizeByte) | |
| NBuf | int | (SramDepth * SramDw) / (MaxPktSizeByte * 8) | |
| NBufWidth | int | $clog2(NBuf) | |
| AVFifoWidth | int | NBufWidth | AV fifo just stores buffer numbers |
| AVFifoDepth | int | 4 | |
| RXFifoWidth | int | NBufWidth + (1+SizeWidth) + 4 + 1 | RX fifo stores buf# + size(0-MaxPktSizeByte) + EP# + Type |
| RXFifoDepth | int | 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clk_aon_i | in | logic | |
| rst_aon_ni | in | logic | |
| clk_usb_48mhz_i | in | logic | use usb_ prefix for signals in this clk |
| rst_usb_48mhz_ni | in | logic | async reset, with relase sync to clk_usb_48_mhz_i |
| tl_i | in | tl_h2d_t | Register interface |
| tl_o | out | tl_d2h_t | |
| cio_d_i | in | logic | differential |
| cio_dp_i | in | logic | single-ended, can be used in differential mode to detect SE0 |
| cio_dn_i | in | logic | single-ended, can be used in differential mode to detect SE0 |
| cio_d_o | out | logic | Data outputs |
| cio_d_en_o | out | logic | |
| cio_dp_o | out | logic | |
| cio_dp_en_o | out | logic | |
| cio_dn_o | out | logic | |
| cio_dn_en_o | out | logic | |
| cio_sense_i | in | logic | Non-data I/O |
| cio_se0_o | out | logic | |
| cio_se0_en_o | out | logic | |
| cio_dp_pullup_o | out | logic | |
| cio_dp_pullup_en_o | out | logic | |
| cio_dn_pullup_o | out | logic | |
| cio_dn_pullup_en_o | out | logic | |
| cio_suspend_o | out | logic | |
| cio_suspend_en_o | out | logic | |
| cio_tx_mode_se_o | out | logic | |
| cio_tx_mode_se_en_o | out | logic | |
| usb_out_of_rst_o | out | logic | Direct pinmux aon detect connections |
| usb_aon_wake_en_o | out | logic | |
| usb_aon_wake_ack_o | out | logic | |
| usb_suspend_o | out | logic | |
| usb_state_debug_i | in | awk_state_t | Debug info from wakeup module |
| usb_ref_val_o | out | logic | SOF reference for clock calibration |
| usb_ref_pulse_o | out | logic | |
| intr_pkt_received_o | out | logic | Packet received |
| intr_pkt_sent_o | out | logic | Packet sent |
| intr_connected_o | out | logic | |
| intr_disconnected_o | out | logic | |
| intr_host_lost_o | out | logic | |
| intr_link_reset_o | out | logic | |
| intr_link_suspend_o | out | logic | |
| intr_link_resume_o | out | logic | |
| intr_av_empty_o | out | logic | |
| intr_rx_full_o | out | logic | |
| intr_av_overflow_o | out | logic | |
| intr_link_in_err_o | out | logic | |
| intr_link_out_err_o | out | logic | |
| intr_rx_crc_err_o | out | logic | |
| intr_rx_pid_err_o | out | logic | |
| intr_rx_bitstuff_err_o | out | logic | |
| intr_frame_o | out | logic |
Clear of ready and set of sent is a pulse in USB clock domain but needs to ensure register bit is cleared/set in TLUL domain usbdev_pulsesync takes pulse in clk_src to pulse in clk_dst
Event (pulse) synchronization
USB clk -> sys clk
sys clk -> USB clk
CDC for event signals (arguably they are there for a long time so would be ok) Just want a pulse to ensure only one interrupt for an event
Resume is a single pulse so needs pulsesync
resets etc cause the device address to clear
AV empty is a single pulse so needs pulsesync
RX full is a single pulse so needs pulsesync
TL-UL to SRAM adapter
SRAM Wrapper
Register module
sys clk -> USB clk
This design unit is implemented in usbdev_pkg.sv
This design unit is implemented in uvm_pkg.sv
| Type | Name | Description |
|---|---|---|
uvm_default_coreservice_t | inst |
| Type | Method | Description |
|---|---|---|
uvm_factory | get_factory() | |
void | set_factory(uvm_factory f) | |
uvm_report_server | get_report_server() | |
void | set_report_server(uvm_report_server server) | |
uvm_tr_database | get_default_tr_database() | |
void | set_default_tr_database(uvm_tr_database db) | |
void | set_component_visitor(uvm_visitor v) | |
uvm_visitor | get_component_visitor() | |
uvm_root | get_root() | |
uvm_coreservice_t | get() | get |
Extends: uvm_coreservice_t
Class: uvm_default_coreservice_t
uvm_default_coreservice_t provides a default implementation of the uvm_coreservice_t API. It instantiates uvm_default_factory, uvm_default_report_server, uvm_root.
| Type | Name | Description |
|---|---|---|
uvm_factory | factory | |
uvm_tr_database | tr_database | |
uvm_report_server | report_server | |
uvm_visitor | _visitor |
| Type | Method | Description |
|---|---|---|
uvm_factory | get_factory() | |
void | set_factory(uvm_factory f) | |
uvm_tr_database | get_default_tr_database() | |
void | set_default_tr_database(uvm_tr_database db) | |
uvm_report_server | get_report_server() | |
void | set_report_server(uvm_report_server server) | |
uvm_root | get_root() | |
void | set_component_visitor(uvm_visitor v) | |
uvm_visitor | get_component_visitor() |
| Type | Name | Description |
|---|---|---|
string | m_arg | |
string[] | m_stack |
| Type | Method | Description |
|---|---|---|
int | depth() | |
string | get() | |
string | get_arg() | |
void | set(string s) | |
void | down(string s) | |
void | down_element(int element) | |
void | up_element() | |
void | up(byte separator) | |
void | set_arg(string arg) | |
void | set_arg_element(string arg, int ele) | |
void | unset_arg(string arg) |
| Type | Name | Description |
|---|---|---|
bit | clone | The clone setting is used by the set/get config to know if cloning is on. |
bit | warning | Information variables used by the macro functions for storage. |
bit | status | |
uvm_bitstream_t | bitstream | |
int | intv | |
int | element | |
string | stringv | |
string | scratch1 | |
string | scratch2 | |
string | key | |
uvm_object | object | |
bit | array_warning_done | |
bit[] | field_array | |
bit | print_matches | |
uvm_scope_stack | scope | The scope stack is used for messages that are emitted by policy classes. |
bit[] | cycle_check | Used for checking cycles. When a data function is entered, if the depth is non-zero, then then the existeance of the object in the map means that a cycle has occured and the function should immediately exit. When the function exits, it should reset the cycle map so that there is no memory leak. |
uvm_comparer | comparer | These are the policy objects currently in use. The policy object gets set when a function starts up. The macros use this. |
uvm_packer | packer | |
uvm_recorder | recorder | |
uvm_printer | printer | |
uvm_object[] | m_uvm_cycle_scopes | utility function used to perform a cycle check when config setting are pushed to uvm_objects. the function has to look at the current object stack representing the call stack of all __m_uvm_field_automation() invocations. it is a only a cycle if the previous __m_uvm_field_automation call scope is not identical with the current scope AND the scope is already present in the object stack |
| Type | Method | Description |
|---|---|---|
void | do_field_check(string field, uvm_object obj) | |
string | get_function_type(int what) | |
string | get_full_scope_arg() | |
bit | m_do_cycle_check(uvm_object scope) |
Class- uvm_seed_map
This map is a seed map that can be used to update seeds. The update is done automatically by the seed hashing routine. The seed_table_lookup uses an instance name lookup and the seed_table inside a given map uses a type name for the lookup.
| Type | Name | Description |
|---|---|---|
int[] | seed_table | |
int[] | count |
| Type | Method | Description |
|---|---|---|
types_t | find_all(uvm_component start) | |
TYPE | find(uvm_component start) | |
TYPE | create_type_by_name(string type_name, string contxt) | |
TYPE | get_config(uvm_component comp, bit is_fatal) |
Extends: uvm_void
| Type | Name | Description |
|---|---|---|
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map |
| Type | Method | Description |
|---|---|---|
uvm_object | new(string name) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | type_name | |
this_type | m_global_pool | |
T[] | pool |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
this_type | get_global_pool() | |
T | get_global(KEY key) | |
T | get(KEY key) | |
void | add(KEY key, T item) | |
int | num() | |
void | delete(KEY key) | |
int | exists(KEY key) | |
int | first(KEY key) | |
int | last(KEY key) | |
int | next(KEY key) | |
int | prev(KEY key) | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | do_copy(uvm_object rhs) | |
void | do_print(uvm_printer printer) |
| Type | Name | Description |
|---|---|---|
this_type | m_global_pool | |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
T[] | pool |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
string | get_type_name() | |
this_type | get_global_pool() | |
T | get_global(string key) | |
T | get(string key) | |
void | delete(string key) | |
void | do_print(uvm_printer printer) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
void | add(KEY key, T item) | |
int | num() | |
int | exists(KEY key) | |
int | first(KEY key) | |
int | last(KEY key) | |
int | next(KEY key) | |
int | prev(KEY key) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | type_name | |
this_type | m_global_queue | |
T[] | queue |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
this_type | get_global_queue() | |
T | get_global(int index) | |
T | get(int index) | |
int | size() | |
void | insert(int index, T item) | |
void | delete(int index) | |
T | pop_front() | |
T | pop_back() | |
void | push_front(T item) | |
void | push_back(T item) | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | do_copy(uvm_object rhs) | |
string | convert2string() |
Instance overrides by requested type lookup
| Type | Name | Description |
|---|---|---|
uvm_factory_override[] | queue |
| Type | Method | Description |
|---|---|---|
uvm_factory | get() | |
void | register(uvm_object_wrapper obj) | |
void | set_inst_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path) | |
void | set_inst_override_by_name(string original_type_name, string override_type_name, string full_inst_path) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_type_override_by_name(string original_type_name, string override_type_name, bit replace) | |
uvm_object | create_object_by_type(uvm_object_wrapper requested_type, string parent_inst_path, string name) | |
uvm_component | create_component_by_type(uvm_object_wrapper requested_type, string parent_inst_path, string name, uvm_component parent) | |
uvm_object | create_object_by_name(string requested_type_name, string parent_inst_path, string name) | |
uvm_component | create_component_by_name(string requested_type_name, string parent_inst_path, string name, uvm_component parent) | |
void | debug_create_by_type(uvm_object_wrapper requested_type, string parent_inst_path, string name) | |
void | debug_create_by_name(string requested_type_name, string parent_inst_path, string name) | |
uvm_object_wrapper | find_override_by_type(uvm_object_wrapper requested_type, string full_inst_path) | |
uvm_object_wrapper | find_override_by_name(string requested_type_name, string full_inst_path) | |
uvm_object_wrapper | find_wrapper_by_name(string type_name) | |
void | print(int all_types) |
Extends: uvm_factory
| Type | Name | Description |
|---|---|---|
bit[] | m_types | |
bit[] | m_lookup_strs | |
uvm_object_wrapper[] | m_type_names | |
uvm_factory_override[] | m_type_overrides | |
uvm_factory_queue_class[] | m_inst_override_queues | |
uvm_factory_queue_class[] | m_inst_override_name_queues | |
uvm_factory_override[] | m_wildcard_inst_overrides | |
uvm_factory_override[] | m_override_info | |
bit | m_debug_pass |
| Type | Method | Description |
|---|---|---|
void | register(uvm_object_wrapper obj) | |
void | set_inst_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path) | |
void | set_inst_override_by_name(string original_type_name, string override_type_name, string full_inst_path) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_type_override_by_name(string original_type_name, string override_type_name, bit replace) | |
uvm_object | create_object_by_type(uvm_object_wrapper requested_type, string parent_inst_path, string name) | |
uvm_component | create_component_by_type(uvm_object_wrapper requested_type, string parent_inst_path, string name, uvm_component parent) | |
uvm_object | create_object_by_name(string requested_type_name, string parent_inst_path, string name) | |
uvm_component | create_component_by_name(string requested_type_name, string parent_inst_path, string name, uvm_component parent) | |
void | debug_create_by_type(uvm_object_wrapper requested_type, string parent_inst_path, string name) | |
void | debug_create_by_name(string requested_type_name, string parent_inst_path, string name) | |
uvm_object_wrapper | find_override_by_type(uvm_object_wrapper requested_type, string full_inst_path) | |
uvm_object_wrapper | find_override_by_name(string requested_type_name, string full_inst_path) | |
uvm_object_wrapper | find_wrapper_by_name(string type_name) | |
void | print(int all_types) | |
void | m_debug_create(string requested_type_name, uvm_object_wrapper requested_type, string parent_inst_path, string name) | |
void | m_debug_display(string requested_type_name, uvm_object_wrapper result, string full_inst_path) | |
bit | m_has_wildcard(string nm) | |
bit | check_inst_override_exists(uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path) |
| Type | Method | Description |
|---|---|---|
uvm_object | create_object(string name) | |
uvm_component | create_component(string name, uvm_component parent) | |
string | get_type_name() |
| Type | Name | Description |
|---|---|---|
string | full_inst_path | |
string | orig_type_name | |
string | ovrd_type_name | |
bit | selected | |
int | used | |
uvm_object_wrapper | orig_type | |
uvm_object_wrapper | ovrd_type |
| Type | Method | Description |
|---|---|---|
logic | new(string full_inst_path, string orig_type_name, uvm_object_wrapper orig_type, uvm_object_wrapper ovrd_type) |
Extends: uvm_object_wrapper
| Type | Name | Description |
|---|---|---|
string | type_name | |
this_type | me |
| Type | Method | Description |
|---|---|---|
uvm_component | create_component(string name, uvm_component parent) | |
string | get_type_name() | |
this_type | get() | |
T | create(string name, uvm_component parent, string contxt) | |
void | set_type_override(uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent) |
Extends: uvm_object_wrapper
| Type | Name | Description |
|---|---|---|
string | type_name | |
this_type | me |
| Type | Method | Description |
|---|---|---|
uvm_object | create_object(string name) | |
string | get_type_name() | |
this_type | get() | |
T | create(string name, uvm_component parent, string contxt) | |
void | set_type_override(uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent) |
class uvm_spell_chkr
| Type | Name | Description |
|---|---|---|
int | max |
| Type | Method | Description |
|---|---|---|
bit | check(tab_t strtab, string s) | |
int | levenshtein_distance(string s, string t) | |
int | minimum(int a, int b, int c) |
Class: uvm_resource_types
Provides typedefs and enums used throughout the resources facility. This class has no members or methods, only typedefs. It's used in lieu of package-scope types. When needed, other classes can use these types by prefixing their usage with uvm_resource_types::. E.g.
| uvm_resource_types::rsrc_q_t queue;
Options include:
auditing: on/off
The default for auditing is on. You may wish to turn it off to for performance reasons. With auditing off memory is not consumed for storage of auditing information and time is not spent collecting and storing auditing information. Of course, during the period when auditing is off no audit trail information is available
| Type | Name | Description |
|---|---|---|
bit | auditing |
| Type | Method | Description |
|---|---|---|
void | turn_on_auditing() | |
void | turn_off_auditing() | |
bit | is_auditing() |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | scope | |
bit | modified | |
bit | read_only | |
access_t[] | access | |
int | precedence | |
int | default_precedence |
| Type | Method | Description |
|---|---|---|
logic | new(string name, string s) | |
uvm_resource_base | get_type_handle() | |
void | set_read_only() | |
void | set_read_write() | |
bit | is_read_only() | Function: is_read_only Returns one if this resource has been set to read-only, zero otherwise |
void | wait_modified() | |
void | set_scope(string s) | Function: set_scope Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored. |
string | get_scope() | Function: get_scope Retrieve the regular expression string that identifies the set of scopes over which this resource is visible. |
bit | match_scope(string s) | Function: match_scope Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise. |
void | set_priority(priority_e pri) | |
string | convert2string() | |
void | do_print(uvm_printer printer) | |
void | record_read_access(uvm_object accessor) | |
void | record_write_access(uvm_object accessor) | |
void | print_accessors() | |
void | init_access_record(access_t access_record) | Function: init_access_record Initialize a new access record |
Class - get_t
Instances of get_t are stored in the history list as a record of each get. Failed gets are indicated with rsrc set to ~null~. This is part of the audit trail facility for resources.
| Type | Name | Description |
|---|---|---|
string | name | |
string | scope | |
uvm_resource_base | rsrc | |
time | t |
| Type | Name | Description |
|---|---|---|
uvm_resource_pool | rp | |
rsrc_q_t[] | rtab | |
rsrc_q_t[] | ttab | |
get_t[] | get_record | history of gets |
| Type | Method | Description |
|---|---|---|
logic | new() | |
uvm_resource_pool | get() | |
bit | spell_check(string s) | |
void | set(uvm_resource_base rsrc, override_t override) | Function: set Add a new resource to the resource pool. The resource is inserted into both the name map and type map so it can be located by either. An object creates a resources and ~sets~ it into the resource pool. Later, other objects that want to access the resource must ~get~ it from the pool Overrides can be specified using this interface. Either a name override, a type override or both can be specified. If an override is specified then the resource is entered at the front of the queue instead of at the back. It is not recommended that users specify the override parameter directly, rather they use the <set_override>, <set_name_override>, or <set_type_override> functions. |
void | set_override(uvm_resource_base rsrc) | |
void | set_name_override(uvm_resource_base rsrc) | |
void | set_type_override(uvm_resource_base rsrc) | |
void | push_get_record(string name, string scope, uvm_resource_base rsrc) | |
void | dump_get_records() | |
rsrc_q_t | lookup_name(string scope, string name, uvm_resource_base type_handle, bit rpterr) | |
uvm_resource_base | get_highest_precedence(rsrc_q_t q) | |
void | sort_by_precedence(rsrc_q_t q) | |
uvm_resource_base | get_by_name(string scope, string name, uvm_resource_base type_handle, bit rpterr) | |
rsrc_q_t | lookup_type(string scope, uvm_resource_base type_handle) | |
uvm_resource_base | get_by_type(string scope, uvm_resource_base type_handle) | |
rsrc_q_t | lookup_regex_names(string scope, string name, uvm_resource_base type_handle) | |
rsrc_q_t | lookup_regex(string re, string scope) | |
rsrc_q_t | lookup_scope(string scope) | |
void | set_priority_queue(uvm_resource_base rsrc, rsrc_q_t q, priority_e pri) | |
void | set_priority_type(uvm_resource_base rsrc, priority_e pri) | |
void | set_priority_name(uvm_resource_base rsrc, priority_e pri) | |
void | set_priority(uvm_resource_base rsrc, priority_e pri) | |
rsrc_q_t | find_unused_resources() | |
void | print_resources(rsrc_q_t rq, bit audit) | |
void | dump(bit audit) |
Extends: uvm_resource_base
| Type | Name | Description |
|---|---|---|
this_type | my_type | |
T | val | |
m_uvm_resource_converter | m_r2s |
| Type | Method | Description |
|---|---|---|
m_uvm_resource_converter | m_get_converter() | |
void | m_set_converter(m_uvm_resource_converter r2s) | |
logic | new(string name, string scope) | |
string | convert2string() | |
this_type | get_type() | |
uvm_resource_base | get_type_handle() | |
void | set() | |
void | set_override(override_t override) | |
this_type | get_by_name(string scope, string name, bit rpterr) | |
this_type | get_by_type(string scope, uvm_resource_base type_handle) | |
T | read(uvm_object accessor) | |
void | write(T t, uvm_object accessor) | |
void | set_priority(priority_e pri) | |
this_type | get_highest_precedence(rsrc_q_t q) |
CLASS- uvm_resource_converter#(T)
The uvm_resource_converter class provides a policy object for doing convertion from resource value to string.
| Type | Method | Description |
|---|---|---|
string | convert2string(T val) |
| Type | Name | Description |
|---|---|---|
m_uvm_resource_default_converter | m_singleton | |
string | m_name |
| Type | Method | Description |
|---|---|---|
string | convert2string(T val) | |
logic | new() | |
bit | register(string typename) |
| Type | Name | Description |
|---|---|---|
m_uvm_resource_convert2string_converter | m_singleton |
| Type | Method | Description |
|---|---|---|
string | convert2string(T val) | |
logic | new() | |
bit | register() |
| Type | Name | Description |
|---|---|---|
m_uvm_resource_sprint_converter | m_singleton |
| Type | Method | Description |
|---|---|---|
string | convert2string(T val) | |
logic | new() | |
bit | register() |
CLASS- m_uvm_resource_default_converters Singleton used to register default resource value converters for the built-in singular types.
| Type | Name | Description |
|---|---|---|
bit | m_singleton |
| Type | Method | Description |
|---|---|---|
logic | new() | |
bit | register() |
uvm_int_rsrc
specialization of uvm_resource #(T) for T = int
| Type | Name | Description |
|---|---|---|
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
string | scope | |
bit | modified | |
bit | read_only | |
access_t[] | access | |
int | precedence | |
int | default_precedence | |
uvm_resource | my_type | |
unknown | val | |
m_uvm_resource_converter | m_r2s |
| Type | Method | Description |
|---|---|---|
logic | new(string name, string s) | |
string | convert2string() | |
this_subtype | get_by_name(string scope, string name, bit rpterr) | |
this_subtype | get_by_type(string scope, uvm_resource_base type_handle) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_resource | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_resource_base | get_type_handle() | |
void | set_read_only() | |
void | set_read_write() | |
bit | is_read_only() | Function: is_read_only Returns one if this resource has been set to read-only, zero otherwise |
void | wait_modified() | |
void | set_scope(string s) | Function: set_scope Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored. |
string | get_scope() | Function: get_scope Retrieve the regular expression string that identifies the set of scopes over which this resource is visible. |
bit | match_scope(string s) | Function: match_scope Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise. |
void | set_priority(priority_e pri) | |
void | record_read_access(uvm_object accessor) | |
void | record_write_access(uvm_object accessor) | |
void | print_accessors() | |
void | init_access_record(access_t access_record) | Function: init_access_record Initialize a new access record |
m_uvm_resource_converter | m_get_converter() | |
void | m_set_converter(m_uvm_resource_converter r2s) | |
void | set() | |
void | set_override(override_t override) | |
unknown | read(uvm_object accessor) | |
void | write(T t, uvm_object accessor) | |
uvm_resource | get_highest_precedence(rsrc_q_t q) |
uvm_string_rsrc
specialization of uvm_resource #(T) for T = string
| Type | Name | Description |
|---|---|---|
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
string | scope | |
bit | modified | |
bit | read_only | |
access_t[] | access | |
int | precedence | |
int | default_precedence | |
uvm_resource | my_type | |
unknown | val | |
m_uvm_resource_converter | m_r2s |
| Type | Method | Description |
|---|---|---|
logic | new(string name, string s) | |
string | convert2string() | |
this_subtype | get_by_name(string scope, string name, bit rpterr) | |
this_subtype | get_by_type(string scope, uvm_resource_base type_handle) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_resource | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_resource_base | get_type_handle() | |
void | set_read_only() | |
void | set_read_write() | |
bit | is_read_only() | Function: is_read_only Returns one if this resource has been set to read-only, zero otherwise |
void | wait_modified() | |
void | set_scope(string s) | Function: set_scope Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored. |
string | get_scope() | Function: get_scope Retrieve the regular expression string that identifies the set of scopes over which this resource is visible. |
bit | match_scope(string s) | Function: match_scope Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise. |
void | set_priority(priority_e pri) | |
void | record_read_access(uvm_object accessor) | |
void | record_write_access(uvm_object accessor) | |
void | print_accessors() | |
void | init_access_record(access_t access_record) | Function: init_access_record Initialize a new access record |
m_uvm_resource_converter | m_get_converter() | |
void | m_set_converter(m_uvm_resource_converter r2s) | |
void | set() | |
void | set_override(override_t override) | |
unknown | read(uvm_object accessor) | |
void | write(T t, uvm_object accessor) | |
uvm_resource | get_highest_precedence(rsrc_q_t q) |
uvm_obj_rsrc
specialization of uvm_resource #(T) for T = uvm_object
| Type | Name | Description |
|---|---|---|
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
string | scope | |
bit | modified | |
bit | read_only | |
access_t[] | access | |
int | precedence | |
int | default_precedence | |
uvm_resource | my_type | |
uvm_object | val | |
m_uvm_resource_converter | m_r2s |
| Type | Method | Description |
|---|---|---|
logic | new(string name, string s) | |
this_subtype | get_by_name(string scope, string name, bit rpterr) | |
this_subtype | get_by_type(string scope, uvm_resource_base type_handle) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_resource | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_resource_base | get_type_handle() | |
void | set_read_only() | |
void | set_read_write() | |
bit | is_read_only() | Function: is_read_only Returns one if this resource has been set to read-only, zero otherwise |
void | wait_modified() | |
void | set_scope(string s) | Function: set_scope Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored. |
string | get_scope() | Function: get_scope Retrieve the regular expression string that identifies the set of scopes over which this resource is visible. |
bit | match_scope(string s) | Function: match_scope Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise. |
void | set_priority(priority_e pri) | |
void | record_read_access(uvm_object accessor) | |
void | record_write_access(uvm_object accessor) | |
void | print_accessors() | |
void | init_access_record(access_t access_record) | Function: init_access_record Initialize a new access record |
m_uvm_resource_converter | m_get_converter() | |
void | m_set_converter(m_uvm_resource_converter r2s) | |
void | set() | |
void | set_override(override_t override) | |
uvm_object | read(uvm_object accessor) | |
void | write(T t, uvm_object accessor) | |
uvm_resource | get_highest_precedence(rsrc_q_t q) |
uvm_bit_rsrc
specialization of uvm_resource #(T) for T = vector of bits
| Type | Name | Description |
|---|---|---|
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
string | scope | |
bit | modified | |
bit | read_only | |
access_t[] | access | |
int | precedence | |
int | default_precedence | |
uvm_resource | my_type | |
unknown | val | |
m_uvm_resource_converter | m_r2s |
| Type | Method | Description |
|---|---|---|
logic | new(string name, string s) | |
string | convert2string() | |
this_subtype | get_by_name(string scope, string name, bit rpterr) | |
this_subtype | get_by_type(string scope, uvm_resource_base type_handle) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_resource | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_resource_base | get_type_handle() | |
void | set_read_only() | |
void | set_read_write() | |
bit | is_read_only() | Function: is_read_only Returns one if this resource has been set to read-only, zero otherwise |
void | wait_modified() | |
void | set_scope(string s) | Function: set_scope Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored. |
string | get_scope() | Function: get_scope Retrieve the regular expression string that identifies the set of scopes over which this resource is visible. |
bit | match_scope(string s) | Function: match_scope Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise. |
void | set_priority(priority_e pri) | |
void | record_read_access(uvm_object accessor) | |
void | record_write_access(uvm_object accessor) | |
void | print_accessors() | |
void | init_access_record(access_t access_record) | Function: init_access_record Initialize a new access record |
m_uvm_resource_converter | m_get_converter() | |
void | m_set_converter(m_uvm_resource_converter r2s) | |
void | set() | |
void | set_override(override_t override) | |
unknown | read(uvm_object accessor) | |
void | write(T t, uvm_object accessor) | |
uvm_resource | get_highest_precedence(rsrc_q_t q) |
uvm_byte_rsrc
specialization of uvm_resource #T() for T = vector of bytes
| Type | Name | Description |
|---|---|---|
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
string | scope | |
bit | modified | |
bit | read_only | |
access_t[] | access | |
int | precedence | |
int | default_precedence | |
uvm_resource | my_type | |
unknown | val | |
m_uvm_resource_converter | m_r2s |
| Type | Method | Description |
|---|---|---|
logic | new(string name, string s) | |
string | convert2string() | |
this_subtype | get_by_name(string scope, string name, bit rpterr) | |
this_subtype | get_by_type(string scope, uvm_resource_base type_handle) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_resource | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_resource_base | get_type_handle() | |
void | set_read_only() | |
void | set_read_write() | |
bit | is_read_only() | Function: is_read_only Returns one if this resource has been set to read-only, zero otherwise |
void | wait_modified() | |
void | set_scope(string s) | Function: set_scope Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored. |
string | get_scope() | Function: get_scope Retrieve the regular expression string that identifies the set of scopes over which this resource is visible. |
bit | match_scope(string s) | Function: match_scope Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise. |
void | set_priority(priority_e pri) | |
void | record_read_access(uvm_object accessor) | |
void | record_write_access(uvm_object accessor) | |
void | print_accessors() | |
void | init_access_record(access_t access_record) | Function: init_access_record Initialize a new access record |
m_uvm_resource_converter | m_get_converter() | |
void | m_set_converter(m_uvm_resource_converter r2s) | |
void | set() | |
void | set_override(override_t override) | |
unknown | read(uvm_object accessor) | |
void | write(T t, uvm_object accessor) | |
uvm_resource | get_highest_precedence(rsrc_q_t q) |
class: uvm_resource_db
All of the functions in uvm_resource_db#(T) are static, so they must be called using the :: operator. For example:
| uvm_resource_db#(int)::set("A", "*", 17, this);
The parameter value "int" identifies the resource type as uvm_resource#(int). Thus, the type of the object in the resource container is int. This maintains the type-safety characteristics of resource operations.
| Type | Method | Description |
|---|---|---|
logic | new() | |
rsrc_t | get_by_type(string scope) | |
rsrc_t | get_by_name(string scope, string name, bit rpterr) | |
rsrc_t | set_default(string scope, string name) | |
void | m_show_msg(string id, string rtype, string action, string scope, string name, uvm_object accessor, rsrc_t rsrc) | |
void | set(string scope, string name, T val, uvm_object accessor) | |
void | set_anonymous(string scope, T val, uvm_object accessor) | |
void | set_override(string scope, string name, T val, uvm_object accessor) | |
void | set_override_type(string scope, string name, T val, uvm_object accessor) | |
void | set_override_name(string scope, string name, T val, uvm_object accessor) | |
bit | read_by_name(string scope, string name, T val, uvm_object accessor) | |
bit | read_by_type(string scope, T val, uvm_object accessor) | |
bit | write_by_name(string scope, string name, T val, uvm_object accessor) | |
bit | write_by_type(string scope, T val, uvm_object accessor) | |
void | dump() |
Options include:
tracing: on/off
The default for tracing is off.
| Type | Name | Description |
|---|---|---|
bit | ready | |
bit | tracing |
| Type | Method | Description |
|---|---|---|
void | turn_on_tracing() | |
void | turn_off_tracing() | |
bit | is_tracing() | |
void | init() |
Internal class for config waiters
| Type | Name | Description |
|---|---|---|
string | inst_name | |
string | field_name | |
event | trigger |
| Type | Method | Description |
|---|---|---|
logic | new(string inst_name, string field_name) |
class: uvm_config_db
All of the functions in uvm_config_db#(T) are static, so they must be called using the :: operator. For example:
| uvm_config_db#(int)::set(this, "*", "A");
The parameter value "int" identifies the configuration type as an int property.
The and methods provide the same API and semantics as the set/get_config_* functions in <uvm_component>.
| Type | Name | Description |
|---|---|---|
uvm_pool[] | m_rsc | |
uvm_queue[] | m_waiters |
| Type | Method | Description |
|---|---|---|
bit | get(uvm_component cntxt, string inst_name, string field_name, T value) | |
void | set(uvm_component cntxt, string inst_name, string field_name, T value) | |
bit | exists(uvm_component cntxt, string inst_name, string field_name, bit spell_chk) | |
void | wait_modified(uvm_component cntxt, string inst_name, string field_name) | |
uvm_resource | get_by_type(string scope) | |
uvm_resource | get_by_name(string scope, string name, bit rpterr) | |
uvm_resource | set_default(string scope, string name) | |
void | m_show_msg(string id, string rtype, string action, string scope, string name, uvm_object accessor, rsrc_t rsrc) | |
void | set_anonymous(string scope, T val, uvm_object accessor) | |
void | set_override(string scope, string name, T val, uvm_object accessor) | |
void | set_override_type(string scope, string name, T val, uvm_object accessor) | |
void | set_override_name(string scope, string name, T val, uvm_object accessor) | |
bit | read_by_name(string scope, string name, T val, uvm_object accessor) | |
bit | read_by_type(string scope, T val, uvm_object accessor) | |
bit | write_by_name(string scope, string name, T val, uvm_object accessor) | |
bit | write_by_type(string scope, T val, uvm_object accessor) | |
void | dump() |
Options include:
tracing: on/off
The default for tracing is off.
| Type | Name | Description |
|---|---|---|
bit | ready | |
bit | tracing |
| Type | Method | Description |
|---|---|---|
void | turn_on_tracing() | |
void | turn_off_tracing() | |
bit | is_tracing() | |
void | init() |
Class: uvm_printer
The uvm_printer class provides an interface for printing <uvm_objects> in various formats. Subtypes of uvm_printer implement different print formats, or policies.
A user-defined printer format can be created, or one of the following four built-in printers can be used:
<uvm_printer> - provides base printer functionality; must be overridden.
<uvm_table_printer> - prints the object in a tabular form.
<uvm_tree_printer> - prints the object in a tree form.
<uvm_line_printer> - prints the information on a single line, but uses the same object separators as the tree printer.
Printers have knobs that you use to control what and how information is printed. These knobs are contained in a separate knob class:
<uvm_printer_knobs> - common printer settings
For convenience, global instances of each printer type are available for direct reference in your testbenches.
<uvm_default_tree_printer>
<uvm_default_line_printer>
<uvm_default_table_printer>
<uvm_default_printer> (set to default_table_printer by default)
When <uvm_object::print> and <uvm_object::sprint> are called without specifying a printer, the <uvm_default_printer> is used.
| Type | Name | Description |
|---|---|---|
uvm_printer_knobs | knobs | Variable: knobs The knob object provides access to the variety of knobs associated with a specific printer instance. |
bit[] | m_array_stack | |
uvm_scope_stack | m_scope | |
string | m_string | |
uvm_printer_row_info[] | m_rows |
| Type | Method | Description |
|---|---|---|
void | print_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix, byte scope_separator, string type_name) | |
void | print_int(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix, byte scope_separator, string type_name) | |
void | print_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix, byte scope_separator, string type_name) | |
void | print_object(string name, uvm_object value, byte scope_separator) | |
void | print_object_header(string name, uvm_object value, byte scope_separator) | |
void | print_string(string name, string value, byte scope_separator) | |
void | print_time(string name, time value, byte scope_separator) | |
void | print_real(string name, real value, byte scope_separator) | |
void | print_generic(string name, string type_name, int size, string value, byte scope_separator) | |
string | emit() | |
string | format_row(uvm_printer_row_info row) | |
string | format_header() | |
string | format_footer() | |
string | adjust_name(string id, byte scope_separator) | |
void | print_array_header(string name, int size, string arraytype, byte scope_separator) | |
void | print_array_range(int min, int max) | |
void | print_array_footer(int size) | |
bit | istop() | |
string | index_string(int index, string name) |
Extends: uvm_printer
| Type | Name | Description |
|---|---|---|
int | m_max_name | |
int | m_max_type | |
int | m_max_size | |
int | m_max_value |
| Type | Method | Description |
|---|---|---|
uvm_table_printer | new() | |
string | emit() | |
void | calculate_max_widths() |
Extends: uvm_printer
| Type | Name | Description |
|---|---|---|
string | newline |
| Type | Method | Description |
|---|---|---|
uvm_tree_printer | new() | |
string | emit() |
Extends: uvm_tree_printer
| Type | Method | Description |
|---|---|---|
logic | new() |
| Type | Name | Description |
|---|---|---|
bit | header | |
bit | footer | |
bit | full_name | |
bit | identifier | |
bit | type_name | |
bit | size | |
int | depth | |
bit | reference | |
int | begin_elements | |
int | end_elements | |
string | prefix | |
int | indent | |
bit | show_root | |
int | mcd | |
string | separator | |
bit | show_radix | |
uvm_radix_enum | default_radix | |
string | dec_radix | |
string | bin_radix | |
string | oct_radix | |
string | unsigned_radix | |
string | hex_radix | |
int | max_width | Deprecated knobs, hereafter ignored |
string | truncation | |
int | name_width | |
int | type_width | |
int | size_width | |
int | value_width | |
bit | sprint |
| Type | Method | Description |
|---|---|---|
string | get_radix_str(uvm_radix_enum radix) |
| Type | Name | Description |
|---|---|---|
uvm_recursion_policy_enum | policy | |
int | show_max | |
int | verbosity | |
uvm_severity | sev | |
string | miscompares | |
bit | physical | |
bit | abstract | |
bit | check_type | |
int | result | |
int | depth | current depth of objects |
uvm_object[] | compare_map | |
uvm_scope_stack | scope |
| Type | Method | Description |
|---|---|---|
bit | compare_field(string name, uvm_bitstream_t lhs, uvm_bitstream_t rhs, int size, uvm_radix_enum radix) | |
bit | compare_field_int(string name, uvm_integral_t lhs, uvm_integral_t rhs, int size, uvm_radix_enum radix) | |
bit | compare_field_real(string name, real lhs, real rhs) | |
bit | compare_object(string name, uvm_object lhs, uvm_object rhs) | |
bit | compare_string(string name, string lhs, string rhs) | |
void | print_msg(string msg) | |
void | print_rollup(uvm_object rhs, uvm_object lhs) | Need this function because sformat doesn't support objects |
void | print_msg_object(uvm_object lhs, uvm_object rhs) | |
uvm_comparer | init() |
| Type | Name | Description |
|---|---|---|
bit | physical | |
bit | abstract | |
bit | use_metadata | |
bit | big_endian | |
bit[] | bitstream | local bits for (un)pack_bytes |
bit[] | fabitstream | field automation bits for (un)pack_bytes |
int | count | used to count the number of packed bits |
uvm_scope_stack | scope | |
bit | reverse_order | flip the bit order around |
byte | byte_size | set up bytesize for endianess |
int | word_size | set up worksize for endianess |
bit | nopack | only count packable bits |
uvm_recursion_policy_enum | policy | |
uvm_pack_bitstream_t | m_bits | |
int | m_packed_size |
| Type | Method | Description |
|---|---|---|
void | pack_field(uvm_bitstream_t value, int size) | |
void | pack_field_int(uvm_integral_t value, int size) | |
void | pack_bits(bit[] value, int size) | |
void | pack_bytes(byte[] value, int size) | |
void | pack_ints(int[] value, int size) | |
void | pack_string(string value) | |
void | pack_time(time value) | |
void | pack_real(real value) | |
void | pack_object(uvm_object value) | |
bit | is_null() | |
uvm_bitstream_t | unpack_field(int size) | |
uvm_integral_t | unpack_field_int(int size) | |
void | unpack_bits(bit[] value, int size) | |
void | unpack_bytes(byte[] value, int size) | |
void | unpack_ints(int[] value, int size) | |
string | unpack_string(int num_chars) | |
time | unpack_time() | |
real | unpack_real() | |
void | unpack_object(uvm_object value) | |
int | get_packed_size() | |
void | unpack_object_ext(uvm_object value) | |
uvm_pack_bitstream_t | get_packed_bits() | |
bit | get_bit(int index) | |
byte | get_byte(int index) | |
int | get_int(int index) | |
void | get_bits(bit[] bits) | |
void | get_bytes(byte[] bytes) | |
void | get_ints(int[] ints) | |
void | put_bits(bit[] bitstream) | |
void | put_bytes(byte[] bytestream) | |
void | put_ints(int[] intstream) | |
void | set_packed_size() | |
void | index_error(int index, string id, int sz) | |
bit | enough_bits(int needed, string id) | |
void | reset() |
Extends: uvm_object
CLASS: uvm_link_base
The ~uvm_link_base~ class presents a simple API for defining a link between any two objects.
Using extensions of this class, a <uvm_tr_database> can determine the type of links being passed, without relying on "magic" string names.
For example: | | virtual function void do_establish_link(uvm_link_base link); | uvm_parent_child_link pc_link; | uvm_cause_effect_link ce_link; | | if ($cast(pc_link, link)) begin | // Record the parent-child relationship | end | else if ($cast(ce_link, link)) begin | // Record the cause-effect relationship | end | else begin | // Unsupported relationship! | end | endfunction : do_establish_link
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new Constructor Parameters: name - Instance name |
void | set_lhs(uvm_object lhs) | Function: set_lhs Sets the left-hand-side of the link Triggers the <do_set_lhs> callback. |
uvm_object | get_lhs() | Function: get_lhs Gets the left-hand-side of the link Triggers the <do_get_lhs> callback |
void | set_rhs(uvm_object rhs) | Function: set_rhs Sets the right-hand-side of the link Triggers the <do_set_rhs> callback. |
uvm_object | get_rhs() | Function: get_rhs Gets the right-hand-side of the link Triggers the <do_get_rhs> callback |
void | set(uvm_object lhs, uvm_object rhs) | Function: set Convenience method for setting both sides in one call. Triggers both the <do_set_rhs> and <do_set_lhs> callbacks. |
void | do_set_lhs(uvm_object lhs) | |
uvm_object | do_get_lhs() | |
void | do_set_rhs(uvm_object rhs) | |
uvm_object | do_get_rhs() |
Extends: uvm_link_base
| Type | Name | Description |
|---|---|---|
uvm_object | m_lhs | |
uvm_object | m_rhs | |
string | type_name |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Constructor Parameters: name - Instance name |
uvm_parent_child_link | get_link(uvm_object lhs, uvm_object rhs, string name) | |
void | do_set_lhs(uvm_object lhs) | |
uvm_object | do_get_lhs() | |
void | do_set_rhs(uvm_object rhs) | |
uvm_object | do_get_rhs() |
Extends: uvm_link_base
| Type | Name | Description |
|---|---|---|
uvm_object | m_lhs | |
uvm_object | m_rhs | |
string | type_name |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Constructor Parameters: name - Instance name |
uvm_cause_effect_link | get_link(uvm_object lhs, uvm_object rhs, string name) | |
void | do_set_lhs(uvm_object lhs) | |
uvm_object | do_get_lhs() | |
void | do_set_rhs(uvm_object rhs) | |
uvm_object | do_get_rhs() |
Extends: uvm_link_base
| Type | Name | Description |
|---|---|---|
uvm_object | m_lhs | |
uvm_object | m_rhs | |
string | type_name |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Constructor Parameters: name - Instance name |
uvm_related_link | get_link(uvm_object lhs, uvm_object rhs, string name) | |
void | do_set_lhs(uvm_object lhs) | |
uvm_object | do_get_lhs() | |
void | do_set_rhs(uvm_object rhs) | |
uvm_object | do_get_rhs() |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
bit | m_is_opened | |
bit[] | m_streams |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new Constructor Parameters: name - Instance name |
bit | open_db() | Function: open_db Open the backend connection to the database. If the database is already open, then this method will return 1. Otherwise, the method will call <do_open_db>, and return the result. |
bit | close_db() | Function: close_db Closes the backend connection to the database. Closing a database implicitly closes and frees all <uvm_tr_streams> within the database. If the database is already closed, then this method will return 1. Otherwise, this method will trigger a <do_close_db> call, and return the result. |
bit | is_open() | Function: is_open Returns the open/closed status of the database. This method returns 1 if the database has been successfully opened, but not yet closed. |
uvm_tr_stream | open_stream(string name, string scope, string type_name) | Function: open_stream Provides a reference to a ~stream~ within the database. Parameters: name - A string name for the stream. This is the name associated with the stream in the database. scope - An optional scope for the stream. type_name - An optional name describing the type of records which will be created in this stream. The method returns a reference to a <uvm_tr_stream> object if successful, ~null~ otherwise. This method will trigger a <do_open_stream> call, and if a non ~null~ stream is returned, then <uvm_tr_stream::do_open> will be called. Streams can only be opened if the database is open (per <is_open>). Otherwise the request will be ignored, and ~null~ will be returned. |
void | m_free_stream(uvm_tr_stream stream) | Function- m_free_stream Removes stream from the internal array |
logic | get_streams(uvm_tr_stream[] q) | Function: get_streams Provides a queue of all streams within the database. Parameters: q - A reference to a queue of <uvm_tr_stream>s The ~get_streams~ method returns the size of the queue, such that the user can conditionally process the elements. | uvm_tr_stream stream_q$; | if (my_db.get_streams(stream_q)) begin | // Process the queue... | end |
void | establish_link(uvm_link_base link) | Function: establish_link Establishes a ~link~ between two elements in the database Links are only supported between ~streams~ and ~records~ within a single database. This method will trigger a <do_establish_link> call. |
bit | do_open_db() | |
bit | do_close_db() | |
uvm_tr_stream | do_open_stream(string name, string scope, string type_name) | |
void | do_establish_link(uvm_link_base link) |
Extends: uvm_tr_database
| Type | Name | Description |
|---|---|---|
uvm_simple_lock_dap | m_filename_dap | |
UVM_FILE | m_file | Variable- m_file |
string | type_name |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Constructor Parameters: name - Instance name |
bit | do_open_db() | |
bit | do_close_db() | |
uvm_tr_stream | do_open_stream(string name, string scope, string type_name) | |
void | do_establish_link(uvm_link_base link) | |
void | set_file_name(string filename) | Function: set_file_name Sets the file name which will be used for output. The ~set_file_name~ method can only be called prior to ~open_db~. By default, the database will use a file named "tr_db.log". |
class- m_uvm_tr_stream_cfg Undocumented helper class for storing stream initialization values.
| Type | Name | Description |
|---|---|---|
uvm_tr_database | db | |
string | scope | |
string | stream_type_name |
Extends: uvm_object
CLASS: uvm_tr_stream
The ~uvm_tr_stream~ base class is a representation of a stream of records within a <uvm_tr_database>.
The record stream is intended to hide the underlying database implementation from the end user, as these details are often vendor or tool-specific.
The ~uvm_tr_stream~ class is pure virtual, and must be extended with an implementation. A default text-based implementation is provided via the <uvm_text_tr_stream> class.
| Type | Name | Description |
|---|---|---|
uvm_set_before_get_dap | m_cfg_dap | |
bit[] | m_records | |
bit | m_warn_null_cfg | |
bit | m_is_opened | |
bit | m_is_closed | |
integer[] | m_ids_by_stream | |
uvm_tr_stream[] | m_streams_by_id |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new Constructor Parameters: name - Stream instance name |
uvm_tr_database | get_db() | Function: get_db Returns a reference to the database which contains this stream. A warning will be asserted if get_db is called prior to the stream being initialized via <do_open>. |
string | get_scope() | Function: get_scope Returns the ~scope~ supplied when opening this stream. A warning will be asserted if get_scope is called prior to the stream being initialized via <do_open>. |
string | get_stream_type_name() | Function: get_stream_type_name Returns a reference to the database which contains this stream. A warning will be asserted if get_stream_type_name is called prior to the stream being initialized via <do_open>. |
void | close() | Function: close Closes this stream. Closing a stream closes all open recorders in the stream. This method will trigger a <do_close> call, followed by <uvm_recorder::close> on all open recorders within the stream. |
void | free() | Function: free Frees this stream. Freeing a stream indicates that the database can free any references to the stream (including references to records within the stream). This method will trigger a <do_free> call, followed by <uvm_recorder::free> on all recorders within the stream. |
void | m_do_open(uvm_tr_database db, string scope, string stream_type_name) | Function- m_do_open Initializes the state of the stream Parameters- db - Database which the stream belongs to scope - Optional scope stream_type_name - Optional type name for the stream This method will trigger a <do_open> call. An error will be asserted if-
|
bit | is_open() | Function: is_open Returns true if this ~uvm_tr_stream~ was opened on the database, but has not yet been closed. |
bit | is_closed() | Function: is_closed Returns true if this ~uvm_tr_stream~ was closed on the database, but has not yet been freed. |
uvm_recorder | open_recorder(string name, time open_time, string type_name) | Function: open_recorder Marks the opening of a new transaction recorder on the stream. Parameters: name - A name for the new transaction open_time - Optional time to record as the opening of this transaction type_name - Optional type name for the transaction If ~open_time~ is omitted (or set to 0), then the stream will use the current time. This method will trigger a <do_open_recorder> call. If ~do_open_recorder~ returns a non-~null~ value, then the <uvm_recorder::do_open> method will be called in the recorder. Transaction recorders can only be opened if the stream is ~open~ on the database (per <is_open>). Otherwise the request will be ignored, and ~null~ will be returned. |
void | m_free_recorder(uvm_recorder recorder) | Function- m_free_recorder Removes recorder from the internal array |
logic | get_recorders(uvm_recorder[] q) | Function: get_recorders Provides a queue of all transactions within the stream. Parameters: q - A reference to the queue of <uvm_recorder>s The <get_recorders> method returns the size of the queue, such that the user can conditionally process the elements. | uvm_recorder tr_q$; | if (my_stream.get_recorders(tr_q)) begin | // Process the queue... | end |
integer | get_handle() | Function: get_handle Returns a unique ID for this stream. A value of ~0~ indicates that the recorder has been ~freed~, and no longer has a valid ID. |
integer | m_get_handle() | |
uvm_tr_stream | get_stream_from_handle(integer id) | |
void | m_free_id(integer id) | |
void | do_open(uvm_tr_database db, string scope, string stream_type_name) | |
void | do_close() | |
void | do_free() | |
uvm_recorder | do_open_recorder(string name, time open_time, string type_name) |
Extends: uvm_tr_stream
| Type | Name | Description |
|---|---|---|
uvm_text_tr_database | m_text_db | |
string | type_name |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Constructor Parameters: name - Instance name |
void | do_open(uvm_tr_database db, string scope, string stream_type_name) | |
void | do_close() | |
void | do_free() | |
uvm_recorder | do_open_recorder(string name, time open_time, string type_name) |
Extends: uvm_object
uvm_recorder
| Type | Name | Description |
|---|---|---|
uvm_set_before_get_dap | m_stream_dap | |
bit | m_warn_null_stream | |
bit | m_is_opened | |
bit | m_is_closed | |
time | m_open_time | |
time | m_close_time | |
int | recording_depth | Variable- recording_depth |
uvm_radix_enum | default_radix | |
bit | physical | |
bit | abstract | |
bit | identifier | |
uvm_recursion_policy_enum | policy | |
integer[] | m_ids_by_recorder | |
uvm_recorder[] | m_recorders_by_id | |
integer | m_id |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
uvm_tr_stream | get_stream() | Function: get_stream Returns a reference to the stream which created this record. A warning will be asserted if get_stream is called prior to the record being initialized via <do_open>. |
void | close(time close_time) | Function: close Closes this recorder. Closing a recorder marks the end of the transaction in the stream. Parameters: close_time - Optional time to record as the closing time of this transaction. This method will trigger a <do_close> call. |
void | free(time close_time) | Function: free Frees this recorder Freeing a recorder indicates that the stream and database can release any references to the recorder. Parameters: close_time - Optional time to record as the closing time of this transaction. If a recorder has not yet been closed (via a call to ), then will automatically be called, and passed the ~close_time~. If the recorder has already been closed, then the ~close_time~ will be ignored. This method will trigger a <do_free> call. |
bit | is_open() | Function: is_open Returns true if this ~uvm_recorder~ was opened on its stream, but has not yet been closed. |
time | get_open_time() | Function: get_open_time Returns the ~open_time~ |
bit | is_closed() | Function: is_closed Returns true if this ~uvm_recorder~ was closed on its stream, but has not yet been freed. |
time | get_close_time() | Function: get_close_time Returns the ~close_time~ |
void | m_do_open(uvm_tr_stream stream, time open_time, string type_name) | Function- m_do_open Initializes the internal state of the recorder. Parameters: stream - The stream which spawned this recorder This method will trigger a <do_open> call. An error will be asserted if:
|
void | m_free_id(integer id) | |
integer | get_handle() | Function: get_handle Returns a unique ID for this recorder. A value of ~0~ indicates that the recorder has been ~freed~, and no longer has a valid ID. |
uvm_recorder | get_recorder_from_handle(integer id) | |
void | record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix) | Function: record_field Records an integral field (less than or equal to 4096 bits). Parameters: name - Name of the field value - Value of the field to record. size - Number of bits of the field which apply (Usually obtained via $bits). radix - The <uvm_radix_enum> to use. This method will trigger a <do_record_field> call. |
void | record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix) | Function: record_field_int Records an integral field (less than or equal to 64 bits). This optimized version of <record_field> is useful for sizes up to 64 bits. Parameters: name - Name of the field value - Value of the field to record size - Number of bits of the wfield which apply (Usually obtained via $bits). radix - The <uvm_radix_enum> to use. This method will trigger a <do_record_field_int> call. |
void | record_field_real(string name, real value) | Function: record_field_real Records a real field. Parameters: name - Name of the field value - Value of the field to record This method will trigger a <do_record_field_real> call. |
void | record_object(string name, uvm_object value) | Function: record_object Records an object field. Parameters: name - Name of the field value - Object to record The implementation must use the <recursion_policy> and to determine exactly what should be recorded. |
void | record_string(string name, string value) | Function: record_string Records a string field. Parameters: name - Name of the field value - Value of the field |
void | record_time(string name, time value) | Function: record_time Records a time field. Parameters: name - Name of the field value - Value of the field |
void | record_generic(string name, string value, string type_name) | Function: record_generic Records a name/value pair, where ~value~ has been converted to a string. For example: | recorder.record_generic("myvar","var_type", $sformatf("%0d",myvar), 32); Parameters: name - Name of the field value - Value of the field type_name - ~optional~ Type name of the field |
bit | use_record_attribute() | |
integer | get_record_attribute_handle() | |
void | do_open(uvm_tr_stream stream, time open_time, string type_name) | |
void | do_close(time close_time) | |
void | do_free() | |
void | do_record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix) | |
void | do_record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix) | |
void | do_record_field_real(string name, real value) | |
void | do_record_object(string name, uvm_object value) | |
void | do_record_string(string name, string value) | |
void | do_record_time(string name, time value) | |
void | do_record_generic(string name, string value, string type_name) | |
bit | open_file() | |
integer | create_stream(string name, string t, string scope) | |
void | m_set_attribute(integer txh, string nm, string value) | |
void | set_attribute(integer txh, string nm, anonymous value, uvm_radix_enum radix, integer numbits) | |
integer | check_handle_kind(string htype, integer handle) | |
integer | begin_tr(string txtype, integer stream, string nm, string label, string desc, time begin_time) | |
void | end_tr(integer handle, time end_time) | |
void | link_tr(integer h1, integer h2, string relation) | |
void | free_tr(integer handle) |
Extends: uvm_recorder
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_text_tr_database | m_text_db | Variable- m_text_db Reference to the text database backend |
uvm_scope_stack | scope | Variable- scope Imeplementation detail |
string | filename | |
bit | filename_set |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Constructor Parameters: name - Instance name |
void | do_open(uvm_tr_stream stream, time open_time, string type_name) | |
void | do_close(time close_time) | |
void | do_free() | |
void | do_record_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix) | |
void | do_record_field_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix) | |
void | do_record_field_real(string name, real value) | |
void | do_record_object(string name, uvm_object value) | |
void | do_record_string(string name, string value) | |
void | do_record_time(string name, time value) | |
void | do_record_generic(string name, string value, string type_name) | |
void | write_attribute(string nm, uvm_bitstream_t value, uvm_radix_enum radix, integer numbits) | Function: write_attribute Outputs an integral attribute to the textual log Parameters: nm - Name of the attribute value - Value radix - Radix of the output numbits - number of valid bits |
void | write_attribute_int(string nm, uvm_integral_t value, uvm_radix_enum radix, integer numbits) | Function: write_attribute_int Outputs an integral attribute to the textual log Parameters: nm - Name of the attribute value - Value radix - Radix of the output numbits - number of valid bits |
bit | open_file() | |
integer | create_stream(string name, string t, string scope) | |
void | m_set_attribute(integer txh, string nm, string value) | |
void | set_attribute(integer txh, string nm, anonymous value, uvm_radix_enum radix, integer numbits) | |
integer | check_handle_kind(string htype, integer handle) | |
integer | begin_tr(string txtype, integer stream, string nm, string label, string desc, time begin_time) | |
void | end_tr(integer handle, time end_time) | |
void | link_tr(integer h1, integer h2, string relation) | |
void | free_tr(integer handle) | free_tr |
Extends: uvm_object
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
bit | pre_trigger(uvm_event e, T data) | |
void | post_trigger(uvm_event e, T data) | |
uvm_object | create(string name) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | type_name | |
event | m_event | |
int | num_waiters | |
bit | on | |
time | trigger_time | |
uvm_event_callback[] | callbacks |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | wait_on(bit delta) | |
void | wait_off(bit delta) | |
void | wait_trigger() | |
void | wait_ptrigger() | |
time | get_trigger_time() | |
bit | is_on() | |
bit | is_off() | |
void | reset(bit wakeup) | |
void | cancel() | |
int | get_num_waiters() | |
string | get_type_name() | |
void | do_print(uvm_printer printer) | |
void | do_copy(uvm_object rhs) |
Extends: uvm_event_base
| Type | Name | Description |
|---|---|---|
string | type_name | |
T | trigger_data |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | wait_trigger_data(T data) | |
void | wait_ptrigger_data(T data) | |
void | trigger(T data) | |
T | get_trigger_data() | |
string | get_type_name() | |
void | add_callback(uvm_event_callback cb, bit append) | |
void | delete_callback(uvm_event_callback cb) | |
void | do_print(uvm_printer printer) | |
void | do_copy(uvm_object rhs) | do_copy |
uvm_object | create(string name) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
int | threshold | |
int | num_waiters | |
bit | at_threshold | |
bit | auto_reset | |
uvm_event | m_event | |
string | type_name |
| Type | Method | Description |
|---|---|---|
logic | new(string name, int threshold) | |
void | wait_for() | |
void | reset(bit wakeup) | |
void | set_auto_reset(bit value) | |
void | set_threshold(int threshold) | |
int | get_threshold() | |
int | get_num_waiters() | |
void | cancel() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | m_trigger() | |
void | do_print(uvm_printer printer) | |
void | do_copy(uvm_object rhs) |
| Type | Name | Description |
|---|---|---|
string | typename | |
uvm_callbacks_base[] | typeid_map | |
uvm_typeid_base[] | type_map |
Extends: uvm_typeid_base
| Type | Name | Description |
|---|---|---|
uvm_typeid | m_b_inst |
| Type | Method | Description |
|---|---|---|
uvm_typeid | get() |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
bit | m_tracing | |
this_type | m_b_inst | |
uvm_pool | m_pool | |
this_type[] | m_this_type | one to many T->T/CB |
uvm_typeid_base | m_super_type | one to one relation |
uvm_typeid_base[] | m_derived_types | one to many relation |
| Type | Method | Description |
|---|---|---|
this_type | m_initialize() | |
bit | m_am_i_a(uvm_object obj) | |
bit | m_is_for_me(uvm_callback cb) | |
bit | m_is_registered(uvm_object obj, uvm_callback cb) | |
uvm_queue | m_get_tw_cb_q(uvm_object obj) | |
void | m_add_tw_cbs(uvm_callback cb, uvm_apprepend ordering) | |
bit | m_delete_tw_cbs(uvm_callback cb) | |
bit | check_registration(uvm_object obj, uvm_callback cb) | Check registration. To test registration, start at this class and work down the class hierarchy. If any class returns true then the pair is legal. |
Extends: uvm_callbacks_base
| Type | Name | Description |
|---|---|---|
uvm_queue | m_tw_cb_q | |
string | m_typename | |
this_type | m_t_inst |
| Type | Method | Description |
|---|---|---|
this_type | m_initialize() | |
bit | m_am_i_a(uvm_object obj) | |
uvm_queue | m_get_tw_cb_q(uvm_object obj) | |
int | m_cb_find(uvm_queue q, uvm_callback cb) | |
int | m_cb_find_name(uvm_queue q, string name, string where) | |
void | m_add_tw_cbs(uvm_callback cb, uvm_apprepend ordering) | |
bit | m_delete_tw_cbs(uvm_callback cb) | |
void | display(T obj) |
| Type | Name | Description |
|---|---|---|
this_type | m_inst | |
uvm_typeid_base | m_typeid | |
uvm_typeid_base | m_cb_typeid | |
string | m_typename | |
string | m_cb_typename | |
uvm_report_object | reporter | |
uvm_callbacks | m_base_inst | |
bit | m_registered | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
bit | m_tracing | |
this_type | m_b_inst | |
uvm_pool | m_pool | |
this_type[] | m_this_type | one to many T->T/CB |
uvm_typeid_base | m_super_type | one to one relation |
uvm_typeid_base[] | m_derived_types | one to many relation |
uvm_queue | m_tw_cb_q | |
uvm_typed_callbacks | m_t_inst |
| Type | Method | Description |
|---|---|---|
this_type | get() | |
bit | m_register_pair(string tname, string cbname) | |
bit | m_is_registered(uvm_object obj, uvm_callback cb) | |
bit | m_is_for_me(uvm_callback cb) | |
void | add(T obj, uvm_callback cb, uvm_apprepend ordering) | |
void | add_by_name(string name, uvm_callback cb, uvm_component root, uvm_apprepend ordering) | |
void | delete(T obj, uvm_callback cb) | |
void | delete_by_name(string name, uvm_callback cb, uvm_component root) | |
void | m_get_q(uvm_queue q, T obj) | |
CB | get_first(int itr, T obj) | |
CB | get_last(int itr, T obj) | |
CB | get_next(int itr, T obj) | |
CB | get_prev(int itr, T obj) | |
void | display(T obj) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_typed_callbacks | m_initialize() | |
bit | m_am_i_a(uvm_object obj) | |
uvm_queue | m_get_tw_cb_q(uvm_object obj) | |
void | m_add_tw_cbs(uvm_callback cb, uvm_apprepend ordering) | |
bit | m_delete_tw_cbs(uvm_callback cb) | |
bit | check_registration(uvm_object obj, uvm_callback cb) | Check registration. To test registration, start at this class and work down the class hierarchy. If any class returns true then the pair is legal. |
int | m_cb_find(uvm_queue q, uvm_callback cb) | |
int | m_cb_find_name(uvm_queue q, string name, string where) |
| Type | Name | Description |
|---|---|---|
this_type | m_d_inst | |
this_user_type | m_user_inst | |
this_super_type | m_super_inst | |
uvm_typeid_base | m_s_typeid | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
bit | m_tracing | |
this_type | m_b_inst | |
uvm_pool | m_pool | |
this_type[] | m_this_type | one to many T->T/CB |
uvm_typeid_base | m_super_type | one to one relation |
uvm_typeid_base[] | m_derived_types | one to many relation |
uvm_queue | m_tw_cb_q | |
string | m_typename | |
uvm_typed_callbacks | m_t_inst | |
uvm_callbacks | m_inst | |
uvm_typeid_base | m_typeid | |
uvm_typeid_base | m_cb_typeid | |
string | m_cb_typename | |
uvm_report_object | reporter | |
uvm_callbacks | m_base_inst | |
bit | m_registered |
| Type | Method | Description |
|---|---|---|
this_type | get() | |
bit | register_super_type(string tname, string sname) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_typed_callbacks | m_initialize() | |
bit | m_am_i_a(uvm_object obj) | |
bit | m_is_for_me(uvm_callback cb) | |
bit | m_is_registered(uvm_object obj, uvm_callback cb) | |
uvm_queue | m_get_tw_cb_q(uvm_object obj) | |
void | m_add_tw_cbs(uvm_callback cb, uvm_apprepend ordering) | |
bit | m_delete_tw_cbs(uvm_callback cb) | |
bit | check_registration(uvm_object obj, uvm_callback cb) | Check registration. To test registration, start at this class and work down the class hierarchy. If any class returns true then the pair is legal. |
int | m_cb_find(uvm_queue q, uvm_callback cb) | |
int | m_cb_find_name(uvm_queue q, string name, string where) | |
void | display(T obj) | |
bit | m_register_pair(string tname, string cbname) | |
void | add(T obj, uvm_callback cb, uvm_apprepend ordering) | |
void | add_by_name(string name, uvm_callback cb, uvm_component root, uvm_apprepend ordering) | |
void | delete(T obj, uvm_callback cb) | |
void | delete_by_name(string name, uvm_callback cb, uvm_component root) | |
void | m_get_q(uvm_queue q, T obj) | |
CB | get_first(int itr, T obj) | |
CB | get_last(int itr, T obj) | |
CB | get_next(int itr, T obj) | |
CB | get_prev(int itr, T obj) |
| Type | Name | Description |
|---|---|---|
int | m_i | |
T | m_obj | |
CB | m_cb |
| Type | Method | Description |
|---|---|---|
logic | new(T obj) | |
CB | first() | |
CB | last() | |
CB | next() | |
CB | prev() | |
CB | get_cb() |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
uvm_report_object | reporter | |
bit | m_enabled | |
string | type_name |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
bit | callback_mode(int on) | |
bit | is_enabled() | |
string | get_type_name() |
| Type | Name | Description |
|---|---|---|
uvm_action | _action | |
string | _name |
| Type | Method | Description |
|---|---|---|
string | get_name() | |
void | set_name(string name) | |
uvm_action | get_action() | |
void | set_action(uvm_action action) | |
void | print(uvm_printer printer) | |
void | record(uvm_recorder recorder) | |
void | copy(uvm_report_message_element_base rhs) | |
uvm_report_message_element_base | clone() | |
void | do_print(uvm_printer printer) | |
void | do_record(uvm_recorder recorder) | |
void | do_copy(uvm_report_message_element_base rhs) | |
uvm_report_message_element_base | do_clone() |
Extends: uvm_report_message_element_base
| Type | Name | Description |
|---|---|---|
uvm_bitstream_t | _val | |
int | _size | |
uvm_radix_enum | _radix |
| Type | Method | Description |
|---|---|---|
uvm_bitstream_t | get_value(int size, uvm_radix_enum radix) | |
void | set_value(uvm_bitstream_t value, int size, uvm_radix_enum radix) | |
void | do_print(uvm_printer printer) | |
void | do_record(uvm_recorder recorder) | |
void | do_copy(uvm_report_message_element_base rhs) | |
uvm_report_message_element_base | do_clone() |
Extends: uvm_report_message_element_base
| Type | Name | Description |
|---|---|---|
string | _val |
| Type | Method | Description |
|---|---|---|
string | get_value() | |
void | set_value(string value) | |
void | do_print(uvm_printer printer) | |
void | do_record(uvm_recorder recorder) | |
void | do_copy(uvm_report_message_element_base rhs) | |
uvm_report_message_element_base | do_clone() |
Extends: uvm_report_message_element_base
| Type | Name | Description |
|---|---|---|
uvm_object | _val |
| Type | Method | Description |
|---|---|---|
uvm_object | get_value() | |
void | set_value(uvm_object value) | |
void | do_print(uvm_printer printer) | |
void | do_record(uvm_recorder recorder) | |
void | do_copy(uvm_report_message_element_base rhs) | |
uvm_report_message_element_base | do_clone() |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
uvm_report_message_element_base[] | elements | |
string | type_name |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
int | size() | |
void | delete(int index) | |
void | delete_elements() | |
queue_of_element | get_elements() | |
void | add_int(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix, uvm_action action) | |
void | add_string(string name, string value, uvm_action action) | |
void | add_object(string name, uvm_object obj, uvm_action action) | |
void | do_print(uvm_printer printer) | |
void | do_record(uvm_recorder recorder) | |
void | do_copy(uvm_object rhs) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
uvm_report_object | _report_object | |
uvm_report_handler | _report_handler | |
uvm_report_server | _report_server | |
uvm_severity | _severity | |
string | _id | |
string | _message | |
int | _verbosity | |
string | _filename | |
int | _line | |
string | _context_name | |
uvm_action | _action | |
UVM_FILE | _file | |
uvm_report_message_element_container | _report_message_element_container | |
string | type_name |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
uvm_report_message | new_report_message(string name) | |
void | do_print(uvm_printer printer) | |
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
void | do_copy(uvm_object rhs) | |
uvm_report_object | get_report_object() | |
void | set_report_object(uvm_report_object ro) | |
uvm_report_handler | get_report_handler() | |
void | set_report_handler(uvm_report_handler rh) | |
uvm_report_server | get_report_server() | |
void | set_report_server(uvm_report_server rs) | |
uvm_severity | get_severity() | |
void | set_severity(uvm_severity sev) | |
string | get_id() | |
void | set_id(string id) | |
string | get_message() | |
void | set_message(string msg) | |
int | get_verbosity() | |
void | set_verbosity(int ver) | |
string | get_filename() | |
void | set_filename(string fname) | |
int | get_line() | |
void | set_line(int ln) | |
string | get_context() | |
void | set_context(string cn) | |
uvm_action | get_action() | |
void | set_action(uvm_action act) | |
UVM_FILE | get_file() | |
void | set_file(UVM_FILE fl) | |
uvm_report_message_element_container | get_element_container() | |
void | set_report_message(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name) | |
void | m_record_message(uvm_recorder recorder) | |
void | m_record_core_properties(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | add_int(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix, uvm_action action) | |
void | add_string(string name, string value, uvm_action action) | |
void | add_object(string name, uvm_object obj, uvm_action action) |
| Type | Name | Description |
|---|---|---|
bit | sev_specified | |
bit | id_specified | |
uvm_severity | sev | |
string | id | |
bit | is_on |
Extends: uvm_callback
| Type | Name | Description |
|---|---|---|
bit | m_register_cb_uvm_report_catcher | |
uvm_report_message | m_modified_report_message | |
uvm_report_message | m_orig_report_message | |
bit | m_set_action_called | |
int | m_demoted_fatal | |
int | m_demoted_error | |
int | m_demoted_warning | |
int | m_caught_fatal | |
int | m_caught_error | |
int | m_caught_warning | |
int | DO_NOT_CATCH | |
int | DO_NOT_MODIFY | |
int | m_debug_flags | |
bit | do_report |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
uvm_report_object | get_client() | |
uvm_severity | get_severity() | |
string | get_context() | |
int | get_verbosity() | |
string | get_id() | |
string | get_message() | |
uvm_action | get_action() | |
string | get_fname() | |
int | get_line() | |
uvm_report_message_element_container | get_element_container() | |
void | set_severity(uvm_severity severity) | |
void | set_verbosity(int verbosity) | |
void | set_id(string id) | |
void | set_message(string message) | |
void | set_action(uvm_action action) | |
void | set_context(string context_str) | |
void | add_int(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix, uvm_action action) | |
void | add_string(string name, string value, uvm_action action) | |
void | add_object(string name, uvm_object obj, uvm_action action) | |
uvm_report_catcher | get_report_catcher(string name) | |
void | print_catcher(UVM_FILE file) | |
void | debug_report_catcher(int what) | |
action_e | catch() | |
void | uvm_report_fatal(string id, string message, int verbosity, string fname, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string fname, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string fname, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string fname, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string fname, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message msg) | |
void | issue() | |
int | process_all_report_catchers(uvm_report_message rm) | |
int | process_report_catcher() | |
void | summarize() |
Extends: uvm_object
| Type | Method | Description |
|---|---|---|
string | get_type_name() | |
logic | new(string name) | |
void | set_max_quit_count(int count, bit overridable) | |
int | get_max_quit_count() | |
void | set_quit_count(int quit_count) | |
int | get_quit_count() | |
void | set_severity_count(uvm_severity severity, int count) | |
int | get_severity_count(uvm_severity severity) | |
void | set_id_count(string id, int count) | |
int | get_id_count(string id) | |
void | get_id_set(string[] q) | |
void | get_severity_set(uvm_severity[] q) | |
void | set_message_database(uvm_tr_database database) | |
uvm_tr_database | get_message_database() | |
void | do_copy(uvm_object rhs) | Function: do_copy copies all message statistic severity,id counts to the destination uvm_report_server the copy is cummulative (only items from the source are transferred, already existing entries are not deleted, existing entries/counts are overridden when they exist in the source set) |
void | process_report_message(uvm_report_message report_message) | |
void | execute_report_message(uvm_report_message report_message, string composed_message) | |
string | compose_report_message(uvm_report_message report_message, string report_object_name) | |
void | report_summarize(UVM_FILE file) | |
void | summarize(UVM_FILE file) | |
void | set_server(uvm_report_server server) | |
uvm_report_server | get_server() |
Extends: uvm_report_server
| Type | Name | Description |
|---|---|---|
int | m_quit_count | |
int | m_max_quit_count | |
bit | max_quit_overridable | |
int[] | m_severity_count | |
int[] | m_id_count | |
uvm_tr_database | m_message_db | |
unknown[] | m_streams | ro.name,rh.name |
bit | enable_report_id_count_summary | Variable: enable_report_id_count_summary A flag to enable report count summary for each ID |
bit | record_all_messages | Variable: record_all_messages A flag to force recording of all messages (add UVM_RM_RECORD action) |
bit | show_verbosity | Variable: show_verbosity A flag to include verbosity in the messages, e.g. "UVM_INFO(UVM_MEDIUM) file.v(3) @ 60: reporter ID0 Message 0" |
bit | show_terminator | Variable: show_terminator A flag to add a terminator in the messages, e.g. "UVM_INFO file.v(3) @ 60: reporter ID0 Message 0 -UVM_INFO" |
| Type | Method | Description |
|---|---|---|
string | get_type_name() | Needed for callbacks |
logic | new(string name) | |
void | do_print(uvm_printer printer) | |
int | get_max_quit_count() | |
void | set_max_quit_count(int count, bit overridable) | |
int | get_quit_count() | |
void | set_quit_count(int quit_count) | |
void | incr_quit_count() | |
void | reset_quit_count() | |
bit | is_quit_count_reached() | |
int | get_severity_count(uvm_severity severity) | |
void | set_severity_count(uvm_severity severity, int count) | |
void | incr_severity_count(uvm_severity severity) | |
void | reset_severity_counts() | |
int | get_id_count(string id) | |
void | set_id_count(string id, int count) | |
void | incr_id_count(string id) | |
void | set_message_database(uvm_tr_database database) | |
uvm_tr_database | get_message_database() | |
void | get_severity_set(uvm_severity[] q) | |
void | get_id_set(string[] q) | |
void | f_display(UVM_FILE file, string str) | |
void | process_report_message(uvm_report_message report_message) | |
void | execute_report_message(uvm_report_message report_message, string composed_message) | |
string | compose_report_message(uvm_report_message report_message, string report_object_name) | |
void | report_summarize(UVM_FILE file) | |
void | process_report(uvm_severity severity, string name, string id, string message, uvm_action action, UVM_FILE file, string filename, int line, string composed_message, int verbosity_level, uvm_report_object client) | |
string | compose_message(uvm_severity severity, string name, string id, string message, string filename, int line) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
int | m_max_verbosity_level | |
uvm_id_verbosities_array | id_verbosities | id verbosity settings : default and severity |
uvm_id_verbosities_array[] | severity_id_verbosities | |
uvm_id_actions_array | id_actions | actions |
uvm_action[] | severity_actions | |
uvm_id_actions_array[] | severity_id_actions | |
uvm_sev_override_array | sev_overrides | severity overrides |
uvm_sev_override_array[] | sev_id_overrides | |
UVM_FILE | default_file_handle | file handles : default, severity, action, (severity,id) |
uvm_id_file_array | id_file_handles | |
UVM_FILE[] | severity_file_handles | |
uvm_id_file_array[] | severity_id_file_handles | |
string | type_name |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | do_print(uvm_printer printer) | |
void | process_report_message(uvm_report_message report_message) | |
string | format_action(uvm_action action) | |
void | initialize() | |
UVM_FILE | get_severity_id_file(uvm_severity severity, string id) | |
void | set_verbosity_level(int verbosity_level) | |
int | get_verbosity_level(uvm_severity severity, string id) | |
uvm_action | get_action(uvm_severity severity, string id) | |
UVM_FILE | get_file_handle(uvm_severity severity, string id) | |
void | set_severity_action(uvm_severity severity, uvm_action action) | |
void | set_id_action(string id, uvm_action action) | |
void | set_severity_id_action(uvm_severity severity, string id, uvm_action action) | |
void | set_id_verbosity(string id, int verbosity) | |
void | set_severity_id_verbosity(uvm_severity severity, string id, int verbosity) | |
void | set_default_file(UVM_FILE file) | |
void | set_severity_file(uvm_severity severity, UVM_FILE file) | |
void | set_id_file(string id, UVM_FILE file) | |
void | set_severity_id_file(uvm_severity severity, string id, UVM_FILE file) | |
void | set_severity_override(uvm_severity cur_severity, uvm_severity new_severity) | |
void | set_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity) | |
void | report(uvm_severity severity, string name, string id, string message, int verbosity_level, string filename, int line, uvm_report_object client) | |
bit | run_hooks(uvm_report_object client, uvm_severity severity, string id, string message, int verbosity, string filename, int line) | |
void | dump_state() |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
uvm_report_handler | m_rh |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
int | get_report_verbosity_level(uvm_severity severity, string id) | |
int | get_report_max_verbosity_level() | |
void | set_report_verbosity_level(int verbosity_level) | |
void | set_report_id_verbosity(string id, int verbosity) | Function: set_report_id_verbosity |
void | set_report_severity_id_verbosity(uvm_severity severity, string id, int verbosity) | |
int | get_report_action(uvm_severity severity, string id) | |
void | set_report_severity_action(uvm_severity severity, uvm_action action) | Function: set_report_severity_action |
void | set_report_id_action(string id, uvm_action action) | Function: set_report_id_action |
void | set_report_severity_id_action(uvm_severity severity, string id, uvm_action action) | |
int | get_report_file_handle(uvm_severity severity, string id) | |
void | set_report_default_file(UVM_FILE file) | |
void | set_report_id_file(string id, UVM_FILE file) | |
void | set_report_severity_file(uvm_severity severity, UVM_FILE file) | Function: set_report_severity_file |
void | set_report_severity_id_file(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity) | Function: set_report_severity_override |
void | set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity) | Function: set_report_severity_id_override These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~. |
void | set_report_handler(uvm_report_handler handler) | |
uvm_report_handler | get_report_handler() | |
void | reset_report_handler() | |
bit | report_info_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_error_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_warning_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_fatal_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_hook(string id, string message, int verbosity, string filename, int line) | |
void | report_header(UVM_FILE file) | |
void | report_summarize(UVM_FILE file) | |
void | die() | |
void | set_report_max_quit_count(int max_count) | |
uvm_report_server | get_report_server() | |
void | dump_report_state() | |
uvm_report_object | m_get_report_object() |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder |
| Type | Method | Description |
|---|---|---|
uvm_transaction | new(string name, uvm_component initiator) | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
void | do_print(uvm_printer printer) | |
void | do_record(uvm_recorder recorder) | |
void | do_copy(uvm_object rhs) | |
integer | m_begin_tr(time begin_time, integer parent_handle) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
bit | m_register_cb_uvm_phase_cb | |
int | max_ready_to_end_iter | |
uvm_phase_type | m_phase_type | |
uvm_phase | m_parent | our 'schedule' node or points 'up' one level |
uvm_phase | m_imp | phase imp to call when we execute this node |
uvm_phase_state | m_state | |
int | m_run_count | num times this phase has executed |
anonymous | m_phase_proc | |
int | m_num_procs_not_yet_returned | |
bit[] | m_predecessors | |
bit[] | m_successors | |
uvm_phase | m_end_node | |
bit[] | m_executing_phases | |
uvm_phase[] | m_sync | schedule instance to which we are synced |
uvm_objection | phase_done | phase done objection |
int | m_ready_to_end_count | |
bit | m_jump_bkwd | |
bit | m_jump_fwd | |
uvm_phase | m_jump_phase | |
bit | m_premature_end | |
anonymous | m_phase_hopper | |
bit | m_phase_trace | |
bit | m_use_ovm_run_semantic |
| Type | Method | Description |
|---|---|---|
uvm_phase | new(string name, uvm_phase_type phase_type, uvm_phase parent) | |
uvm_phase_type | get_phase_type() | |
uvm_phase_state | get_state() | |
int | get_run_count() | |
uvm_phase | find_by_name(string name, bit stay_in_scope) | |
uvm_phase | find(uvm_phase phase, bit stay_in_scope) | |
bit | is(uvm_phase phase) | |
bit | is_before(uvm_phase phase) | |
bit | is_after(uvm_phase phase) | |
void | exec_func(uvm_component comp, uvm_phase phase) | |
void | exec_task(uvm_component comp, uvm_phase phase) | |
void | add(uvm_phase phase, uvm_phase with_phase, uvm_phase after_phase, uvm_phase before_phase) | |
uvm_phase | get_parent() | |
string | get_full_name() | |
uvm_phase | get_schedule(bit hier) | |
string | get_schedule_name(bit hier) | |
uvm_domain | get_domain() | |
uvm_phase | get_imp() | |
string | get_domain_name() | |
void | get_adjacent_predecessor_nodes(uvm_phase[] pred) | |
void | get_adjacent_successor_nodes(uvm_phase[] succ) | |
void | m_report_null_objection(uvm_object obj, string description, int count, string action) | |
uvm_objection | get_objection() | Function: get_objection Return the <uvm_objection> that gates the termination of the phase. |
void | raise_objection(uvm_object obj, string description, int count) | |
void | drop_objection(uvm_object obj, string description, int count) | |
int | get_objection_count(uvm_object obj) | |
void | sync(uvm_domain target, uvm_phase phase, uvm_phase with_phase) | |
void | unsync(uvm_domain target, uvm_phase phase, uvm_phase with_phase) | |
void | wait_for_state(uvm_phase_state state, uvm_wait_op op) | |
void | jump(uvm_phase phase) | |
void | set_jump_phase(uvm_phase phase) | |
void | end_prematurely() | |
void | jump_all(uvm_phase phase) | |
uvm_phase | get_jump_target() | |
uvm_phase | m_find_predecessor(uvm_phase phase, bit stay_in_scope, uvm_phase orig_phase) | |
uvm_phase | m_find_successor(uvm_phase phase, bit stay_in_scope, uvm_phase orig_phase) | |
uvm_phase | m_find_predecessor_by_name(string name, bit stay_in_scope, uvm_phase orig_phase) | |
uvm_phase | m_find_successor_by_name(string name, bit stay_in_scope, uvm_phase orig_phase) | |
void | m_print_successors() | |
void | traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state) | |
void | execute(uvm_component comp, uvm_phase phase) | |
uvm_phase | get_begin_node() | |
uvm_phase | get_end_node() | |
int | get_ready_to_end_count() | |
void | get_predecessors_for_successors(bit[] pred_of_succ) | |
void | m_wait_for_pred() | |
void | clear(uvm_phase_state state) | |
void | clear_successors(uvm_phase_state state, uvm_phase end_state) | |
void | m_run_phases() | |
void | execute_phase() | |
void | m_terminate_phase() | |
void | m_print_termination_state() | |
void | wait_for_self_and_siblings_to_drop() | |
void | kill() | |
void | kill_successors() | |
string | convert2string() | |
string | m_aa2string(bit[] aa) | |
bit | is_domain() | |
void | m_get_transitive_children(uvm_phase[] phases) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_phase | m_phase | |
uvm_phase_state | m_prev_state | |
uvm_phase | m_jump_to |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
uvm_phase_state | get_state() | |
uvm_phase_state | get_prev_state() | |
uvm_phase | jump_to() | Function: jump_to() If the current state is ~UVM_PHASE_ENDED~ or ~UVM_PHASE_JUMPING~ because of a phase jump, returns the phase that is the target of jump. Returns ~null~ otherwise. |
Extends: uvm_callback
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new Constructor |
void | phase_state_change(uvm_phase phase, uvm_phase_state_change change) |
Extends: uvm_phase
| Type | Name | Description |
|---|---|---|
uvm_domain | m_common_domain | |
uvm_domain | m_uvm_domain | run-time phases |
uvm_domain[] | m_domains | |
uvm_phase | m_uvm_schedule |
| Type | Method | Description |
|---|---|---|
void | get_domains(uvm_domain[] domains) | |
uvm_phase | get_uvm_schedule() | |
uvm_domain | get_common_domain() | |
void | add_uvm_phases(uvm_phase schedule) | |
uvm_domain | get_uvm_domain() | |
logic | new(string name) | Function: new Create a new instance of a phase domain. |
void | jump(uvm_phase phase) | Function: jump jumps all active phases of this domain to to-phase if there is a path between active-phase and to-phase |
void | jump_all(uvm_phase phase) |
Extends: uvm_phase
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new Create a new instance of a bottom-up phase. |
void | traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state) | |
void | execute(uvm_component comp, uvm_phase phase) |
Extends: uvm_phase
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new Create a new instance of a top-down phase |
void | traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state) | |
void | execute(uvm_component comp, uvm_phase phase) |
Extends: uvm_phase
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new Create a new instance of a task-based phase |
void | traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state) | |
void | m_traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state) | |
void | execute(uvm_component comp, uvm_phase phase) |
Extends: uvm_topdown_phase
| Type | Name | Description |
|---|---|---|
uvm_build_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_func(uvm_component comp, uvm_phase phase) | |
uvm_build_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_bottomup_phase
| Type | Name | Description |
|---|---|---|
uvm_connect_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_func(uvm_component comp, uvm_phase phase) | |
uvm_connect_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_bottomup_phase
| Type | Name | Description |
|---|---|---|
uvm_end_of_elaboration_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_func(uvm_component comp, uvm_phase phase) | |
uvm_end_of_elaboration_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_bottomup_phase
| Type | Name | Description |
|---|---|---|
uvm_start_of_simulation_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_func(uvm_component comp, uvm_phase phase) | |
uvm_start_of_simulation_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_run_phase
Stimulate the DUT.
This <uvm_task_phase> calls the <uvm_component::run_phase> virtual method. This phase runs in parallel to the runtime phases, <uvm_pre_reset_phase> through <uvm_post_shutdown_phase>. All components in the testbench are synchronized with respect to the run phase regardless of the phase domain they belong to.
Upon Entry:
Indicates that power has been applied.
There should not have been any active clock edges before entry into this phase (e.g. x->1 transitions via initial blocks).
Current simulation time is still equal to 0 but some "delta cycles" may have occurred.
Typical Uses:
Components implement behavior that is exhibited for the entire run-time, across the various run-time phases.
Backward compatibility with OVM.
Exit Criteria:
The DUT no longer needs to be simulated, and
The <uvm_post_shutdown_phase> is ready to end
The run phase terminates in one of two ways.
All run_phase objections are dropped:
When all objections on the run_phase objection have been dropped, the phase ends and all of its threads are killed. If no component raises a run_phase objection immediately upon entering the phase, the phase ends immediately.
Timeout:
The phase ends if the timeout expires before all objections are dropped. By default, the timeout is set to 9200 seconds. You may override this via <uvm_root::set_timeout>.
If a timeout occurs in your simulation, or if simulation never ends despite completion of your test stimulus, then it usually indicates that a component continues to object to the end of a phase.
| Type | Name | Description |
|---|---|---|
uvm_run_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_run_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_bottomup_phase
Class: uvm_extract_phase
Extract data from different points of the verification environment.
<uvm_bottomup_phase> that calls the <uvm_component::extract_phase> method.
Upon Entry:
The DUT no longer needs to be simulated.
Simulation time will no longer advance.
Typical Uses:
Extract any remaining data and final state information from scoreboard and testbench components
Probe the DUT (via zero-time hierarchical references and/or backdoor accesses) for final state information.
Compute statistics and summaries.
Display final state information
Close files.
Exit Criteria:
All data has been collected and summarized.
| Type | Name | Description |
|---|---|---|
uvm_extract_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_func(uvm_component comp, uvm_phase phase) | |
uvm_extract_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_bottomup_phase
Class: uvm_check_phase
Check for any unexpected conditions in the verification environment.
<uvm_bottomup_phase> that calls the <uvm_component::check_phase> method.
Upon Entry:
All data has been collected.
Typical Uses:
Check that no unaccounted-for data remain.
Exit Criteria:
Test is known to have passed or failed.
| Type | Name | Description |
|---|---|---|
uvm_check_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_func(uvm_component comp, uvm_phase phase) | |
uvm_check_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_bottomup_phase
Class: uvm_report_phase
Report results of the test.
<uvm_bottomup_phase> that calls the <uvm_component::report_phase> method.
Upon Entry:
Test is known to have passed or failed.
Typical Uses:
Report test results.
Write results to file.
Exit Criteria:
End of test.
| Type | Name | Description |
|---|---|---|
uvm_report_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_func(uvm_component comp, uvm_phase phase) | |
uvm_report_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_topdown_phase
| Type | Name | Description |
|---|---|---|
uvm_final_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_func(uvm_component comp, uvm_phase phase) | |
uvm_final_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_pre_reset_phase
Before reset is asserted.
<uvm_task_phase> that calls the <uvm_component::pre_reset_phase> method. This phase starts at the same time as the <uvm_run_phase> unless a user defined phase is inserted in front of this phase.
Upon Entry:
Indicates that power has been applied but not necessarily valid or stable.
There should not have been any active clock edges before entry into this phase.
Typical Uses:
Wait for power good.
Components connected to virtual interfaces should initialize their output to X's or Z's.
Initialize the clock signals to a valid value
Assign reset signals to X (power-on reset).
Wait for reset signal to be asserted if not driven by the verification environment.
Exit Criteria:
Reset signal, if driven by the verification environment, is ready to be asserted.
Reset signal, if not driven by the verification environment, is asserted.
| Type | Name | Description |
|---|---|---|
uvm_pre_reset_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_pre_reset_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_reset_phase
Reset is asserted.
<uvm_task_phase> that calls the <uvm_component::reset_phase> method.
Upon Entry:
Indicates that the hardware reset signal is ready to be asserted.
Typical Uses:
Assert reset signals.
Components connected to virtual interfaces should drive their output to their specified reset or idle value.
Components and environments should initialize their state variables.
Clock generators start generating active edges.
De-assert the reset signal(s) just before exit.
Wait for the reset signal(s) to be de-asserted.
Exit Criteria:
Reset signal has just been de-asserted.
Main or base clock is working and stable.
At least one active clock edge has occurred.
Output signals and state variables have been initialized.
| Type | Name | Description |
|---|---|---|
uvm_reset_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_reset_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_post_reset_phase
After reset is de-asserted.
<uvm_task_phase> that calls the <uvm_component::post_reset_phase> method.
Upon Entry:
Indicates that the DUT reset signal has been de-asserted.
Typical Uses:
Components should start behavior appropriate for reset being inactive. For example, components may start to transmit idle transactions or interface training and rate negotiation. This behavior typically continues beyond the end of this phase.
Exit Criteria:
The testbench and the DUT are in a known, active state.
| Type | Name | Description |
|---|---|---|
uvm_post_reset_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_post_reset_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_pre_configure_phase
Before the DUT is configured by the SW.
<uvm_task_phase> that calls the <uvm_component::pre_configure_phase> method.
Upon Entry:
Indicates that the DUT has been completed reset and is ready to be configured.
Typical Uses:
Procedurally modify the DUT configuration information as described in the environment (and that will be eventually uploaded into the DUT).
Wait for components required for DUT configuration to complete training and rate negotiation.
Exit Criteria:
DUT configuration information is defined.
| Type | Name | Description |
|---|---|---|
uvm_pre_configure_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_pre_configure_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_configure_phase
The SW configures the DUT.
<uvm_task_phase> that calls the <uvm_component::configure_phase> method.
Upon Entry:
Indicates that the DUT is ready to be configured.
Typical Uses:
Components required for DUT configuration execute transactions normally.
Set signals and program the DUT and memories (e.g. read/write operations and sequences) to match the desired configuration for the test and environment.
Exit Criteria:
The DUT has been configured and is ready to operate normally.
| Type | Name | Description |
|---|---|---|
uvm_configure_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_configure_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_post_configure_phase
After the SW has configured the DUT.
<uvm_task_phase> that calls the <uvm_component::post_configure_phase> method.
Upon Entry:
Indicates that the configuration information has been fully uploaded.
Typical Uses:
Wait for configuration information to fully propagate and take effect.
Wait for components to complete training and rate negotiation.
Enable the DUT.
Sample DUT configuration coverage.
Exit Criteria:
The DUT has been fully configured and enabled and is ready to start operating normally.
| Type | Name | Description |
|---|---|---|
uvm_post_configure_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_post_configure_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_pre_main_phase
Before the primary test stimulus starts.
<uvm_task_phase> that calls the <uvm_component::pre_main_phase> method.
Upon Entry:
Indicates that the DUT has been fully configured.
Typical Uses:
Wait for components to complete training and rate negotiation.
Exit Criteria:
All components have completed training and rate negotiation.
All components are ready to generate and/or observe normal stimulus.
| Type | Name | Description |
|---|---|---|
uvm_pre_main_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_pre_main_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_main_phase
Primary test stimulus.
<uvm_task_phase> that calls the <uvm_component::main_phase> method.
Upon Entry:
The stimulus associated with the test objectives is ready to be applied.
Typical Uses:
Components execute transactions normally.
Data stimulus sequences are started.
Wait for a time-out or certain amount of time, or completion of stimulus sequences.
Exit Criteria:
Enough stimulus has been applied to meet the primary stimulus objective of the test.
| Type | Name | Description |
|---|---|---|
uvm_main_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_main_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_post_main_phase
After enough of the primary test stimulus.
<uvm_task_phase> that calls the <uvm_component::post_main_phase> method.
Upon Entry:
The primary stimulus objective of the test has been met.
Typical Uses:
Included for symmetry.
Exit Criteria:
None.
| Type | Name | Description |
|---|---|---|
uvm_post_main_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_post_main_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_pre_shutdown_phase
Before things settle down.
<uvm_task_phase> that calls the <uvm_component::pre_shutdown_phase> method.
Upon Entry:
None.
Typical Uses:
Included for symmetry.
Exit Criteria:
None.
| Type | Name | Description |
|---|---|---|
uvm_pre_shutdown_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_pre_shutdown_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_shutdown_phase
Letting things settle down.
<uvm_task_phase> that calls the <uvm_component::shutdown_phase> method.
Upon Entry:
None.
Typical Uses:
Wait for all data to be drained out of the DUT.
Extract data still buffered in the DUT, usually through read/write operations or sequences.
Exit Criteria:
All data has been drained or extracted from the DUT.
All interfaces are idle.
| Type | Name | Description |
|---|---|---|
uvm_shutdown_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_shutdown_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_task_phase
Class: uvm_post_shutdown_phase
After things have settled down.
<uvm_task_phase> that calls the <uvm_component::post_shutdown_phase> method. The end of this phase is synchronized to the end of the <uvm_run_phase> phase unless a user defined phase is added after this phase.
Upon Entry:
No more "data" stimulus is applied to the DUT.
Typical Uses:
Perform final checks that require run-time access to the DUT (e.g. read accounting registers or dump the content of memories).
Exit Criteria:
All run-time checks have been satisfied.
The <uvm_run_phase> phase is ready to end.
| Type | Name | Description |
|---|---|---|
uvm_post_shutdown_phase | m_inst | |
string | type_name |
| Type | Method | Description |
|---|---|---|
void | exec_task(uvm_component comp, uvm_phase phase) | |
uvm_post_shutdown_phase | get() | |
logic | new(string name) | |
string | get_type_name() |
Extends: uvm_report_object
| Type | Name | Description |
|---|---|---|
int | enable_stop_interrupt | |
bit | m_config_deprecated_warned | |
bit | m_config_set | |
bit | print_config_matches | |
bit | print_enabled | |
uvm_tr_database | tr_database | Variable: tr_database Specifies the <uvm_tr_database> object to use for <begin_tr>
and other methods in the . |
uvm_domain | m_domain | set_domain stores our domain handle |
uvm_phase[] | m_phase_imps | functors to override ovm_root defaults |
uvm_phase | m_current_phase | the most recently executed phase |
anonymous | m_phase_process | |
bit | m_build_done | |
int | m_phasing_active | |
uvm_component | m_parent | |
uvm_component[] | m_children | |
uvm_component[] | m_children_by_handle | |
uvm_tr_stream | m_main_stream | |
unknown[] | m_streams | |
uvm_recorder[] | m_tr_h | |
string | m_name | |
string | type_name | |
uvm_event_pool | event_pool | |
int | recording_detail | |
m_verbosity_setting[] | m_verbosity_settings | |
m_verbosity_setting[] | m_time_settings | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_action | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_sev |
| Type | Method | Description |
|---|---|---|
uvm_component | new(string name, uvm_component parent) | |
uvm_component | get_parent() | |
string | get_full_name() | |
void | get_children(uvm_component[] children) | |
uvm_component | get_child(string name) | |
int | get_next_child(string name) | |
int | get_first_child(string name) | |
int | get_num_children() | |
int | has_child(string name) | |
void | set_name(string name) | |
uvm_component | lookup(string name) | |
int | get_depth() | |
void | build_phase(uvm_phase phase) | |
void | build() | |
void | connect_phase(uvm_phase phase) | |
void | connect() | |
void | end_of_elaboration_phase(uvm_phase phase) | |
void | end_of_elaboration() | |
void | start_of_simulation_phase(uvm_phase phase) | |
void | start_of_simulation() | |
void | run_phase(uvm_phase phase) | |
void | run() | |
void | pre_reset_phase(uvm_phase phase) | |
void | reset_phase(uvm_phase phase) | |
void | post_reset_phase(uvm_phase phase) | |
void | pre_configure_phase(uvm_phase phase) | |
void | configure_phase(uvm_phase phase) | |
void | post_configure_phase(uvm_phase phase) | |
void | pre_main_phase(uvm_phase phase) | |
void | main_phase(uvm_phase phase) | |
void | post_main_phase(uvm_phase phase) | |
void | pre_shutdown_phase(uvm_phase phase) | |
void | shutdown_phase(uvm_phase phase) | |
void | post_shutdown_phase(uvm_phase phase) | |
void | extract_phase(uvm_phase phase) | |
void | extract() | |
void | check_phase(uvm_phase phase) | |
void | check() | |
void | report_phase(uvm_phase phase) | |
void | report() | |
void | final_phase(uvm_phase phase) | |
void | phase_started(uvm_phase phase) | |
void | phase_ready_to_end(uvm_phase phase) | |
void | phase_ended(uvm_phase phase) | |
void | set_domain(uvm_domain domain, int hier) | |
uvm_domain | get_domain() | |
void | define_domain(uvm_domain domain) | |
void | set_phase_imp(uvm_phase phase, uvm_phase imp, int hier) | |
void | suspend() | |
void | resume() | |
string | status() | |
void | kill() | |
void | do_kill_all() | |
void | stop_phase(uvm_phase phase) | |
void | stop(string ph_name) | |
void | resolve_bindings() | |
string | massage_scope(string scope) | |
void | set_config_int(string inst_name, string field_name, uvm_bitstream_t value) | |
void | set_config_string(string inst_name, string field_name, string value) | |
void | set_config_object(string inst_name, string field_name, uvm_object value, bit clone) | |
bit | get_config_int(string field_name, uvm_bitstream_t value) | |
bit | get_config_string(string field_name, string value) | |
bit | get_config_object(string field_name, uvm_object value, bit clone) | |
void | check_config_usage(bit recurse) | |
void | apply_config_settings(bit verbose) | |
void | print_config_settings(string field, uvm_component comp, bit recurse) | |
void | print_config(bit recurse, bit audit) | |
void | print_config_with_audit(bit recurse) | |
void | raised(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
uvm_component | create_component(string requested_type_name, string name) | |
uvm_object | create_object(string requested_type_name, string name) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type) | |
void | set_type_override(string original_type_name, string override_type_name, bit replace) | |
void | set_inst_override(string relative_inst_path, string original_type_name, string override_type_name) | |
void | print_override_info(string requested_type_name, string name) | |
void | set_report_id_verbosity_hier(string id, int verbosity) | |
void | set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity) | |
void | set_report_severity_action_hier(uvm_severity severity, uvm_action action) | |
void | set_report_id_action_hier(string id, uvm_action action) | |
void | set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action) | |
void | set_report_default_file_hier(UVM_FILE file) | |
void | set_report_severity_file_hier(uvm_severity severity, UVM_FILE file) | |
void | set_report_id_file_hier(string id, UVM_FILE file) | |
void | set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_verbosity_level_hier(int verbosity) | |
void | pre_abort() | |
void | accept_tr(uvm_transaction tr, time accept_time) | |
void | do_accept_tr(uvm_transaction tr) | |
integer | begin_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle) | |
integer | begin_child_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | do_begin_tr(uvm_transaction tr, string stream_name, integer tr_handle) | |
void | end_tr(uvm_transaction tr, time end_time, bit free_handle) | |
void | do_end_tr(uvm_transaction tr, integer tr_handle) | |
integer | record_error_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active) | |
integer | record_event_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active) | |
uvm_tr_stream | get_tr_stream(string name, string stream_type_name) | |
void | free_tr_stream(uvm_tr_stream stream) | |
uvm_tr_database | m_get_tr_database() | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
bit | m_add_child(uvm_component child) | |
void | m_set_full_name() | |
void | do_resolve_bindings() | |
void | do_flush() | |
void | flush() | |
void | m_extract_name(string name, string leaf, string remainder) | |
uvm_object | create(string name) | |
uvm_object | clone() | |
integer | m_begin_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
string | get_type_name() | |
void | do_print(uvm_printer printer) | |
void | m_set_cl_msg_args() | |
void | m_set_cl_verb() | |
void | m_set_cl_action() | |
void | m_set_cl_sev() | |
void | m_apply_verbosity_settings(uvm_phase phase) | |
void | m_do_pre_abort() |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
uvm_cmdline_processor | clp | |
bit | finish_on_completion | |
uvm_component[] | top_levels | |
bit | enable_print_topology | |
time | phase_timeout | |
uvm_root | m_inst | |
bit | m_phase_all_done | |
bit | m_relnotes_done |
| Type | Method | Description |
|---|---|---|
uvm_root | get() | |
string | get_type_name() | |
void | run_test(string test_name) | |
void | die() | |
void | set_timeout(time timeout, bit overridable) | |
uvm_component | find(string comp_match) | |
void | find_all(string comp_match, uvm_component[] comps, uvm_component comp) | |
void | print_topology(uvm_printer printer) | |
void | m_find_all_recurse(string comp_match, uvm_component[] comps, uvm_component comp) | |
uvm_root | new() | |
bit | m_add_child(uvm_component child) | |
void | build_phase(uvm_phase phase) | |
void | m_do_verbosity_settings() | |
void | m_do_timeout_settings() | |
void | m_do_factory_settings() | |
void | m_process_inst_override(string ovr) | |
void | m_process_type_override(string ovr) | |
void | m_do_config_settings() | |
void | m_do_max_quit_settings() | |
void | m_do_dump_args() | |
void | m_process_config(string cfg, bit is_int) | |
void | m_process_default_sequence(string cfg) | |
void | m_check_verbosity() | |
void | report_header(UVM_FILE file) | |
void | run_phase(uvm_phase phase) | |
void | phase_started(uvm_phase phase) | phase_started At end of elab phase we need to do tlm binding resolution. |
uvm_root | m_uvm_get_root() | |
void | stop_request() | backward compat only call global_stop_request() or uvm_test_done.stop_request() instead |
void | end_of_elaboration_phase(uvm_phase phase) |
Undocumented struct for storing clone bit along w/ object on set_config_object(...) calls
| Type | Name | Description |
|---|---|---|
uvm_object | obj | |
bit | clone |
| Type | Name | Description |
|---|---|---|
int | waiters | |
event | raised | |
event | dropped | |
event | all_dropped |
Extends: uvm_report_object
| Type | Name | Description |
|---|---|---|
bit | m_register_cb_uvm_objection_callback | |
bit | m_trace_mode | |
int[] | m_source_count | |
int[] | m_total_count | |
time[] | m_drain_time | |
uvm_objection_events[] | m_events | |
bit | m_top_all_dropped | |
uvm_root | m_top | |
uvm_objection[] | m_objections | |
uvm_objection_context_object[] | m_context_pool | |
unknown[] | m_drain_proc | |
uvm_objection_context_object[] | m_scheduled_list | |
uvm_objection_context_object[] | m_scheduled_contexts | |
uvm_objection_context_object[] | m_forked_list | |
uvm_objection_context_object[] | m_forked_contexts | |
bit | m_prop_mode | |
bit | m_cleared | for checking obj count<0 |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
bit | trace_mode(int mode) | |
void | m_report(uvm_object obj, uvm_object source_obj, string description, int count, string action) | |
uvm_object | m_get_parent(uvm_object obj) | |
void | m_propagate(uvm_object obj, uvm_object source_obj, string description, int count, bit raise, int in_top_thread) | |
void | set_propagate_mode(bit prop_mode) | Function: set_propagate_mode Sets the propagation mode for this objection. By default, objections support hierarchical propagation for components. For example, if we have the following basic component tree: | uvm_top.parent.child Any objections raised by 'child' would get propagated down to parent, and then to uvm_test_top. Resulting in the following counts and totals: | | count | total | | uvm_top.parent.child | 1 | 1 | | uvm_top.parent | 0 | 1 | | uvm_top | 0 | 1 | | While propagations such as these can be useful, if they are unused by the testbench then they are simply an unnecessary performance hit. If the testbench is not going to use this functionality, then the performance can be improved by setting the propagation mode to 0. When propagation mode is set to 0, all intermediate callbacks between the ~source~ and ~top~ will be skipped. This would result in the following counts and totals for the above objection: | | count | total | | uvm_top.parent.child | 1 | 1 | | uvm_top.parent | 0 | 0 | | uvm_top | 0 | 1 | | Since the propagation mode changes the behavior of the objection, it can only be safely changed if there are no objections ~raised~ or ~draining~. Any attempts to change the mode while objections are ~raised~ or ~draining~ will result in an error. |
bit | get_propagate_mode() | Function: get_propagate_mode Returns the propagation mode for this objection. |
void | raise_objection(uvm_object obj, string description, int count) | |
void | m_raise(uvm_object obj, uvm_object source_obj, string description, int count) | |
void | drop_objection(uvm_object obj, string description, int count) | |
void | m_drop(uvm_object obj, uvm_object source_obj, string description, int count, int in_top_thread) | |
void | clear(uvm_object obj) | |
void | m_execute_scheduled_forks() | |
void | m_forked_drain(uvm_object obj, uvm_object source_obj, string description, int count, int in_top_thread) | |
void | m_init_objections() | |
void | set_drain_time(uvm_object obj, time drain) | AE: set_drain_time(drain,obj=null)? |
void | raised(uvm_object obj, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_object obj, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_object obj, uvm_object source_obj, string description, int count) | |
void | get_objectors(uvm_object[] list) | |
void | wait_for(uvm_objection_event objt_event, uvm_object obj) | Task: wait_for Waits for the raised, dropped, or all_dropped ~event~ to occur in the given ~obj~. The task returns after all corresponding callbacks for that event have been executed. |
void | wait_for_total_count(uvm_object obj, int count) | |
int | get_objection_count(uvm_object obj) | |
int | get_objection_total(uvm_object obj) | |
time | get_drain_time(uvm_object obj) | |
string | m_display_objections(uvm_object obj, bit show_header) | |
string | convert2string() | |
void | display_objections(uvm_object obj, bit show_header) | |
type_id | get_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | do_copy(uvm_object rhs) |
Extends: uvm_objection
| Type | Name | Description |
|---|---|---|
uvm_test_done_objection | m_inst | |
bit | m_forced | |
bit | m_executing_stop_processes | |
int | m_n_stop_threads | |
time | stop_timeout |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | qualify(uvm_object obj, bit is_raise, string description) | |
void | m_do_stop_all(uvm_component comp) | |
void | stop_request() | |
void | m_stop_request() | |
void | all_dropped(uvm_object obj, uvm_object source_obj, string description, int count) | |
void | raise_objection(uvm_object obj, string description, int count) | |
void | drop_objection(uvm_object obj, string description, int count) | |
void | force_stop(uvm_object obj) | |
type_id | get_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
uvm_test_done_objection | get() |
Have a pool of context objects to use
| Type | Name | Description |
|---|---|---|
uvm_object | obj | |
uvm_object | source_obj | |
string | description | |
int | count | |
uvm_objection | objection |
| Type | Method | Description |
|---|---|---|
void | clear() | Clears the values stored within the object, preventing memory leaks from reused objects |
Extends: uvm_callback
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | raised(uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
uvm_objection | m_objection | |
uvm_heartbeat_callback | m_cb | |
uvm_component | m_cntxt | |
uvm_heartbeat_modes | m_mode | |
uvm_component[] | m_hblist | |
uvm_event | m_event | |
bit | m_started | |
event | m_stop_event | |
bit | m_added |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component cntxt, uvm_objection objection) | |
uvm_heartbeat_modes | set_mode(uvm_heartbeat_modes mode) | |
void | set_heartbeat(uvm_event e, uvm_component[] comps) | |
void | add(uvm_component comp) | |
void | remove(uvm_component comp) | |
void | start(uvm_event e) | |
void | stop() | |
void | m_start_hb_process() | |
void | m_enable_cb() | |
void | m_disable_cb() | |
void | m_hb_process() |
Extends: uvm_objection_callback
| Type | Name | Description |
|---|---|---|
int[] | cnt | |
time[] | last_trigger | |
uvm_object | target | |
uvm_coreservice_t | cs |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_object target) | |
void | raised(uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count) | |
void | reset_counts() | |
int | objects_triggered() |
| Type | Name | Description |
|---|---|---|
T[] | map |
| Type | Method | Description |
|---|---|---|
bit | from_name(string name, T value) | |
void | m_init_map() | |
logic | new() |
| Type | Name | Description |
|---|---|---|
string | comp_path | |
string | id | |
uvm_verbosity | verb | |
int | exec_time |
Extends: uvm_report_object
| Type | Name | Description |
|---|---|---|
uvm_cmdline_processor | m_inst | |
string[] | m_argv | |
string[] | m_plus_argv | |
string[] | m_uvm_argv |
| Type | Method | Description |
|---|---|---|
uvm_cmdline_processor | get_inst() | |
void | get_args(string[] args) | |
void | get_plusargs(string[] args) | |
void | get_uvm_args(string[] args) | |
int | get_arg_matches(string match, string[] args) | |
int | get_arg_value(string match, string value) | |
int | get_arg_values(string match, string[] values) | |
string | get_tool_name() | |
string | get_tool_version() | |
logic | new(string name) | |
bit | m_convert_verb(string verb_str, uvm_verbosity verb_enum) |
Extends: uvm_object
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | begin_v() | |
void | end_v() | |
void | visit(NODE node) |
Extends: uvm_object
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | get_immediate_children(STRUCTURE s, STRUCTURE[] children) |
Extends: uvm_object
| Type | Method | Description |
|---|---|---|
void | accept(STRUCTURE s, VISITOR v, uvm_structure_proxy p, bit invoke_begin_end) | |
logic | new(string name) |
| Type | Name | Description |
|---|---|---|
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | accept(STRUCTURE s, VISITOR v, uvm_structure_proxy p, bit invoke_begin_end) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() |
| Type | Name | Description |
|---|---|---|
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | accept(STRUCTURE s, VISITOR v, uvm_structure_proxy p, bit invoke_begin_end) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() |
| Type | Name | Description |
|---|---|---|
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | accept(STRUCTURE s, VISITOR v, uvm_structure_proxy p, bit invoke_begin_end) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() |
| Type | Name | Description |
|---|---|---|
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map |
| Type | Method | Description |
|---|---|---|
void | get_immediate_children(uvm_component s, uvm_component[] children) | |
logic | new(string name) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() |
| Type | Name | Description |
|---|---|---|
uvm_root | _root | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map |
| Type | Method | Description |
|---|---|---|
string | get_name_constraint() | |
void | visit(uvm_component node) | |
logic | new(string name) | |
void | begin_v() | |
void | end_v() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() |
Extends: uvm_object
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new Constructor |
void | set(T value) | |
bit | try_set(T value) | |
T | get() | |
bit | try_get(T value) |
uvm_simple_lock_dap
| Type | Name | Description |
|---|---|---|
T | m_value | |
bit | m_locked | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Constructor |
void | set(T value) | |
bit | try_set(T value) | |
T | get() | |
bit | try_get(T value) | |
void | lock() | Function: lock Locks the data value The data value cannot be updated via or <try_set> while locked. |
void | unlock() | Function: unlock Unlocks the data value |
bit | is_locked() | Function: is_locked Returns the state of the lock. Returns: 1 - The value is locked 0 - The value is unlocked |
void | do_copy(uvm_object rhs) | |
void | do_pack(uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
string | convert2string() | |
void | do_print(uvm_printer printer) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
string | get_type_name() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() |
uvm_get_to_lock_dap
| Type | Name | Description |
|---|---|---|
T | m_value | |
bit | m_locked | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Constructor |
void | set(T value) | |
bit | try_set(T value) | |
T | get() | |
bit | try_get(T value) | |
void | do_copy(uvm_object rhs) | |
void | do_pack(uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
string | convert2string() | |
void | do_print(uvm_printer printer) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
string | get_type_name() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() |
uvm_set_before_get_dap
| Type | Name | Description |
|---|---|---|
T | m_value | |
bit | m_set | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Constructor |
void | set(T value) | |
bit | try_set(T value) | |
T | get() | |
bit | try_get(T value) | |
void | do_copy(uvm_object rhs) | |
void | do_pack(uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
string | convert2string() | |
void | do_print(uvm_printer printer) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
string | get_type_name() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() |
| Type | Method | Description |
|---|---|---|
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) |
| Type | Method | Description |
|---|---|---|
void | get_next_item(T1 t) | |
void | try_next_item(T1 t) | |
void | item_done(T2 t) | |
void | wait_for_sequences() | |
bit | has_do_available() | |
void | get(T1 t) | |
void | peek(T1 t) | |
void | put(T2 t) | |
void | put_response(T2 t) | |
void | disable_auto_item_recording() | |
bit | is_auto_item_recording_enabled() |
Extends: uvm_component
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
void | build_phase(uvm_phase phase) | |
void | do_task_phase(uvm_phase phase) |
Extends: uvm_port_component_base
| Type | Name | Description |
|---|---|---|
PORT | m_port |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, PORT port) | |
string | get_type_name() | |
void | resolve_bindings() | |
PORT | get_port() | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
this_type | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, uvm_port_type_e port_type, int min_size, int max_size) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
string | get_type_name() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | put(T t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
bit | try_put(T t) | |
bit | can_put() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | put(T t) | |
bit | try_put(T t) | |
bit | can_put() | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | get(T t) | |
void | put(T1 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
bit | try_get(T t) | |
bit | can_get() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | get(T t) | |
bit | try_get(T t) | |
bit | can_get() | |
void | put(T1 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | peek(T t) | |
void | put(T1 t) | |
void | get(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | peek(T t) | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | get(T t) | |
void | peek(T t) | |
void | put(T1 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
bit | try_get(T t) | |
bit | can_get() | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | get(T t) | |
void | peek(T t) | |
bit | try_get(T t) | |
bit | can_get() | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
this_req_type | m_req_imp | |
this_rsp_type | m_rsp_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp) | |
string | get_type_name() | |
void | put(REQ t) | |
void | get(RSP t) | |
void | peek(RSP t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
this_req_type | m_req_imp | |
this_rsp_type | m_rsp_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp) | |
string | get_type_name() | |
bit | try_put(REQ t) | |
bit | can_put() | |
bit | try_get(RSP t) | |
bit | can_get() | |
bit | try_peek(RSP t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
this_req_type | m_req_imp | |
this_rsp_type | m_rsp_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp) | |
string | get_type_name() | |
void | put(REQ t) | |
bit | try_put(REQ t) | |
bit | can_put() | |
void | get(RSP t) | |
void | peek(RSP t) | |
bit | try_get(RSP t) | |
bit | can_get() | |
bit | try_peek(RSP t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
this_req_type | m_req_imp | |
this_rsp_type | m_rsp_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp) | |
string | get_type_name() | |
void | put(RSP t) | |
void | get(REQ t) | |
void | peek(REQ t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
this_req_type | m_req_imp | |
this_rsp_type | m_rsp_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp) | |
string | get_type_name() | |
bit | try_put(RSP t) | |
bit | can_put() | |
bit | try_get(REQ t) | |
bit | can_get() | |
bit | try_peek(REQ t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
this_req_type | m_req_imp | |
this_rsp_type | m_rsp_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp) | |
string | get_type_name() | |
void | put(RSP t) | |
bit | try_put(RSP t) | |
bit | can_put() | |
void | get(REQ t) | |
void | peek(REQ t) | |
bit | try_get(REQ t) | |
bit | can_get() | |
bit | try_peek(REQ t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | transport(REQ req, RSP rsp) | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
bit | nb_transport(REQ req, RSP rsp) | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | transport(REQ req, RSP rsp) | |
bit | nb_transport(REQ req, RSP rsp) | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(T t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_put(T t) | |
bit | can_put() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(T t) | |
bit | try_put(T t) | |
bit | can_put() | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | get(T t) | |
void | put(T1 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_get(T t) | |
bit | can_get() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | get(T t) | |
bit | try_get(T t) | |
bit | can_get() | |
void | put(T1 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | peek(T t) | |
void | put(T1 t) | |
void | get(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | peek(T t) | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | get(T t) | |
void | peek(T t) | |
void | put(T1 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_get(T t) | |
bit | can_get() | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | get(T t) | |
void | peek(T t) | |
bit | try_get(T t) | |
bit | can_get() | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(REQ t) | |
void | get(RSP t) | |
void | peek(RSP t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_put(REQ t) | |
bit | can_put() | |
bit | try_get(RSP t) | |
bit | can_get() | |
bit | try_peek(RSP t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(REQ t) | |
bit | try_put(REQ t) | |
bit | can_put() | |
void | get(RSP t) | |
void | peek(RSP t) | |
bit | try_get(RSP t) | |
bit | can_get() | |
bit | try_peek(RSP t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(RSP t) | |
void | get(REQ t) | |
void | peek(REQ t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_put(RSP t) | |
bit | can_put() | |
bit | try_get(REQ t) | |
bit | can_get() | |
bit | try_peek(REQ t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(RSP t) | |
bit | try_put(RSP t) | |
bit | can_put() | |
void | get(REQ t) | |
void | peek(REQ t) | |
bit | try_get(REQ t) | |
bit | can_get() | |
bit | try_peek(REQ t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | transport(REQ req, RSP rsp) | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | nb_transport(REQ req, RSP rsp) | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | transport(REQ req, RSP rsp) | |
bit | nb_transport(REQ req, RSP rsp) | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(T t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_put(T t) | |
bit | can_put() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(T t) | |
bit | try_put(T t) | |
bit | can_put() | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | get(T t) | |
void | put(T1 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_get(T t) | |
bit | can_get() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | get(T t) | |
bit | try_get(T t) | |
bit | can_get() | |
void | put(T1 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | peek(T t) | |
void | put(T1 t) | |
void | get(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | peek(T t) | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | get(T t) | |
void | peek(T t) | |
void | put(T1 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_get(T t) | |
bit | can_get() | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | get(T t) | |
void | peek(T t) | |
bit | try_get(T t) | |
bit | can_get() | |
bit | try_peek(T t) | |
bit | can_peek() | |
void | put(T1 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(REQ t) | |
void | get(RSP t) | |
void | peek(RSP t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_put(REQ t) | |
bit | can_put() | |
bit | try_get(RSP t) | |
bit | can_get() | |
bit | try_peek(RSP t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(REQ t) | |
bit | try_put(REQ t) | |
bit | can_put() | |
void | get(RSP t) | |
void | peek(RSP t) | |
bit | try_get(RSP t) | |
bit | can_get() | |
bit | try_peek(RSP t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(RSP t) | |
void | get(REQ t) | |
void | peek(REQ t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | try_put(RSP t) | |
bit | can_put() | |
bit | try_get(REQ t) | |
bit | can_get() | |
bit | try_peek(REQ t) | |
bit | can_peek() | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | put(RSP t) | |
bit | try_put(RSP t) | |
bit | can_put() | |
void | get(REQ t) | |
void | peek(REQ t) | |
bit | try_get(REQ t) | |
bit | can_get() | |
bit | try_peek(REQ t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | transport(REQ req, RSP rsp) | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
bit | nb_transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
bit | nb_transport(REQ req, RSP rsp) | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | transport(REQ req, RSP rsp) | |
bit | nb_transport(REQ req, RSP rsp) | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | write(T1 t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
string | get_type_name() | |
void | write(T t) | Method: write Send specified value to all connected interface |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | write(T t) | |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | Function: new Instantiate the export. |
string | get_type_name() | |
void | write(T t) | analysis port differs from other ports in that it broadcasts to all connected interfaces. Ports only send to the interface at the index specified in a call to set_if (0 by default). |
void | put(T1 t) | |
void | get(T2 t) | |
void | peek(T2 t) | |
bit | try_put(T1 t) | |
bit | can_put() | |
bit | try_get(T2 t) | |
bit | can_get() | |
bit | try_peek(T2 t) | |
bit | can_peek() | |
void | transport(T1 req, T2 rsp) | |
bit | nb_transport(T1 req, T2 rsp) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
event | trigger |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
uvm_put_imp | put_export | |
uvm_get_peek_imp | get_peek_export | |
uvm_analysis_port | put_ap | |
uvm_analysis_port | get_ap | |
uvm_put_imp | blocking_put_export | |
uvm_put_imp | nonblocking_put_export | |
uvm_get_peek_imp | blocking_get_export | |
uvm_get_peek_imp | nonblocking_get_export | |
uvm_get_peek_imp | get_export | |
uvm_get_peek_imp | blocking_peek_export | |
uvm_get_peek_imp | nonblocking_peek_export | |
uvm_get_peek_imp | peek_export | |
uvm_get_peek_imp | blocking_get_peek_export | |
uvm_get_peek_imp | nonblocking_get_peek_export |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | build_phase(uvm_phase phase) | turn off auto config |
void | flush() | |
int | size() | |
void | put(T t) | |
void | get(T t) | |
void | peek(T t) | |
bit | try_put(T t) | |
bit | try_get(T t) | |
bit | try_peek(T t) | |
bit | can_put() | |
bit | can_get() | |
bit | can_peek() | |
uvm_tlm_event | ok_to_put() | |
uvm_tlm_event | ok_to_get() | |
uvm_tlm_event | ok_to_peek() | |
bit | is_empty() | |
bit | is_full() | |
int | used() |
| Type | Name | Description |
|---|---|---|
string | type_name | |
anonymous | m | |
int | m_size | |
int | m_pending_blocked_gets | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_report_handler | m_rh | |
int | enable_stop_interrupt | |
bit | m_config_deprecated_warned | |
bit | m_config_set | |
bit | print_config_matches | |
bit | print_enabled | |
uvm_tr_database | tr_database | Variable: tr_database Specifies the <uvm_tr_database> object to use for <begin_tr>
and other methods in the . |
uvm_domain | m_domain | set_domain stores our domain handle |
uvm_phase[] | m_phase_imps | functors to override ovm_root defaults |
uvm_phase | m_current_phase | the most recently executed phase |
unknown | m_phase_process | |
bit | m_build_done | |
int | m_phasing_active | |
uvm_component | m_parent | |
uvm_component[] | m_children | |
uvm_component[] | m_children_by_handle | |
uvm_tr_stream | m_main_stream | |
unknown[] | m_streams | |
uvm_recorder[] | m_tr_h | |
string | m_name | |
uvm_event_pool | event_pool | |
int | recording_detail | |
m_verbosity_setting[] | m_verbosity_settings | |
m_verbosity_setting[] | m_time_settings | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_action | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_sev | |
uvm_put_imp | put_export | |
uvm_get_peek_imp | get_peek_export | |
uvm_analysis_port | put_ap | |
uvm_analysis_port | get_ap | |
uvm_put_imp | blocking_put_export | |
uvm_put_imp | nonblocking_put_export | |
uvm_get_peek_imp | blocking_get_export | |
uvm_get_peek_imp | nonblocking_get_export | |
uvm_get_peek_imp | get_export | |
uvm_get_peek_imp | blocking_peek_export | |
uvm_get_peek_imp | nonblocking_peek_export | |
uvm_get_peek_imp | peek_export | |
uvm_get_peek_imp | blocking_get_peek_export | |
uvm_get_peek_imp | nonblocking_get_peek_export |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int size) | |
string | get_type_name() | |
int | size() | |
int | used() | |
bit | is_empty() | |
bit | is_full() | |
void | put(T t) | |
void | get(T t) | |
void | peek(T t) | |
bit | try_get(T t) | |
bit | try_peek(T t) | |
bit | try_put(T t) | |
bit | can_put() | |
bit | can_get() | |
bit | can_peek() | |
void | flush() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
int | get_report_verbosity_level(uvm_severity severity, string id) | |
int | get_report_max_verbosity_level() | |
void | set_report_verbosity_level(int verbosity_level) | |
void | set_report_id_verbosity(string id, int verbosity) | Function: set_report_id_verbosity |
void | set_report_severity_id_verbosity(uvm_severity severity, string id, int verbosity) | |
int | get_report_action(uvm_severity severity, string id) | |
void | set_report_severity_action(uvm_severity severity, uvm_action action) | Function: set_report_severity_action |
void | set_report_id_action(string id, uvm_action action) | Function: set_report_id_action |
void | set_report_severity_id_action(uvm_severity severity, string id, uvm_action action) | |
int | get_report_file_handle(uvm_severity severity, string id) | |
void | set_report_default_file(UVM_FILE file) | |
void | set_report_id_file(string id, UVM_FILE file) | |
void | set_report_severity_file(uvm_severity severity, UVM_FILE file) | Function: set_report_severity_file |
void | set_report_severity_id_file(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity) | Function: set_report_severity_override |
void | set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity) | Function: set_report_severity_id_override These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~. |
void | set_report_handler(uvm_report_handler handler) | |
uvm_report_handler | get_report_handler() | |
void | reset_report_handler() | |
bit | report_info_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_error_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_warning_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_fatal_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_hook(string id, string message, int verbosity, string filename, int line) | |
void | report_header(UVM_FILE file) | |
void | report_summarize(UVM_FILE file) | |
void | die() | |
void | set_report_max_quit_count(int max_count) | |
uvm_report_server | get_report_server() | |
void | dump_report_state() | |
uvm_component | get_parent() | |
void | get_children(uvm_component[] children) | |
uvm_component | get_child(string name) | |
int | get_next_child(string name) | |
int | get_first_child(string name) | |
int | get_num_children() | |
int | has_child(string name) | |
uvm_component | lookup(string name) | |
int | get_depth() | |
void | build_phase(uvm_phase phase) | turn off auto config |
void | build() | |
void | connect_phase(uvm_phase phase) | |
void | connect() | |
void | end_of_elaboration_phase(uvm_phase phase) | |
void | end_of_elaboration() | |
void | start_of_simulation_phase(uvm_phase phase) | |
void | start_of_simulation() | |
void | run_phase(uvm_phase phase) | |
void | run() | |
void | pre_reset_phase(uvm_phase phase) | |
void | reset_phase(uvm_phase phase) | |
void | post_reset_phase(uvm_phase phase) | |
void | pre_configure_phase(uvm_phase phase) | |
void | configure_phase(uvm_phase phase) | |
void | post_configure_phase(uvm_phase phase) | |
void | pre_main_phase(uvm_phase phase) | |
void | main_phase(uvm_phase phase) | |
void | post_main_phase(uvm_phase phase) | |
void | pre_shutdown_phase(uvm_phase phase) | |
void | shutdown_phase(uvm_phase phase) | |
void | post_shutdown_phase(uvm_phase phase) | |
void | extract_phase(uvm_phase phase) | |
void | extract() | |
void | check_phase(uvm_phase phase) | |
void | check() | |
void | report_phase(uvm_phase phase) | |
void | report() | |
void | final_phase(uvm_phase phase) | |
void | phase_started(uvm_phase phase) | |
void | phase_ready_to_end(uvm_phase phase) | |
void | phase_ended(uvm_phase phase) | |
void | set_domain(uvm_domain domain, int hier) | |
uvm_domain | get_domain() | |
void | define_domain(uvm_domain domain) | |
void | set_phase_imp(uvm_phase phase, uvm_phase imp, int hier) | |
void | suspend() | |
void | resume() | |
string | status() | |
void | kill() | |
void | do_kill_all() | |
void | stop_phase(uvm_phase phase) | |
void | stop(string ph_name) | |
void | resolve_bindings() | |
string | massage_scope(string scope) | |
void | set_config_int(string inst_name, string field_name, uvm_bitstream_t value) | |
void | set_config_string(string inst_name, string field_name, string value) | |
void | set_config_object(string inst_name, string field_name, uvm_object value, bit clone) | |
bit | get_config_int(string field_name, uvm_bitstream_t value) | |
bit | get_config_string(string field_name, string value) | |
bit | get_config_object(string field_name, uvm_object value, bit clone) | |
void | check_config_usage(bit recurse) | |
void | apply_config_settings(bit verbose) | |
void | print_config_settings(string field, uvm_component comp, bit recurse) | |
void | print_config(bit recurse, bit audit) | |
void | print_config_with_audit(bit recurse) | |
void | raised(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
uvm_component | create_component(string requested_type_name, string name) | |
uvm_object | create_object(string requested_type_name, string name) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type) | |
void | set_type_override(string original_type_name, string override_type_name, bit replace) | |
void | set_inst_override(string relative_inst_path, string original_type_name, string override_type_name) | |
void | print_override_info(string requested_type_name, string name) | |
void | set_report_id_verbosity_hier(string id, int verbosity) | |
void | set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity) | |
void | set_report_severity_action_hier(uvm_severity severity, uvm_action action) | |
void | set_report_id_action_hier(string id, uvm_action action) | |
void | set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action) | |
void | set_report_default_file_hier(UVM_FILE file) | |
void | set_report_severity_file_hier(uvm_severity severity, UVM_FILE file) | |
void | set_report_id_file_hier(string id, UVM_FILE file) | |
void | set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_verbosity_level_hier(int verbosity) | |
void | pre_abort() | |
void | accept_tr(uvm_transaction tr, time accept_time) | |
void | do_accept_tr(uvm_transaction tr) | |
integer | begin_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle) | |
integer | begin_child_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | do_begin_tr(uvm_transaction tr, string stream_name, integer tr_handle) | |
void | end_tr(uvm_transaction tr, time end_time, bit free_handle) | |
void | do_end_tr(uvm_transaction tr, integer tr_handle) | |
integer | record_error_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active) | |
integer | record_event_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active) | |
uvm_tr_stream | get_tr_stream(string name, string stream_type_name) | |
void | free_tr_stream(uvm_tr_stream stream) | |
uvm_tr_database | m_get_tr_database() | |
bit | m_add_child(uvm_component child) | |
void | m_set_full_name() | |
void | do_resolve_bindings() | |
void | do_flush() | |
void | m_extract_name(string name, string leaf, string remainder) | |
integer | m_begin_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | m_set_cl_msg_args() | |
void | m_set_cl_verb() | |
void | m_set_cl_action() | |
void | m_set_cl_sev() | |
void | m_apply_verbosity_settings(uvm_phase phase) | |
void | m_do_pre_abort() | |
uvm_tlm_event | ok_to_put() | |
uvm_tlm_event | ok_to_get() | |
uvm_tlm_event | ok_to_peek() |
| Type | Name | Description |
|---|---|---|
uvm_analysis_imp | analysis_export | |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_report_handler | m_rh | |
int | enable_stop_interrupt | |
bit | m_config_deprecated_warned | |
bit | m_config_set | |
bit | print_config_matches | |
bit | print_enabled | |
uvm_tr_database | tr_database | Variable: tr_database Specifies the <uvm_tr_database> object to use for <begin_tr>
and other methods in the . |
uvm_domain | m_domain | set_domain stores our domain handle |
uvm_phase[] | m_phase_imps | functors to override ovm_root defaults |
uvm_phase | m_current_phase | the most recently executed phase |
unknown | m_phase_process | |
bit | m_build_done | |
int | m_phasing_active | |
uvm_component | m_parent | |
uvm_component[] | m_children | |
uvm_component[] | m_children_by_handle | |
uvm_tr_stream | m_main_stream | |
unknown[] | m_streams | |
uvm_recorder[] | m_tr_h | |
string | m_name | |
uvm_event_pool | event_pool | |
int | recording_detail | |
m_verbosity_setting[] | m_verbosity_settings | |
m_verbosity_setting[] | m_time_settings | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_action | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_sev | |
uvm_put_imp | put_export | |
uvm_get_peek_imp | get_peek_export | |
uvm_analysis_port | put_ap | |
uvm_analysis_port | get_ap | |
uvm_put_imp | blocking_put_export | |
uvm_put_imp | nonblocking_put_export | |
uvm_get_peek_imp | blocking_get_export | |
uvm_get_peek_imp | nonblocking_get_export | |
uvm_get_peek_imp | get_export | |
uvm_get_peek_imp | blocking_peek_export | |
uvm_get_peek_imp | nonblocking_peek_export | |
uvm_get_peek_imp | peek_export | |
uvm_get_peek_imp | blocking_get_peek_export | |
uvm_get_peek_imp | nonblocking_get_peek_export | |
anonymous | m | |
int | m_size | |
int | m_pending_blocked_gets |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
string | get_type_name() | |
void | write(T t) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
int | get_report_verbosity_level(uvm_severity severity, string id) | |
int | get_report_max_verbosity_level() | |
void | set_report_verbosity_level(int verbosity_level) | |
void | set_report_id_verbosity(string id, int verbosity) | Function: set_report_id_verbosity |
void | set_report_severity_id_verbosity(uvm_severity severity, string id, int verbosity) | |
int | get_report_action(uvm_severity severity, string id) | |
void | set_report_severity_action(uvm_severity severity, uvm_action action) | Function: set_report_severity_action |
void | set_report_id_action(string id, uvm_action action) | Function: set_report_id_action |
void | set_report_severity_id_action(uvm_severity severity, string id, uvm_action action) | |
int | get_report_file_handle(uvm_severity severity, string id) | |
void | set_report_default_file(UVM_FILE file) | |
void | set_report_id_file(string id, UVM_FILE file) | |
void | set_report_severity_file(uvm_severity severity, UVM_FILE file) | Function: set_report_severity_file |
void | set_report_severity_id_file(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity) | Function: set_report_severity_override |
void | set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity) | Function: set_report_severity_id_override These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~. |
void | set_report_handler(uvm_report_handler handler) | |
uvm_report_handler | get_report_handler() | |
void | reset_report_handler() | |
bit | report_info_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_error_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_warning_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_fatal_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_hook(string id, string message, int verbosity, string filename, int line) | |
void | report_header(UVM_FILE file) | |
void | report_summarize(UVM_FILE file) | |
void | die() | |
void | set_report_max_quit_count(int max_count) | |
uvm_report_server | get_report_server() | |
void | dump_report_state() | |
uvm_component | get_parent() | |
void | get_children(uvm_component[] children) | |
uvm_component | get_child(string name) | |
int | get_next_child(string name) | |
int | get_first_child(string name) | |
int | get_num_children() | |
int | has_child(string name) | |
uvm_component | lookup(string name) | |
int | get_depth() | |
void | build_phase(uvm_phase phase) | turn off auto config |
void | build() | |
void | connect_phase(uvm_phase phase) | |
void | connect() | |
void | end_of_elaboration_phase(uvm_phase phase) | |
void | end_of_elaboration() | |
void | start_of_simulation_phase(uvm_phase phase) | |
void | start_of_simulation() | |
void | run_phase(uvm_phase phase) | |
void | run() | |
void | pre_reset_phase(uvm_phase phase) | |
void | reset_phase(uvm_phase phase) | |
void | post_reset_phase(uvm_phase phase) | |
void | pre_configure_phase(uvm_phase phase) | |
void | configure_phase(uvm_phase phase) | |
void | post_configure_phase(uvm_phase phase) | |
void | pre_main_phase(uvm_phase phase) | |
void | main_phase(uvm_phase phase) | |
void | post_main_phase(uvm_phase phase) | |
void | pre_shutdown_phase(uvm_phase phase) | |
void | shutdown_phase(uvm_phase phase) | |
void | post_shutdown_phase(uvm_phase phase) | |
void | extract_phase(uvm_phase phase) | |
void | extract() | |
void | check_phase(uvm_phase phase) | |
void | check() | |
void | report_phase(uvm_phase phase) | |
void | report() | |
void | final_phase(uvm_phase phase) | |
void | phase_started(uvm_phase phase) | |
void | phase_ready_to_end(uvm_phase phase) | |
void | phase_ended(uvm_phase phase) | |
void | set_domain(uvm_domain domain, int hier) | |
uvm_domain | get_domain() | |
void | define_domain(uvm_domain domain) | |
void | set_phase_imp(uvm_phase phase, uvm_phase imp, int hier) | |
void | suspend() | |
void | resume() | |
string | status() | |
void | kill() | |
void | do_kill_all() | |
void | stop_phase(uvm_phase phase) | |
void | stop(string ph_name) | |
void | resolve_bindings() | |
string | massage_scope(string scope) | |
void | set_config_int(string inst_name, string field_name, uvm_bitstream_t value) | |
void | set_config_string(string inst_name, string field_name, string value) | |
void | set_config_object(string inst_name, string field_name, uvm_object value, bit clone) | |
bit | get_config_int(string field_name, uvm_bitstream_t value) | |
bit | get_config_string(string field_name, string value) | |
bit | get_config_object(string field_name, uvm_object value, bit clone) | |
void | check_config_usage(bit recurse) | |
void | apply_config_settings(bit verbose) | |
void | print_config_settings(string field, uvm_component comp, bit recurse) | |
void | print_config(bit recurse, bit audit) | |
void | print_config_with_audit(bit recurse) | |
void | raised(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
uvm_component | create_component(string requested_type_name, string name) | |
uvm_object | create_object(string requested_type_name, string name) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type) | |
void | set_type_override(string original_type_name, string override_type_name, bit replace) | |
void | set_inst_override(string relative_inst_path, string original_type_name, string override_type_name) | |
void | print_override_info(string requested_type_name, string name) | |
void | set_report_id_verbosity_hier(string id, int verbosity) | |
void | set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity) | |
void | set_report_severity_action_hier(uvm_severity severity, uvm_action action) | |
void | set_report_id_action_hier(string id, uvm_action action) | |
void | set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action) | |
void | set_report_default_file_hier(UVM_FILE file) | |
void | set_report_severity_file_hier(uvm_severity severity, UVM_FILE file) | |
void | set_report_id_file_hier(string id, UVM_FILE file) | |
void | set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_verbosity_level_hier(int verbosity) | |
void | pre_abort() | |
void | accept_tr(uvm_transaction tr, time accept_time) | |
void | do_accept_tr(uvm_transaction tr) | |
integer | begin_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle) | |
integer | begin_child_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | do_begin_tr(uvm_transaction tr, string stream_name, integer tr_handle) | |
void | end_tr(uvm_transaction tr, time end_time, bit free_handle) | |
void | do_end_tr(uvm_transaction tr, integer tr_handle) | |
integer | record_error_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active) | |
integer | record_event_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active) | |
uvm_tr_stream | get_tr_stream(string name, string stream_type_name) | |
void | free_tr_stream(uvm_tr_stream stream) | |
uvm_tr_database | m_get_tr_database() | |
bit | m_add_child(uvm_component child) | |
void | m_set_full_name() | |
void | do_resolve_bindings() | |
void | do_flush() | |
void | flush() | |
void | m_extract_name(string name, string leaf, string remainder) | |
integer | m_begin_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | m_set_cl_msg_args() | |
void | m_set_cl_verb() | |
void | m_set_cl_action() | |
void | m_set_cl_sev() | |
void | m_apply_verbosity_settings(uvm_phase phase) | |
void | m_do_pre_abort() | |
int | size() | |
void | put(T t) | |
void | get(T t) | |
void | peek(T t) | |
bit | try_put(T t) | |
bit | try_get(T t) | |
bit | try_peek(T t) | |
bit | can_put() | |
bit | can_get() | |
bit | can_peek() | |
uvm_tlm_event | ok_to_put() | |
uvm_tlm_event | ok_to_get() | |
uvm_tlm_event | ok_to_peek() | |
bit | is_empty() | |
bit | is_full() | |
int | used() |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_put_export | put_request_export | |
uvm_get_peek_export | get_peek_response_export | |
uvm_get_peek_export | get_peek_request_export | |
uvm_put_export | put_response_export | |
uvm_analysis_port | request_ap | |
uvm_analysis_port | response_ap | |
uvm_master_imp | master_export | |
uvm_slave_imp | slave_export | |
uvm_put_export | blocking_put_request_export | port aliases for backward compatibility |
uvm_put_export | nonblocking_put_request_export | port aliases for backward compatibility |
uvm_get_peek_export | get_request_export | |
uvm_get_peek_export | blocking_get_request_export | |
uvm_get_peek_export | nonblocking_get_request_export | |
uvm_get_peek_export | peek_request_export | |
uvm_get_peek_export | blocking_peek_request_export | |
uvm_get_peek_export | nonblocking_peek_request_export | |
uvm_get_peek_export | blocking_get_peek_request_export | |
uvm_get_peek_export | nonblocking_get_peek_request_export | |
uvm_put_export | blocking_put_response_export | |
uvm_put_export | nonblocking_put_response_export | |
uvm_get_peek_export | get_response_export | |
uvm_get_peek_export | blocking_get_response_export | |
uvm_get_peek_export | nonblocking_get_response_export | |
uvm_get_peek_export | peek_response_export | |
uvm_get_peek_export | blocking_peek_response_export | |
uvm_get_peek_export | nonblocking_peek_response_export | |
uvm_get_peek_export | blocking_get_peek_response_export | |
uvm_get_peek_export | nonblocking_get_peek_response_export | |
uvm_master_imp | blocking_master_export | |
uvm_master_imp | nonblocking_master_export | |
uvm_slave_imp | blocking_slave_export | |
uvm_slave_imp | nonblocking_slave_export | |
uvm_tlm_fifo | m_request_fifo | |
uvm_tlm_fifo | m_response_fifo |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int request_fifo_size, int response_fifo_size) | |
void | connect_phase(uvm_phase phase) | |
void | create_aliased_exports() | |
string | get_type_name() | |
uvm_object | create(string name) |
| Type | Name | Description |
|---|---|---|
uvm_transport_imp | transport_export | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_report_handler | m_rh | |
int | enable_stop_interrupt | |
bit | m_config_deprecated_warned | |
bit | m_config_set | |
bit | print_config_matches | |
bit | print_enabled | |
uvm_tr_database | tr_database | Variable: tr_database Specifies the <uvm_tr_database> object to use for <begin_tr>
and other methods in the . |
uvm_domain | m_domain | set_domain stores our domain handle |
uvm_phase[] | m_phase_imps | functors to override ovm_root defaults |
uvm_phase | m_current_phase | the most recently executed phase |
unknown | m_phase_process | |
bit | m_build_done | |
int | m_phasing_active | |
uvm_component | m_parent | |
uvm_component[] | m_children | |
uvm_component[] | m_children_by_handle | |
uvm_tr_stream | m_main_stream | |
unknown[] | m_streams | |
uvm_recorder[] | m_tr_h | |
string | m_name | |
string | type_name | |
uvm_event_pool | event_pool | |
int | recording_detail | |
m_verbosity_setting[] | m_verbosity_settings | |
m_verbosity_setting[] | m_time_settings | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_action | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_sev | |
uvm_put_export | put_request_export | |
uvm_get_peek_export | get_peek_response_export | |
uvm_get_peek_export | get_peek_request_export | |
uvm_put_export | put_response_export | |
uvm_analysis_port | request_ap | |
uvm_analysis_port | response_ap | |
uvm_master_imp | master_export | |
uvm_slave_imp | slave_export | |
uvm_put_export | blocking_put_request_export | port aliases for backward compatibility |
uvm_put_export | nonblocking_put_request_export | port aliases for backward compatibility |
uvm_get_peek_export | get_request_export | |
uvm_get_peek_export | blocking_get_request_export | |
uvm_get_peek_export | nonblocking_get_request_export | |
uvm_get_peek_export | peek_request_export | |
uvm_get_peek_export | blocking_peek_request_export | |
uvm_get_peek_export | nonblocking_peek_request_export | |
uvm_get_peek_export | blocking_get_peek_request_export | |
uvm_get_peek_export | nonblocking_get_peek_request_export | |
uvm_put_export | blocking_put_response_export | |
uvm_put_export | nonblocking_put_response_export | |
uvm_get_peek_export | get_response_export | |
uvm_get_peek_export | blocking_get_response_export | |
uvm_get_peek_export | nonblocking_get_response_export | |
uvm_get_peek_export | peek_response_export | |
uvm_get_peek_export | blocking_peek_response_export | |
uvm_get_peek_export | nonblocking_peek_response_export | |
uvm_get_peek_export | blocking_get_peek_response_export | |
uvm_get_peek_export | nonblocking_get_peek_response_export | |
uvm_master_imp | blocking_master_export | |
uvm_master_imp | nonblocking_master_export | |
uvm_slave_imp | blocking_slave_export | |
uvm_slave_imp | nonblocking_slave_export | |
uvm_tlm_fifo | m_request_fifo | |
uvm_tlm_fifo | m_response_fifo |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | transport(REQ request, RSP response) | |
bit | nb_transport(REQ req, RSP rsp) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
int | get_report_verbosity_level(uvm_severity severity, string id) | |
int | get_report_max_verbosity_level() | |
void | set_report_verbosity_level(int verbosity_level) | |
void | set_report_id_verbosity(string id, int verbosity) | Function: set_report_id_verbosity |
void | set_report_severity_id_verbosity(uvm_severity severity, string id, int verbosity) | |
int | get_report_action(uvm_severity severity, string id) | |
void | set_report_severity_action(uvm_severity severity, uvm_action action) | Function: set_report_severity_action |
void | set_report_id_action(string id, uvm_action action) | Function: set_report_id_action |
void | set_report_severity_id_action(uvm_severity severity, string id, uvm_action action) | |
int | get_report_file_handle(uvm_severity severity, string id) | |
void | set_report_default_file(UVM_FILE file) | |
void | set_report_id_file(string id, UVM_FILE file) | |
void | set_report_severity_file(uvm_severity severity, UVM_FILE file) | Function: set_report_severity_file |
void | set_report_severity_id_file(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity) | Function: set_report_severity_override |
void | set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity) | Function: set_report_severity_id_override These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~. |
void | set_report_handler(uvm_report_handler handler) | |
uvm_report_handler | get_report_handler() | |
void | reset_report_handler() | |
bit | report_info_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_error_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_warning_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_fatal_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_hook(string id, string message, int verbosity, string filename, int line) | |
void | report_header(UVM_FILE file) | |
void | report_summarize(UVM_FILE file) | |
void | die() | |
void | set_report_max_quit_count(int max_count) | |
uvm_report_server | get_report_server() | |
void | dump_report_state() | |
uvm_component | get_parent() | |
void | get_children(uvm_component[] children) | |
uvm_component | get_child(string name) | |
int | get_next_child(string name) | |
int | get_first_child(string name) | |
int | get_num_children() | |
int | has_child(string name) | |
uvm_component | lookup(string name) | |
int | get_depth() | |
void | build_phase(uvm_phase phase) | |
void | build() | |
void | connect_phase(uvm_phase phase) | |
void | connect() | |
void | end_of_elaboration_phase(uvm_phase phase) | |
void | end_of_elaboration() | |
void | start_of_simulation_phase(uvm_phase phase) | |
void | start_of_simulation() | |
void | run_phase(uvm_phase phase) | |
void | run() | |
void | pre_reset_phase(uvm_phase phase) | |
void | reset_phase(uvm_phase phase) | |
void | post_reset_phase(uvm_phase phase) | |
void | pre_configure_phase(uvm_phase phase) | |
void | configure_phase(uvm_phase phase) | |
void | post_configure_phase(uvm_phase phase) | |
void | pre_main_phase(uvm_phase phase) | |
void | main_phase(uvm_phase phase) | |
void | post_main_phase(uvm_phase phase) | |
void | pre_shutdown_phase(uvm_phase phase) | |
void | shutdown_phase(uvm_phase phase) | |
void | post_shutdown_phase(uvm_phase phase) | |
void | extract_phase(uvm_phase phase) | |
void | extract() | |
void | check_phase(uvm_phase phase) | |
void | check() | |
void | report_phase(uvm_phase phase) | |
void | report() | |
void | final_phase(uvm_phase phase) | |
void | phase_started(uvm_phase phase) | |
void | phase_ready_to_end(uvm_phase phase) | |
void | phase_ended(uvm_phase phase) | |
void | set_domain(uvm_domain domain, int hier) | |
uvm_domain | get_domain() | |
void | define_domain(uvm_domain domain) | |
void | set_phase_imp(uvm_phase phase, uvm_phase imp, int hier) | |
void | suspend() | |
void | resume() | |
string | status() | |
void | kill() | |
void | do_kill_all() | |
void | stop_phase(uvm_phase phase) | |
void | stop(string ph_name) | |
void | resolve_bindings() | |
string | massage_scope(string scope) | |
void | set_config_int(string inst_name, string field_name, uvm_bitstream_t value) | |
void | set_config_string(string inst_name, string field_name, string value) | |
void | set_config_object(string inst_name, string field_name, uvm_object value, bit clone) | |
bit | get_config_int(string field_name, uvm_bitstream_t value) | |
bit | get_config_string(string field_name, string value) | |
bit | get_config_object(string field_name, uvm_object value, bit clone) | |
void | check_config_usage(bit recurse) | |
void | apply_config_settings(bit verbose) | |
void | print_config_settings(string field, uvm_component comp, bit recurse) | |
void | print_config(bit recurse, bit audit) | |
void | print_config_with_audit(bit recurse) | |
void | raised(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
uvm_component | create_component(string requested_type_name, string name) | |
uvm_object | create_object(string requested_type_name, string name) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type) | |
void | set_type_override(string original_type_name, string override_type_name, bit replace) | |
void | set_inst_override(string relative_inst_path, string original_type_name, string override_type_name) | |
void | print_override_info(string requested_type_name, string name) | |
void | set_report_id_verbosity_hier(string id, int verbosity) | |
void | set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity) | |
void | set_report_severity_action_hier(uvm_severity severity, uvm_action action) | |
void | set_report_id_action_hier(string id, uvm_action action) | |
void | set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action) | |
void | set_report_default_file_hier(UVM_FILE file) | |
void | set_report_severity_file_hier(uvm_severity severity, UVM_FILE file) | |
void | set_report_id_file_hier(string id, UVM_FILE file) | |
void | set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_verbosity_level_hier(int verbosity) | |
void | pre_abort() | |
void | accept_tr(uvm_transaction tr, time accept_time) | |
void | do_accept_tr(uvm_transaction tr) | |
integer | begin_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle) | |
integer | begin_child_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | do_begin_tr(uvm_transaction tr, string stream_name, integer tr_handle) | |
void | end_tr(uvm_transaction tr, time end_time, bit free_handle) | |
void | do_end_tr(uvm_transaction tr, integer tr_handle) | |
integer | record_error_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active) | |
integer | record_event_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active) | |
uvm_tr_stream | get_tr_stream(string name, string stream_type_name) | |
void | free_tr_stream(uvm_tr_stream stream) | |
uvm_tr_database | m_get_tr_database() | |
bit | m_add_child(uvm_component child) | |
void | m_set_full_name() | |
void | do_resolve_bindings() | |
void | do_flush() | |
void | flush() | |
void | m_extract_name(string name, string leaf, string remainder) | |
integer | m_begin_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | m_set_cl_msg_args() | |
void | m_set_cl_verb() | |
void | m_set_cl_action() | |
void | m_set_cl_sev() | |
void | m_apply_verbosity_settings(uvm_phase phase) | |
void | m_do_pre_abort() | |
void | create_aliased_exports() |
| Type | Name | Description |
|---|---|---|
bit | print_enabled | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | disable_auto_item_recording() | |
bit | is_auto_item_recording_enabled() | |
void | get_next_item(REQ t) | |
void | try_next_item(REQ t) | |
void | item_done(RSP t) | |
void | wait_for_sequences() | |
bit | has_do_available() | |
void | put_response(RSP t) | |
void | get(REQ t) | |
void | peek(REQ t) | |
void | put(RSP t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | disable_auto_item_recording() | |
bit | is_auto_item_recording_enabled() | |
void | get_next_item(REQ t) | |
void | try_next_item(REQ t) | |
void | item_done(RSP t) | |
void | wait_for_sequences() | |
bit | has_do_available() | |
void | put_response(RSP t) | |
void | get(REQ t) | |
void | peek(REQ t) | |
void | put(RSP t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | disable_auto_item_recording() | |
bit | is_auto_item_recording_enabled() | |
void | get_next_item(REQ t) | |
void | try_next_item(REQ t) | |
void | item_done(RSP t) | |
void | wait_for_sequences() | |
bit | has_do_available() | |
void | put_response(RSP t) | |
void | get(REQ t) | |
void | peek(REQ t) | |
void | put(RSP t) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | type_name | |
T1 | first | |
T2 | second |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name, T1 f, T2 s) | |
string | get_type_name() | |
string | convert2string() | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_copy(uvm_object rhs) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | type_name | |
T1 | first | |
T2 | second |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
string | get_type_name() | |
string | convert2string() | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_copy(uvm_object rhs) |
| Type | Method | Description |
|---|---|---|
bit | comp(T a, T b) |
| Type | Method | Description |
|---|---|---|
string | convert2string(T t) |
| Type | Method | Description |
|---|---|---|
T | clone(T from) |
| Type | Method | Description |
|---|---|---|
bit | comp(T a, T b) |
| Type | Method | Description |
|---|---|---|
string | convert2string(T t) |
| Type | Method | Description |
|---|---|---|
uvm_object | clone(T from) |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_analysis_export | before_export | |
uvm_analysis_export | after_export | |
uvm_analysis_port | pair_ap | |
uvm_tlm_analysis_fifo | m_before_fifo | |
uvm_tlm_analysis_fifo | m_after_fifo | |
int | m_matches | |
int | m_mismatches |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
logic | new(string name, uvm_component parent) | |
string | get_type_name() | |
void | connect_phase(uvm_phase phase) | |
void | run_phase(uvm_phase phase) | |
void | flush() |
| Type | Name | Description |
|---|---|---|
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_report_handler | m_rh | |
int | enable_stop_interrupt | |
bit | m_config_deprecated_warned | |
bit | m_config_set | |
bit | print_config_matches | |
bit | print_enabled | |
uvm_tr_database | tr_database | Variable: tr_database Specifies the <uvm_tr_database> object to use for <begin_tr>
and other methods in the . |
uvm_domain | m_domain | set_domain stores our domain handle |
uvm_phase[] | m_phase_imps | functors to override ovm_root defaults |
uvm_phase | m_current_phase | the most recently executed phase |
unknown | m_phase_process | |
bit | m_build_done | |
int | m_phasing_active | |
uvm_component | m_parent | |
uvm_component[] | m_children | |
uvm_component[] | m_children_by_handle | |
uvm_tr_stream | m_main_stream | |
unknown[] | m_streams | |
uvm_recorder[] | m_tr_h | |
string | m_name | |
uvm_event_pool | event_pool | |
int | recording_detail | |
m_verbosity_setting[] | m_verbosity_settings | |
m_verbosity_setting[] | m_time_settings | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_action | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_sev | |
uvm_analysis_export | before_export | |
uvm_analysis_export | after_export | |
uvm_analysis_port | pair_ap | |
uvm_tlm_analysis_fifo | m_before_fifo | |
uvm_tlm_analysis_fifo | m_after_fifo | |
int | m_matches | |
int | m_mismatches |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
logic | new(string name, uvm_component parent) | |
string | get_type_name() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
int | get_report_verbosity_level(uvm_severity severity, string id) | |
int | get_report_max_verbosity_level() | |
void | set_report_verbosity_level(int verbosity_level) | |
void | set_report_id_verbosity(string id, int verbosity) | Function: set_report_id_verbosity |
void | set_report_severity_id_verbosity(uvm_severity severity, string id, int verbosity) | |
int | get_report_action(uvm_severity severity, string id) | |
void | set_report_severity_action(uvm_severity severity, uvm_action action) | Function: set_report_severity_action |
void | set_report_id_action(string id, uvm_action action) | Function: set_report_id_action |
void | set_report_severity_id_action(uvm_severity severity, string id, uvm_action action) | |
int | get_report_file_handle(uvm_severity severity, string id) | |
void | set_report_default_file(UVM_FILE file) | |
void | set_report_id_file(string id, UVM_FILE file) | |
void | set_report_severity_file(uvm_severity severity, UVM_FILE file) | Function: set_report_severity_file |
void | set_report_severity_id_file(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity) | Function: set_report_severity_override |
void | set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity) | Function: set_report_severity_id_override These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~. |
void | set_report_handler(uvm_report_handler handler) | |
uvm_report_handler | get_report_handler() | |
void | reset_report_handler() | |
bit | report_info_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_error_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_warning_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_fatal_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_hook(string id, string message, int verbosity, string filename, int line) | |
void | report_header(UVM_FILE file) | |
void | report_summarize(UVM_FILE file) | |
void | die() | |
void | set_report_max_quit_count(int max_count) | |
uvm_report_server | get_report_server() | |
void | dump_report_state() | |
uvm_component | get_parent() | |
void | get_children(uvm_component[] children) | |
uvm_component | get_child(string name) | |
int | get_next_child(string name) | |
int | get_first_child(string name) | |
int | get_num_children() | |
int | has_child(string name) | |
uvm_component | lookup(string name) | |
int | get_depth() | |
void | build_phase(uvm_phase phase) | |
void | build() | |
void | connect_phase(uvm_phase phase) | |
void | connect() | |
void | end_of_elaboration_phase(uvm_phase phase) | |
void | end_of_elaboration() | |
void | start_of_simulation_phase(uvm_phase phase) | |
void | start_of_simulation() | |
void | run_phase(uvm_phase phase) | |
void | run() | |
void | pre_reset_phase(uvm_phase phase) | |
void | reset_phase(uvm_phase phase) | |
void | post_reset_phase(uvm_phase phase) | |
void | pre_configure_phase(uvm_phase phase) | |
void | configure_phase(uvm_phase phase) | |
void | post_configure_phase(uvm_phase phase) | |
void | pre_main_phase(uvm_phase phase) | |
void | main_phase(uvm_phase phase) | |
void | post_main_phase(uvm_phase phase) | |
void | pre_shutdown_phase(uvm_phase phase) | |
void | shutdown_phase(uvm_phase phase) | |
void | post_shutdown_phase(uvm_phase phase) | |
void | extract_phase(uvm_phase phase) | |
void | extract() | |
void | check_phase(uvm_phase phase) | |
void | check() | |
void | report_phase(uvm_phase phase) | |
void | report() | |
void | final_phase(uvm_phase phase) | |
void | phase_started(uvm_phase phase) | |
void | phase_ready_to_end(uvm_phase phase) | |
void | phase_ended(uvm_phase phase) | |
void | set_domain(uvm_domain domain, int hier) | |
uvm_domain | get_domain() | |
void | define_domain(uvm_domain domain) | |
void | set_phase_imp(uvm_phase phase, uvm_phase imp, int hier) | |
void | suspend() | |
void | resume() | |
string | status() | |
void | kill() | |
void | do_kill_all() | |
void | stop_phase(uvm_phase phase) | |
void | stop(string ph_name) | |
void | resolve_bindings() | |
string | massage_scope(string scope) | |
void | set_config_int(string inst_name, string field_name, uvm_bitstream_t value) | |
void | set_config_string(string inst_name, string field_name, string value) | |
void | set_config_object(string inst_name, string field_name, uvm_object value, bit clone) | |
bit | get_config_int(string field_name, uvm_bitstream_t value) | |
bit | get_config_string(string field_name, string value) | |
bit | get_config_object(string field_name, uvm_object value, bit clone) | |
void | check_config_usage(bit recurse) | |
void | apply_config_settings(bit verbose) | |
void | print_config_settings(string field, uvm_component comp, bit recurse) | |
void | print_config(bit recurse, bit audit) | |
void | print_config_with_audit(bit recurse) | |
void | raised(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
uvm_component | create_component(string requested_type_name, string name) | |
uvm_object | create_object(string requested_type_name, string name) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type) | |
void | set_type_override(string original_type_name, string override_type_name, bit replace) | |
void | set_inst_override(string relative_inst_path, string original_type_name, string override_type_name) | |
void | print_override_info(string requested_type_name, string name) | |
void | set_report_id_verbosity_hier(string id, int verbosity) | |
void | set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity) | |
void | set_report_severity_action_hier(uvm_severity severity, uvm_action action) | |
void | set_report_id_action_hier(string id, uvm_action action) | |
void | set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action) | |
void | set_report_default_file_hier(UVM_FILE file) | |
void | set_report_severity_file_hier(uvm_severity severity, UVM_FILE file) | |
void | set_report_id_file_hier(string id, UVM_FILE file) | |
void | set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_verbosity_level_hier(int verbosity) | |
void | pre_abort() | |
void | accept_tr(uvm_transaction tr, time accept_time) | |
void | do_accept_tr(uvm_transaction tr) | |
integer | begin_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle) | |
integer | begin_child_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | do_begin_tr(uvm_transaction tr, string stream_name, integer tr_handle) | |
void | end_tr(uvm_transaction tr, time end_time, bit free_handle) | |
void | do_end_tr(uvm_transaction tr, integer tr_handle) | |
integer | record_error_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active) | |
integer | record_event_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active) | |
uvm_tr_stream | get_tr_stream(string name, string stream_type_name) | |
void | free_tr_stream(uvm_tr_stream stream) | |
uvm_tr_database | m_get_tr_database() | |
bit | m_add_child(uvm_component child) | |
void | m_set_full_name() | |
void | do_resolve_bindings() | |
void | do_flush() | |
void | flush() | |
void | m_extract_name(string name, string leaf, string remainder) | |
integer | m_begin_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | m_set_cl_msg_args() | |
void | m_set_cl_verb() | |
void | m_set_cl_action() | |
void | m_set_cl_sev() | |
void | m_apply_verbosity_settings(uvm_phase phase) | |
void | m_do_pre_abort() |
| Type | Name | Description |
|---|---|---|
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_report_handler | m_rh | |
int | enable_stop_interrupt | |
bit | m_config_deprecated_warned | |
bit | m_config_set | |
bit | print_config_matches | |
bit | print_enabled | |
uvm_tr_database | tr_database | Variable: tr_database Specifies the <uvm_tr_database> object to use for <begin_tr>
and other methods in the . |
uvm_domain | m_domain | set_domain stores our domain handle |
uvm_phase[] | m_phase_imps | functors to override ovm_root defaults |
uvm_phase | m_current_phase | the most recently executed phase |
unknown | m_phase_process | |
bit | m_build_done | |
int | m_phasing_active | |
uvm_component | m_parent | |
uvm_component[] | m_children | |
uvm_component[] | m_children_by_handle | |
uvm_tr_stream | m_main_stream | |
unknown[] | m_streams | |
uvm_recorder[] | m_tr_h | |
string | m_name | |
uvm_event_pool | event_pool | |
int | recording_detail | |
m_verbosity_setting[] | m_verbosity_settings | |
m_verbosity_setting[] | m_time_settings | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_action | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_sev | |
uvm_analysis_export | before_export | |
uvm_analysis_export | after_export | |
uvm_analysis_port | pair_ap | |
uvm_tlm_analysis_fifo | m_before_fifo | |
uvm_tlm_analysis_fifo | m_after_fifo | |
int | m_matches | |
int | m_mismatches |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
logic | new(string name, uvm_component parent) | |
string | get_type_name() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
int | get_report_verbosity_level(uvm_severity severity, string id) | |
int | get_report_max_verbosity_level() | |
void | set_report_verbosity_level(int verbosity_level) | |
void | set_report_id_verbosity(string id, int verbosity) | Function: set_report_id_verbosity |
void | set_report_severity_id_verbosity(uvm_severity severity, string id, int verbosity) | |
int | get_report_action(uvm_severity severity, string id) | |
void | set_report_severity_action(uvm_severity severity, uvm_action action) | Function: set_report_severity_action |
void | set_report_id_action(string id, uvm_action action) | Function: set_report_id_action |
void | set_report_severity_id_action(uvm_severity severity, string id, uvm_action action) | |
int | get_report_file_handle(uvm_severity severity, string id) | |
void | set_report_default_file(UVM_FILE file) | |
void | set_report_id_file(string id, UVM_FILE file) | |
void | set_report_severity_file(uvm_severity severity, UVM_FILE file) | Function: set_report_severity_file |
void | set_report_severity_id_file(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity) | Function: set_report_severity_override |
void | set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity) | Function: set_report_severity_id_override These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~. |
void | set_report_handler(uvm_report_handler handler) | |
uvm_report_handler | get_report_handler() | |
void | reset_report_handler() | |
bit | report_info_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_error_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_warning_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_fatal_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_hook(string id, string message, int verbosity, string filename, int line) | |
void | report_header(UVM_FILE file) | |
void | report_summarize(UVM_FILE file) | |
void | die() | |
void | set_report_max_quit_count(int max_count) | |
uvm_report_server | get_report_server() | |
void | dump_report_state() | |
uvm_component | get_parent() | |
void | get_children(uvm_component[] children) | |
uvm_component | get_child(string name) | |
int | get_next_child(string name) | |
int | get_first_child(string name) | |
int | get_num_children() | |
int | has_child(string name) | |
uvm_component | lookup(string name) | |
int | get_depth() | |
void | build_phase(uvm_phase phase) | |
void | build() | |
void | connect_phase(uvm_phase phase) | |
void | connect() | |
void | end_of_elaboration_phase(uvm_phase phase) | |
void | end_of_elaboration() | |
void | start_of_simulation_phase(uvm_phase phase) | |
void | start_of_simulation() | |
void | run_phase(uvm_phase phase) | |
void | run() | |
void | pre_reset_phase(uvm_phase phase) | |
void | reset_phase(uvm_phase phase) | |
void | post_reset_phase(uvm_phase phase) | |
void | pre_configure_phase(uvm_phase phase) | |
void | configure_phase(uvm_phase phase) | |
void | post_configure_phase(uvm_phase phase) | |
void | pre_main_phase(uvm_phase phase) | |
void | main_phase(uvm_phase phase) | |
void | post_main_phase(uvm_phase phase) | |
void | pre_shutdown_phase(uvm_phase phase) | |
void | shutdown_phase(uvm_phase phase) | |
void | post_shutdown_phase(uvm_phase phase) | |
void | extract_phase(uvm_phase phase) | |
void | extract() | |
void | check_phase(uvm_phase phase) | |
void | check() | |
void | report_phase(uvm_phase phase) | |
void | report() | |
void | final_phase(uvm_phase phase) | |
void | phase_started(uvm_phase phase) | |
void | phase_ready_to_end(uvm_phase phase) | |
void | phase_ended(uvm_phase phase) | |
void | set_domain(uvm_domain domain, int hier) | |
uvm_domain | get_domain() | |
void | define_domain(uvm_domain domain) | |
void | set_phase_imp(uvm_phase phase, uvm_phase imp, int hier) | |
void | suspend() | |
void | resume() | |
string | status() | |
void | kill() | |
void | do_kill_all() | |
void | stop_phase(uvm_phase phase) | |
void | stop(string ph_name) | |
void | resolve_bindings() | |
string | massage_scope(string scope) | |
void | set_config_int(string inst_name, string field_name, uvm_bitstream_t value) | |
void | set_config_string(string inst_name, string field_name, string value) | |
void | set_config_object(string inst_name, string field_name, uvm_object value, bit clone) | |
bit | get_config_int(string field_name, uvm_bitstream_t value) | |
bit | get_config_string(string field_name, string value) | |
bit | get_config_object(string field_name, uvm_object value, bit clone) | |
void | check_config_usage(bit recurse) | |
void | apply_config_settings(bit verbose) | |
void | print_config_settings(string field, uvm_component comp, bit recurse) | |
void | print_config(bit recurse, bit audit) | |
void | print_config_with_audit(bit recurse) | |
void | raised(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
uvm_component | create_component(string requested_type_name, string name) | |
uvm_object | create_object(string requested_type_name, string name) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type) | |
void | set_type_override(string original_type_name, string override_type_name, bit replace) | |
void | set_inst_override(string relative_inst_path, string original_type_name, string override_type_name) | |
void | print_override_info(string requested_type_name, string name) | |
void | set_report_id_verbosity_hier(string id, int verbosity) | |
void | set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity) | |
void | set_report_severity_action_hier(uvm_severity severity, uvm_action action) | |
void | set_report_id_action_hier(string id, uvm_action action) | |
void | set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action) | |
void | set_report_default_file_hier(UVM_FILE file) | |
void | set_report_severity_file_hier(uvm_severity severity, UVM_FILE file) | |
void | set_report_id_file_hier(string id, UVM_FILE file) | |
void | set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_verbosity_level_hier(int verbosity) | |
void | pre_abort() | |
void | accept_tr(uvm_transaction tr, time accept_time) | |
void | do_accept_tr(uvm_transaction tr) | |
integer | begin_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle) | |
integer | begin_child_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | do_begin_tr(uvm_transaction tr, string stream_name, integer tr_handle) | |
void | end_tr(uvm_transaction tr, time end_time, bit free_handle) | |
void | do_end_tr(uvm_transaction tr, integer tr_handle) | |
integer | record_error_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active) | |
integer | record_event_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active) | |
uvm_tr_stream | get_tr_stream(string name, string stream_type_name) | |
void | free_tr_stream(uvm_tr_stream stream) | |
uvm_tr_database | m_get_tr_database() | |
bit | m_add_child(uvm_component child) | |
void | m_set_full_name() | |
void | do_resolve_bindings() | |
void | do_flush() | |
void | flush() | |
void | m_extract_name(string name, string leaf, string remainder) | |
integer | m_begin_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | m_set_cl_msg_args() | |
void | m_set_cl_verb() | |
void | m_set_cl_action() | |
void | m_set_cl_sev() | |
void | m_apply_verbosity_settings(uvm_phase phase) | |
void | m_do_pre_abort() |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_analysis_imp | before_export | |
uvm_analysis_export | after_export | |
uvm_in_order_class_comparator | comp | |
TRANSFORMER | m_transformer |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
logic | new(string name, uvm_component parent, TRANSFORMER transformer) | |
string | get_type_name() | |
void | connect_phase(uvm_phase phase) | |
void | write(BEFORE b) |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_blocking_put_port | blocking_put_port | |
bit | m_stop |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
logic | new(string name, uvm_component parent) | |
void | generate_stimulus(T t, int max_count) | |
void | stop_stimulus_generation() | |
string | get_type_name() |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
uvm_analysis_imp | analysis_export |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | write(T t) |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
string | type_name |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
string | get_type_name() |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
uvm_seq_item_pull_port | seq_item_port | |
uvm_seq_item_pull_port | seq_item_prod_if | alias |
uvm_analysis_port | rsp_port | |
REQ | req | |
RSP | rsp | |
string | type_name |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | new |
string | get_type_name() |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
uvm_blocking_put_imp | req_export | |
uvm_analysis_port | rsp_port | |
REQ | req | |
RSP | rsp | |
string | type_name |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | check_port_connections() | |
void | end_of_elaboration_phase(uvm_phase phase) | |
void | put(REQ item) | |
string | get_type_name() |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
string | type_name |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
string | get_type_name() |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
uvm_active_passive_enum | is_active | |
string | type_name |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | build_phase(uvm_phase phase) | |
string | get_type_name() | |
uvm_active_passive_enum | get_is_active() |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
string | type_name |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
string | get_type_name() |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
string | type_name |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
string | get_type_name() |
Extends: uvm_transaction
| Type | Name | Description |
|---|---|---|
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
string | get_type_name() | |
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_full_name() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
void | do_print(uvm_printer printer) |
Utility class for tracking default_sequences
| Type | Name | Description |
|---|---|---|
unknown | pid | |
uvm_sequence_base | seq |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
uvm_sequence_request[] | arb_sequence_q | |
bit[] | arb_completed | |
uvm_sequence_base[] | lock_list | |
uvm_sequence_base[] | reg_sequences | |
int | m_sequencer_id | |
int | m_lock_arb_size | used for waiting processes |
int | m_arb_size | used for waiting processes |
int | m_wait_for_item_sequence_id | |
int | m_wait_for_item_transaction_id | |
int | m_wait_relevant_count | |
int | m_max_zero_time_wait_relevant_count | |
time | m_last_wait_relevant_time | |
uvm_sequencer_arb_mode | m_arbitration | |
int | g_request_id | |
int | g_sequence_id | |
int | g_sequencer_id | |
uvm_sequence_process_wrapper[] | m_default_sequences | |
int | m_is_relevant_completed | |
bit | m_auto_item_recording | |
int | count | |
int | m_random_count | |
int | m_exhaustive_count | |
int | m_simple_count | |
int | max_random_count | |
int | max_random_depth | |
string | default_sequence | |
bit | m_default_seq_set | |
string[] | sequences | |
int[] | sequence_ids | |
int | seq_kind |
| Type | Method | Description |
|---|---|---|
uvm_sequencer_base | new(string name, uvm_component parent) | |
bit | is_child(uvm_sequence_base parent, uvm_sequence_base child) | |
integer | user_priority_arbitration(integer[] avail_sequences) | |
void | execute_item(uvm_sequence_item item) | |
void | start_phase_sequence(uvm_phase phase) | |
void | stop_phase_sequence(uvm_phase phase) | |
void | wait_for_grant(uvm_sequence_base sequence_ptr, int item_priority, bit lock_request) | |
void | wait_for_item_done(uvm_sequence_base sequence_ptr, int transaction_id) | |
bit | is_blocked(uvm_sequence_base sequence_ptr) | |
bit | has_lock(uvm_sequence_base sequence_ptr) | |
void | lock(uvm_sequence_base sequence_ptr) | |
void | grab(uvm_sequence_base sequence_ptr) | |
void | unlock(uvm_sequence_base sequence_ptr) | |
void | ungrab(uvm_sequence_base sequence_ptr) | |
void | stop_sequences() | |
bit | is_grabbed() | |
uvm_sequence_base | current_grabber() | |
bit | has_do_available() | |
void | set_arbitration(UVM_SEQ_ARB_TYPE val) | |
UVM_SEQ_ARB_TYPE | get_arbitration() | |
void | wait_for_sequences() | |
void | send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize) | |
void | set_max_zero_time_wait_relevant_count(int new_val) | |
void | grant_queued_locks() | |
void | m_select_sequence() | |
int | m_choose_next_request() | |
void | m_wait_for_arbitration_completed(int request_id) | |
void | m_set_arbitration_completed(int request_id) | |
void | m_lock_req(uvm_sequence_base sequence_ptr, bit lock) | |
void | m_unlock_req(uvm_sequence_base sequence_ptr) | |
void | remove_sequence_from_queues(uvm_sequence_base sequence_ptr) | |
void | m_sequence_exiting(uvm_sequence_base sequence_ptr) | |
void | kill_sequence(uvm_sequence_base sequence_ptr) | |
void | analysis_write(uvm_sequence_item t) | |
void | build() | |
void | build_phase(uvm_phase phase) | |
void | do_print(uvm_printer printer) | |
int | m_register_sequence(uvm_sequence_base sequence_ptr) | |
void | m_unregister_sequence(int sequence_id) | |
uvm_sequence_base | m_find_sequence(int sequence_id) | |
void | m_update_lists() | |
string | convert2string() | |
int | m_find_number_driver_connections() | |
void | m_wait_arb_not_equal() | |
void | m_wait_for_available_sequence() | |
int | m_get_seq_item_priority(uvm_sequence_request seq_q_entry) | |
void | disable_auto_item_recording() | |
bit | is_auto_item_recording_enabled() | |
void | add_sequence(string type_name) | |
void | remove_sequence(string type_name) | |
void | set_sequences_queue(string[] sequencer_sequence_lib) | |
void | start_default_sequence() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
int | num_sequences() | |
void | m_add_builtin_seqs(bit add_simple) | |
void | run_phase(uvm_phase phase) |
| Type | Name | Description |
|---|---|---|
bit | grant | |
int | sequence_id | |
int | request_id | |
int | item_priority | |
unknown | process_id | |
seq_req_t | request | |
uvm_sequence_base | sequence_ptr |
| Type | Name | Description |
|---|---|---|
uvm_analysis_imp | analysis_export | |
uvm_sequencer_base | sequencer_ptr | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_report_handler | m_rh | |
int | enable_stop_interrupt | |
bit | m_config_deprecated_warned | |
bit | m_config_set | |
bit | print_config_matches | |
bit | print_enabled | |
uvm_tr_database | tr_database | Variable: tr_database Specifies the <uvm_tr_database> object to use for <begin_tr>
and other methods in the . |
uvm_domain | m_domain | set_domain stores our domain handle |
uvm_phase[] | m_phase_imps | functors to override ovm_root defaults |
uvm_phase | m_current_phase | the most recently executed phase |
unknown | m_phase_process | |
bit | m_build_done | |
int | m_phasing_active | |
uvm_component | m_parent | |
uvm_component[] | m_children | |
uvm_component[] | m_children_by_handle | |
uvm_tr_stream | m_main_stream | |
unknown[] | m_streams | |
uvm_recorder[] | m_tr_h | |
string | m_name | |
string | type_name | |
uvm_event_pool | event_pool | |
int | recording_detail | |
m_verbosity_setting[] | m_verbosity_settings | |
m_verbosity_setting[] | m_time_settings | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_action | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_sev | |
uvm_put_imp | put_export | |
uvm_get_peek_imp | get_peek_export | |
uvm_analysis_port | put_ap | |
uvm_analysis_port | get_ap | |
uvm_put_imp | blocking_put_export | |
uvm_put_imp | nonblocking_put_export | |
uvm_get_peek_imp | blocking_get_export | |
uvm_get_peek_imp | nonblocking_get_export | |
uvm_get_peek_imp | get_export | |
uvm_get_peek_imp | blocking_peek_export | |
uvm_get_peek_imp | nonblocking_peek_export | |
uvm_get_peek_imp | peek_export | |
uvm_get_peek_imp | blocking_get_peek_export | |
uvm_get_peek_imp | nonblocking_get_peek_export | |
anonymous | m | |
int | m_size | |
int | m_pending_blocked_gets |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | write(RSP t) | void |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
int | get_report_verbosity_level(uvm_severity severity, string id) | |
int | get_report_max_verbosity_level() | |
void | set_report_verbosity_level(int verbosity_level) | |
void | set_report_id_verbosity(string id, int verbosity) | Function: set_report_id_verbosity |
void | set_report_severity_id_verbosity(uvm_severity severity, string id, int verbosity) | |
int | get_report_action(uvm_severity severity, string id) | |
void | set_report_severity_action(uvm_severity severity, uvm_action action) | Function: set_report_severity_action |
void | set_report_id_action(string id, uvm_action action) | Function: set_report_id_action |
void | set_report_severity_id_action(uvm_severity severity, string id, uvm_action action) | |
int | get_report_file_handle(uvm_severity severity, string id) | |
void | set_report_default_file(UVM_FILE file) | |
void | set_report_id_file(string id, UVM_FILE file) | |
void | set_report_severity_file(uvm_severity severity, UVM_FILE file) | Function: set_report_severity_file |
void | set_report_severity_id_file(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity) | Function: set_report_severity_override |
void | set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity) | Function: set_report_severity_id_override These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~. |
void | set_report_handler(uvm_report_handler handler) | |
uvm_report_handler | get_report_handler() | |
void | reset_report_handler() | |
bit | report_info_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_error_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_warning_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_fatal_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_hook(string id, string message, int verbosity, string filename, int line) | |
void | report_header(UVM_FILE file) | |
void | report_summarize(UVM_FILE file) | |
void | die() | |
void | set_report_max_quit_count(int max_count) | |
uvm_report_server | get_report_server() | |
void | dump_report_state() | |
uvm_component | get_parent() | |
void | get_children(uvm_component[] children) | |
uvm_component | get_child(string name) | |
int | get_next_child(string name) | |
int | get_first_child(string name) | |
int | get_num_children() | |
int | has_child(string name) | |
uvm_component | lookup(string name) | |
int | get_depth() | |
void | build_phase(uvm_phase phase) | turn off auto config |
void | build() | |
void | connect_phase(uvm_phase phase) | |
void | connect() | |
void | end_of_elaboration_phase(uvm_phase phase) | |
void | end_of_elaboration() | |
void | start_of_simulation_phase(uvm_phase phase) | |
void | start_of_simulation() | |
void | run_phase(uvm_phase phase) | |
void | run() | |
void | pre_reset_phase(uvm_phase phase) | |
void | reset_phase(uvm_phase phase) | |
void | post_reset_phase(uvm_phase phase) | |
void | pre_configure_phase(uvm_phase phase) | |
void | configure_phase(uvm_phase phase) | |
void | post_configure_phase(uvm_phase phase) | |
void | pre_main_phase(uvm_phase phase) | |
void | main_phase(uvm_phase phase) | |
void | post_main_phase(uvm_phase phase) | |
void | pre_shutdown_phase(uvm_phase phase) | |
void | shutdown_phase(uvm_phase phase) | |
void | post_shutdown_phase(uvm_phase phase) | |
void | extract_phase(uvm_phase phase) | |
void | extract() | |
void | check_phase(uvm_phase phase) | |
void | check() | |
void | report_phase(uvm_phase phase) | |
void | report() | |
void | final_phase(uvm_phase phase) | |
void | phase_started(uvm_phase phase) | |
void | phase_ready_to_end(uvm_phase phase) | |
void | phase_ended(uvm_phase phase) | |
void | set_domain(uvm_domain domain, int hier) | |
uvm_domain | get_domain() | |
void | define_domain(uvm_domain domain) | |
void | set_phase_imp(uvm_phase phase, uvm_phase imp, int hier) | |
void | suspend() | |
void | resume() | |
string | status() | |
void | kill() | |
void | do_kill_all() | |
void | stop_phase(uvm_phase phase) | |
void | stop(string ph_name) | |
void | resolve_bindings() | |
string | massage_scope(string scope) | |
void | set_config_int(string inst_name, string field_name, uvm_bitstream_t value) | |
void | set_config_string(string inst_name, string field_name, string value) | |
void | set_config_object(string inst_name, string field_name, uvm_object value, bit clone) | |
bit | get_config_int(string field_name, uvm_bitstream_t value) | |
bit | get_config_string(string field_name, string value) | |
bit | get_config_object(string field_name, uvm_object value, bit clone) | |
void | check_config_usage(bit recurse) | |
void | apply_config_settings(bit verbose) | |
void | print_config_settings(string field, uvm_component comp, bit recurse) | |
void | print_config(bit recurse, bit audit) | |
void | print_config_with_audit(bit recurse) | |
void | raised(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
uvm_component | create_component(string requested_type_name, string name) | |
uvm_object | create_object(string requested_type_name, string name) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type) | |
void | set_type_override(string original_type_name, string override_type_name, bit replace) | |
void | set_inst_override(string relative_inst_path, string original_type_name, string override_type_name) | |
void | print_override_info(string requested_type_name, string name) | |
void | set_report_id_verbosity_hier(string id, int verbosity) | |
void | set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity) | |
void | set_report_severity_action_hier(uvm_severity severity, uvm_action action) | |
void | set_report_id_action_hier(string id, uvm_action action) | |
void | set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action) | |
void | set_report_default_file_hier(UVM_FILE file) | |
void | set_report_severity_file_hier(uvm_severity severity, UVM_FILE file) | |
void | set_report_id_file_hier(string id, UVM_FILE file) | |
void | set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_verbosity_level_hier(int verbosity) | |
void | pre_abort() | |
void | accept_tr(uvm_transaction tr, time accept_time) | |
void | do_accept_tr(uvm_transaction tr) | |
integer | begin_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle) | |
integer | begin_child_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | do_begin_tr(uvm_transaction tr, string stream_name, integer tr_handle) | |
void | end_tr(uvm_transaction tr, time end_time, bit free_handle) | |
void | do_end_tr(uvm_transaction tr, integer tr_handle) | |
integer | record_error_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active) | |
integer | record_event_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active) | |
uvm_tr_stream | get_tr_stream(string name, string stream_type_name) | |
void | free_tr_stream(uvm_tr_stream stream) | |
uvm_tr_database | m_get_tr_database() | |
bit | m_add_child(uvm_component child) | |
void | m_set_full_name() | |
void | do_resolve_bindings() | |
void | do_flush() | |
void | flush() | |
void | m_extract_name(string name, string leaf, string remainder) | |
integer | m_begin_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | m_set_cl_msg_args() | |
void | m_set_cl_verb() | |
void | m_set_cl_action() | |
void | m_set_cl_sev() | |
void | m_apply_verbosity_settings(uvm_phase phase) | |
void | m_do_pre_abort() | |
int | size() | |
void | put(T t) | |
void | get(T t) | |
void | peek(T t) | |
bit | try_put(T t) | |
bit | try_get(T t) | |
bit | try_peek(T t) | |
bit | can_put() | |
bit | can_get() | |
bit | can_peek() | |
uvm_tlm_event | ok_to_put() | |
uvm_tlm_event | ok_to_get() | |
uvm_tlm_event | ok_to_peek() | |
bit | is_empty() | |
bit | is_full() | |
int | used() |
Extends: uvm_sequencer_base
| Type | Name | Description |
|---|---|---|
REQ[] | m_last_req_buffer | |
RSP[] | m_last_rsp_buffer | |
int | m_num_last_reqs | |
int | num_last_items | |
int | m_num_last_rsps | |
int | m_num_reqs_sent | |
int | m_num_rsps_received | |
uvm_sequencer_analysis_fifo | sqr_rsp_analysis_fifo | |
uvm_analysis_export | rsp_export | |
uvm_tlm_fifo | m_req_fifo |
| Type | Method | Description |
|---|---|---|
uvm_sequencer_param_base | new(string name, uvm_component parent) | |
void | send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize) | |
REQ | get_current_item() | Function: get_current_item Returns the request_item currently being executed by the sequencer. If the sequencer is not currently executing an item, this method will return ~null~. The sequencer is executing an item from the time that get_next_item or peek is called until the time that get or item_done is called. Note that a driver that only calls get() will never show a current item, since the item is completed at the same time as it is requested. |
int | get_num_reqs_sent() | |
void | set_num_last_reqs(int max) | |
int | get_num_last_reqs() | |
REQ | last_req(int n) | Function: last_req Returns the last request item by default. If n is not 0, then it will get the n�th before last request item. If n is greater than the last request buffer size, the function will return ~null~. |
int | get_num_rsps_received() | |
void | set_num_last_rsps(int max) | |
int | get_num_last_rsps() | |
RSP | last_rsp(int n) | Function: last_rsp Returns the last response item by default. If n is not 0, then it will get the nth-before-last response item. If n is greater than the last response buffer size, the function will return ~null~. |
void | m_last_rsp_push_front(RSP item) | |
void | put_response(RSP t) | |
void | build_phase(uvm_phase phase) | |
void | connect_phase(uvm_phase phase) | |
void | do_print(uvm_printer printer) | |
void | analysis_write(uvm_sequence_item t) | |
void | m_last_req_push_front(REQ item) |
| Type | Name | Description |
|---|---|---|
bit | sequence_item_requested | |
bit | get_next_item_called | |
uvm_seq_item_pull_imp | seq_item_export | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_report_handler | m_rh | |
int | enable_stop_interrupt | |
bit | m_config_deprecated_warned | |
bit | m_config_set | |
bit | print_config_matches | |
bit | print_enabled | |
uvm_tr_database | tr_database | Variable: tr_database Specifies the <uvm_tr_database> object to use for <begin_tr>
and other methods in the . |
uvm_domain | m_domain | set_domain stores our domain handle |
uvm_phase[] | m_phase_imps | functors to override ovm_root defaults |
uvm_phase | m_current_phase | the most recently executed phase |
unknown | m_phase_process | |
bit | m_build_done | |
int | m_phasing_active | |
uvm_component | m_parent | |
uvm_component[] | m_children | |
uvm_component[] | m_children_by_handle | |
uvm_tr_stream | m_main_stream | |
unknown[] | m_streams | |
uvm_recorder[] | m_tr_h | |
string | m_name | |
string | type_name | |
uvm_event_pool | event_pool | |
int | recording_detail | |
m_verbosity_setting[] | m_verbosity_settings | |
m_verbosity_setting[] | m_time_settings | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_action | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_sev | |
uvm_sequence_request[] | arb_sequence_q | |
bit[] | arb_completed | |
uvm_sequence_base[] | lock_list | |
uvm_sequence_base[] | reg_sequences | |
int | m_sequencer_id | |
int | m_lock_arb_size | used for waiting processes |
int | m_arb_size | used for waiting processes |
int | m_wait_for_item_sequence_id | |
int | m_wait_for_item_transaction_id | |
int | m_wait_relevant_count | |
int | m_max_zero_time_wait_relevant_count | |
time | m_last_wait_relevant_time | |
uvm_sequencer_arb_mode | m_arbitration | |
int | g_request_id | |
int | g_sequence_id | |
int | g_sequencer_id | |
uvm_sequence_process_wrapper[] | m_default_sequences | |
int | m_is_relevant_completed | |
bit | m_auto_item_recording | |
int | count | |
int | m_random_count | |
int | m_exhaustive_count | |
int | m_simple_count | |
int | max_random_count | |
int | max_random_depth | |
string | default_sequence | |
bit | m_default_seq_set | |
string[] | sequences | |
int[] | sequence_ids | |
int | seq_kind | |
REQ[] | m_last_req_buffer | |
RSP[] | m_last_rsp_buffer | |
int | m_num_last_reqs | |
int | num_last_items | |
int | m_num_last_rsps | |
int | m_num_reqs_sent | |
int | m_num_rsps_received | |
uvm_sequencer_analysis_fifo | sqr_rsp_analysis_fifo | |
uvm_analysis_export | rsp_export | |
uvm_tlm_fifo | m_req_fifo |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_sequencer | new(string name, uvm_component parent) | |
void | stop_sequences() | |
string | get_type_name() | |
void | get_next_item(REQ t) | |
void | try_next_item(REQ t) | |
void | item_done(RSP item) | |
void | put(RSP t) | |
void | get(REQ t) | |
void | peek(REQ t) | |
void | item_done_trigger(RSP item) | |
RSP | item_done_get_trigger_data() | |
int | m_find_number_driver_connections() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
int | get_report_verbosity_level(uvm_severity severity, string id) | |
int | get_report_max_verbosity_level() | |
void | set_report_verbosity_level(int verbosity_level) | |
void | set_report_id_verbosity(string id, int verbosity) | Function: set_report_id_verbosity |
void | set_report_severity_id_verbosity(uvm_severity severity, string id, int verbosity) | |
int | get_report_action(uvm_severity severity, string id) | |
void | set_report_severity_action(uvm_severity severity, uvm_action action) | Function: set_report_severity_action |
void | set_report_id_action(string id, uvm_action action) | Function: set_report_id_action |
void | set_report_severity_id_action(uvm_severity severity, string id, uvm_action action) | |
int | get_report_file_handle(uvm_severity severity, string id) | |
void | set_report_default_file(UVM_FILE file) | |
void | set_report_id_file(string id, UVM_FILE file) | |
void | set_report_severity_file(uvm_severity severity, UVM_FILE file) | Function: set_report_severity_file |
void | set_report_severity_id_file(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity) | Function: set_report_severity_override |
void | set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity) | Function: set_report_severity_id_override These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~. |
void | set_report_handler(uvm_report_handler handler) | |
uvm_report_handler | get_report_handler() | |
void | reset_report_handler() | |
bit | report_info_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_error_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_warning_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_fatal_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_hook(string id, string message, int verbosity, string filename, int line) | |
void | report_header(UVM_FILE file) | |
void | report_summarize(UVM_FILE file) | |
void | die() | |
void | set_report_max_quit_count(int max_count) | |
uvm_report_server | get_report_server() | |
void | dump_report_state() | |
uvm_component | get_parent() | |
void | get_children(uvm_component[] children) | |
uvm_component | get_child(string name) | |
int | get_next_child(string name) | |
int | get_first_child(string name) | |
int | get_num_children() | |
int | has_child(string name) | |
uvm_component | lookup(string name) | |
int | get_depth() | |
void | build_phase(uvm_phase phase) | |
void | build() | |
void | connect_phase(uvm_phase phase) | |
void | connect() | |
void | end_of_elaboration_phase(uvm_phase phase) | |
void | end_of_elaboration() | |
void | start_of_simulation_phase(uvm_phase phase) | |
void | start_of_simulation() | |
void | run_phase(uvm_phase phase) | |
void | run() | |
void | pre_reset_phase(uvm_phase phase) | |
void | reset_phase(uvm_phase phase) | |
void | post_reset_phase(uvm_phase phase) | |
void | pre_configure_phase(uvm_phase phase) | |
void | configure_phase(uvm_phase phase) | |
void | post_configure_phase(uvm_phase phase) | |
void | pre_main_phase(uvm_phase phase) | |
void | main_phase(uvm_phase phase) | |
void | post_main_phase(uvm_phase phase) | |
void | pre_shutdown_phase(uvm_phase phase) | |
void | shutdown_phase(uvm_phase phase) | |
void | post_shutdown_phase(uvm_phase phase) | |
void | extract_phase(uvm_phase phase) | |
void | extract() | |
void | check_phase(uvm_phase phase) | |
void | check() | |
void | report_phase(uvm_phase phase) | |
void | report() | |
void | final_phase(uvm_phase phase) | |
void | phase_started(uvm_phase phase) | |
void | phase_ready_to_end(uvm_phase phase) | |
void | phase_ended(uvm_phase phase) | |
void | set_domain(uvm_domain domain, int hier) | |
uvm_domain | get_domain() | |
void | define_domain(uvm_domain domain) | |
void | set_phase_imp(uvm_phase phase, uvm_phase imp, int hier) | |
void | suspend() | |
void | resume() | |
string | status() | |
void | kill() | |
void | do_kill_all() | |
void | stop_phase(uvm_phase phase) | |
void | stop(string ph_name) | |
void | resolve_bindings() | |
string | massage_scope(string scope) | |
void | set_config_int(string inst_name, string field_name, uvm_bitstream_t value) | |
void | set_config_string(string inst_name, string field_name, string value) | |
void | set_config_object(string inst_name, string field_name, uvm_object value, bit clone) | |
bit | get_config_int(string field_name, uvm_bitstream_t value) | |
bit | get_config_string(string field_name, string value) | |
bit | get_config_object(string field_name, uvm_object value, bit clone) | |
void | check_config_usage(bit recurse) | |
void | apply_config_settings(bit verbose) | |
void | print_config_settings(string field, uvm_component comp, bit recurse) | |
void | print_config(bit recurse, bit audit) | |
void | print_config_with_audit(bit recurse) | |
void | raised(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
uvm_component | create_component(string requested_type_name, string name) | |
uvm_object | create_object(string requested_type_name, string name) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type) | |
void | set_type_override(string original_type_name, string override_type_name, bit replace) | |
void | set_inst_override(string relative_inst_path, string original_type_name, string override_type_name) | |
void | print_override_info(string requested_type_name, string name) | |
void | set_report_id_verbosity_hier(string id, int verbosity) | |
void | set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity) | |
void | set_report_severity_action_hier(uvm_severity severity, uvm_action action) | |
void | set_report_id_action_hier(string id, uvm_action action) | |
void | set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action) | |
void | set_report_default_file_hier(UVM_FILE file) | |
void | set_report_severity_file_hier(uvm_severity severity, UVM_FILE file) | |
void | set_report_id_file_hier(string id, UVM_FILE file) | |
void | set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_verbosity_level_hier(int verbosity) | |
void | pre_abort() | |
void | accept_tr(uvm_transaction tr, time accept_time) | |
void | do_accept_tr(uvm_transaction tr) | |
integer | begin_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle) | |
integer | begin_child_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | do_begin_tr(uvm_transaction tr, string stream_name, integer tr_handle) | |
void | end_tr(uvm_transaction tr, time end_time, bit free_handle) | |
void | do_end_tr(uvm_transaction tr, integer tr_handle) | |
integer | record_error_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active) | |
integer | record_event_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active) | |
uvm_tr_stream | get_tr_stream(string name, string stream_type_name) | |
void | free_tr_stream(uvm_tr_stream stream) | |
uvm_tr_database | m_get_tr_database() | |
bit | m_add_child(uvm_component child) | |
void | m_set_full_name() | |
void | do_resolve_bindings() | |
void | do_flush() | |
void | flush() | |
void | m_extract_name(string name, string leaf, string remainder) | |
integer | m_begin_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | m_set_cl_msg_args() | |
void | m_set_cl_verb() | |
void | m_set_cl_action() | |
void | m_set_cl_sev() | |
void | m_apply_verbosity_settings(uvm_phase phase) | |
void | m_do_pre_abort() | |
bit | is_child(uvm_sequence_base parent, uvm_sequence_base child) | |
integer | user_priority_arbitration(integer[] avail_sequences) | |
void | execute_item(uvm_sequence_item item) | |
void | start_phase_sequence(uvm_phase phase) | |
void | stop_phase_sequence(uvm_phase phase) | |
void | wait_for_grant(uvm_sequence_base sequence_ptr, int item_priority, bit lock_request) | |
void | wait_for_item_done(uvm_sequence_base sequence_ptr, int transaction_id) | |
bit | is_blocked(uvm_sequence_base sequence_ptr) | |
bit | has_lock(uvm_sequence_base sequence_ptr) | |
void | lock(uvm_sequence_base sequence_ptr) | |
void | grab(uvm_sequence_base sequence_ptr) | |
void | unlock(uvm_sequence_base sequence_ptr) | |
void | ungrab(uvm_sequence_base sequence_ptr) | |
bit | is_grabbed() | |
uvm_sequence_base | current_grabber() | |
bit | has_do_available() | |
void | set_arbitration(UVM_SEQ_ARB_TYPE val) | |
UVM_SEQ_ARB_TYPE | get_arbitration() | |
void | wait_for_sequences() | |
void | send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize) | |
void | set_max_zero_time_wait_relevant_count(int new_val) | |
void | grant_queued_locks() | |
void | m_select_sequence() | |
int | m_choose_next_request() | |
void | m_wait_for_arbitration_completed(int request_id) | |
void | m_set_arbitration_completed(int request_id) | |
void | m_lock_req(uvm_sequence_base sequence_ptr, bit lock) | |
void | m_unlock_req(uvm_sequence_base sequence_ptr) | |
void | remove_sequence_from_queues(uvm_sequence_base sequence_ptr) | |
void | m_sequence_exiting(uvm_sequence_base sequence_ptr) | |
void | kill_sequence(uvm_sequence_base sequence_ptr) | |
void | analysis_write(uvm_sequence_item t) | |
int | m_register_sequence(uvm_sequence_base sequence_ptr) | |
void | m_unregister_sequence(int sequence_id) | |
uvm_sequence_base | m_find_sequence(int sequence_id) | |
void | m_update_lists() | |
void | m_wait_arb_not_equal() | |
void | m_wait_for_available_sequence() | |
int | m_get_seq_item_priority(uvm_sequence_request seq_q_entry) | |
void | disable_auto_item_recording() | |
bit | is_auto_item_recording_enabled() | |
void | add_sequence(string type_name) | |
void | remove_sequence(string type_name) | |
void | set_sequences_queue(string[] sequencer_sequence_lib) | |
void | start_default_sequence() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
int | num_sequences() | |
void | m_add_builtin_seqs(bit add_simple) | |
REQ | get_current_item() | Function: get_current_item Returns the request_item currently being executed by the sequencer. If the sequencer is not currently executing an item, this method will return ~null~. The sequencer is executing an item from the time that get_next_item or peek is called until the time that get or item_done is called. Note that a driver that only calls get() will never show a current item, since the item is completed at the same time as it is requested. |
int | get_num_reqs_sent() | |
void | set_num_last_reqs(int max) | |
int | get_num_last_reqs() | |
REQ | last_req(int n) | Function: last_req Returns the last request item by default. If n is not 0, then it will get the n�th before last request item. If n is greater than the last request buffer size, the function will return ~null~. |
int | get_num_rsps_received() | |
void | set_num_last_rsps(int max) | |
int | get_num_last_rsps() | |
RSP | last_rsp(int n) | Function: last_rsp Returns the last response item by default. If n is not 0, then it will get the nth-before-last response item. If n is greater than the last response buffer size, the function will return ~null~. |
void | m_last_rsp_push_front(RSP item) | |
void | put_response(RSP t) | |
void | m_last_req_push_front(REQ item) |
| Type | Name | Description |
|---|---|---|
uvm_blocking_put_port | req_port | Port: req_port The push sequencer requires access to a blocking put interface. A continuous stream of sequence items are sent out this port, based on the list of available sequences loaded into this sequencer. |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_report_handler | m_rh | |
int | enable_stop_interrupt | |
bit | m_config_deprecated_warned | |
bit | m_config_set | |
bit | print_config_matches | |
bit | print_enabled | |
uvm_tr_database | tr_database | Variable: tr_database Specifies the <uvm_tr_database> object to use for <begin_tr>
and other methods in the . |
uvm_domain | m_domain | set_domain stores our domain handle |
uvm_phase[] | m_phase_imps | functors to override ovm_root defaults |
uvm_phase | m_current_phase | the most recently executed phase |
unknown | m_phase_process | |
bit | m_build_done | |
int | m_phasing_active | |
uvm_component | m_parent | |
uvm_component[] | m_children | |
uvm_component[] | m_children_by_handle | |
uvm_tr_stream | m_main_stream | |
unknown[] | m_streams | |
uvm_recorder[] | m_tr_h | |
string | m_name | |
string | type_name | |
uvm_event_pool | event_pool | |
int | recording_detail | |
m_verbosity_setting[] | m_verbosity_settings | |
m_verbosity_setting[] | m_time_settings | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_action | |
uvm_cmdline_parsed_arg_t[] | m_uvm_applied_cl_sev | |
uvm_sequence_request[] | arb_sequence_q | |
bit[] | arb_completed | |
uvm_sequence_base[] | lock_list | |
uvm_sequence_base[] | reg_sequences | |
int | m_sequencer_id | |
int | m_lock_arb_size | used for waiting processes |
int | m_arb_size | used for waiting processes |
int | m_wait_for_item_sequence_id | |
int | m_wait_for_item_transaction_id | |
int | m_wait_relevant_count | |
int | m_max_zero_time_wait_relevant_count | |
time | m_last_wait_relevant_time | |
uvm_sequencer_arb_mode | m_arbitration | |
int | g_request_id | |
int | g_sequence_id | |
int | g_sequencer_id | |
uvm_sequence_process_wrapper[] | m_default_sequences | |
int | m_is_relevant_completed | |
bit | m_auto_item_recording | |
int | count | |
int | m_random_count | |
int | m_exhaustive_count | |
int | m_simple_count | |
int | max_random_count | |
int | max_random_depth | |
string | default_sequence | |
bit | m_default_seq_set | |
string[] | sequences | |
int[] | sequence_ids | |
int | seq_kind | |
REQ[] | m_last_req_buffer | |
RSP[] | m_last_rsp_buffer | |
int | m_num_last_reqs | |
int | num_last_items | |
int | m_num_last_rsps | |
int | m_num_reqs_sent | |
int | m_num_rsps_received | |
uvm_sequencer_analysis_fifo | sqr_rsp_analysis_fifo | |
uvm_analysis_export | rsp_export | |
uvm_tlm_fifo | m_req_fifo |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | Function: new Standard component constructor that creates an instance of this class using the given ~name~ and ~parent~, if any. |
void | run_phase(uvm_phase phase) | Task: run_phase The push sequencer continuously selects from its list of available sequences and sends the next item from the selected sequence out its <req_port> using req_port.put(item). Typically, the req_port would be connected to the req_export on an instance of a <uvm_push_driver #(REQ,RSP)>, which would be responsible for executing the item. |
int | m_find_number_driver_connections() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_wrapper | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
int | get_report_verbosity_level(uvm_severity severity, string id) | |
int | get_report_max_verbosity_level() | |
void | set_report_verbosity_level(int verbosity_level) | |
void | set_report_id_verbosity(string id, int verbosity) | Function: set_report_id_verbosity |
void | set_report_severity_id_verbosity(uvm_severity severity, string id, int verbosity) | |
int | get_report_action(uvm_severity severity, string id) | |
void | set_report_severity_action(uvm_severity severity, uvm_action action) | Function: set_report_severity_action |
void | set_report_id_action(string id, uvm_action action) | Function: set_report_id_action |
void | set_report_severity_id_action(uvm_severity severity, string id, uvm_action action) | |
int | get_report_file_handle(uvm_severity severity, string id) | |
void | set_report_default_file(UVM_FILE file) | |
void | set_report_id_file(string id, UVM_FILE file) | |
void | set_report_severity_file(uvm_severity severity, UVM_FILE file) | Function: set_report_severity_file |
void | set_report_severity_id_file(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_severity_override(uvm_severity cur_severity, uvm_severity new_severity) | Function: set_report_severity_override |
void | set_report_severity_id_override(uvm_severity cur_severity, string id, uvm_severity new_severity) | Function: set_report_severity_id_override These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~. |
void | set_report_handler(uvm_report_handler handler) | |
uvm_report_handler | get_report_handler() | |
void | reset_report_handler() | |
bit | report_info_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_error_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_warning_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_fatal_hook(string id, string message, int verbosity, string filename, int line) | |
bit | report_hook(string id, string message, int verbosity, string filename, int line) | |
void | report_header(UVM_FILE file) | |
void | report_summarize(UVM_FILE file) | |
void | die() | |
void | set_report_max_quit_count(int max_count) | |
uvm_report_server | get_report_server() | |
void | dump_report_state() | |
uvm_component | get_parent() | |
void | get_children(uvm_component[] children) | |
uvm_component | get_child(string name) | |
int | get_next_child(string name) | |
int | get_first_child(string name) | |
int | get_num_children() | |
int | has_child(string name) | |
uvm_component | lookup(string name) | |
int | get_depth() | |
void | build_phase(uvm_phase phase) | |
void | build() | |
void | connect_phase(uvm_phase phase) | |
void | connect() | |
void | end_of_elaboration_phase(uvm_phase phase) | |
void | end_of_elaboration() | |
void | start_of_simulation_phase(uvm_phase phase) | |
void | start_of_simulation() | |
void | run() | |
void | pre_reset_phase(uvm_phase phase) | |
void | reset_phase(uvm_phase phase) | |
void | post_reset_phase(uvm_phase phase) | |
void | pre_configure_phase(uvm_phase phase) | |
void | configure_phase(uvm_phase phase) | |
void | post_configure_phase(uvm_phase phase) | |
void | pre_main_phase(uvm_phase phase) | |
void | main_phase(uvm_phase phase) | |
void | post_main_phase(uvm_phase phase) | |
void | pre_shutdown_phase(uvm_phase phase) | |
void | shutdown_phase(uvm_phase phase) | |
void | post_shutdown_phase(uvm_phase phase) | |
void | extract_phase(uvm_phase phase) | |
void | extract() | |
void | check_phase(uvm_phase phase) | |
void | check() | |
void | report_phase(uvm_phase phase) | |
void | report() | |
void | final_phase(uvm_phase phase) | |
void | phase_started(uvm_phase phase) | |
void | phase_ready_to_end(uvm_phase phase) | |
void | phase_ended(uvm_phase phase) | |
void | set_domain(uvm_domain domain, int hier) | |
uvm_domain | get_domain() | |
void | define_domain(uvm_domain domain) | |
void | set_phase_imp(uvm_phase phase, uvm_phase imp, int hier) | |
void | suspend() | |
void | resume() | |
string | status() | |
void | kill() | |
void | do_kill_all() | |
void | stop_phase(uvm_phase phase) | |
void | stop(string ph_name) | |
void | resolve_bindings() | |
string | massage_scope(string scope) | |
void | set_config_int(string inst_name, string field_name, uvm_bitstream_t value) | |
void | set_config_string(string inst_name, string field_name, string value) | |
void | set_config_object(string inst_name, string field_name, uvm_object value, bit clone) | |
bit | get_config_int(string field_name, uvm_bitstream_t value) | |
bit | get_config_string(string field_name, string value) | |
bit | get_config_object(string field_name, uvm_object value, bit clone) | |
void | check_config_usage(bit recurse) | |
void | apply_config_settings(bit verbose) | |
void | print_config_settings(string field, uvm_component comp, bit recurse) | |
void | print_config(bit recurse, bit audit) | |
void | print_config_with_audit(bit recurse) | |
void | raised(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
void | all_dropped(uvm_objection objection, uvm_object source_obj, string description, int count) | |
uvm_component | create_component(string requested_type_name, string name) | |
uvm_object | create_object(string requested_type_name, string name) | |
void | set_type_override_by_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace) | |
void | set_inst_override_by_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type) | |
void | set_type_override(string original_type_name, string override_type_name, bit replace) | |
void | set_inst_override(string relative_inst_path, string original_type_name, string override_type_name) | |
void | print_override_info(string requested_type_name, string name) | |
void | set_report_id_verbosity_hier(string id, int verbosity) | |
void | set_report_severity_id_verbosity_hier(uvm_severity severity, string id, int verbosity) | |
void | set_report_severity_action_hier(uvm_severity severity, uvm_action action) | |
void | set_report_id_action_hier(string id, uvm_action action) | |
void | set_report_severity_id_action_hier(uvm_severity severity, string id, uvm_action action) | |
void | set_report_default_file_hier(UVM_FILE file) | |
void | set_report_severity_file_hier(uvm_severity severity, UVM_FILE file) | |
void | set_report_id_file_hier(string id, UVM_FILE file) | |
void | set_report_severity_id_file_hier(uvm_severity severity, string id, UVM_FILE file) | |
void | set_report_verbosity_level_hier(int verbosity) | |
void | pre_abort() | |
void | accept_tr(uvm_transaction tr, time accept_time) | |
void | do_accept_tr(uvm_transaction tr) | |
integer | begin_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle) | |
integer | begin_child_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | do_begin_tr(uvm_transaction tr, string stream_name, integer tr_handle) | |
void | end_tr(uvm_transaction tr, time end_time, bit free_handle) | |
void | do_end_tr(uvm_transaction tr, integer tr_handle) | |
integer | record_error_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active) | |
integer | record_event_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active) | |
uvm_tr_stream | get_tr_stream(string name, string stream_type_name) | |
void | free_tr_stream(uvm_tr_stream stream) | |
uvm_tr_database | m_get_tr_database() | |
bit | m_add_child(uvm_component child) | |
void | m_set_full_name() | |
void | do_resolve_bindings() | |
void | do_flush() | |
void | flush() | |
void | m_extract_name(string name, string leaf, string remainder) | |
integer | m_begin_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time) | |
void | m_set_cl_msg_args() | |
void | m_set_cl_verb() | |
void | m_set_cl_action() | |
void | m_set_cl_sev() | |
void | m_apply_verbosity_settings(uvm_phase phase) | |
void | m_do_pre_abort() | |
bit | is_child(uvm_sequence_base parent, uvm_sequence_base child) | |
integer | user_priority_arbitration(integer[] avail_sequences) | |
void | execute_item(uvm_sequence_item item) | |
void | start_phase_sequence(uvm_phase phase) | |
void | stop_phase_sequence(uvm_phase phase) | |
void | wait_for_grant(uvm_sequence_base sequence_ptr, int item_priority, bit lock_request) | |
void | wait_for_item_done(uvm_sequence_base sequence_ptr, int transaction_id) | |
bit | is_blocked(uvm_sequence_base sequence_ptr) | |
bit | has_lock(uvm_sequence_base sequence_ptr) | |
void | lock(uvm_sequence_base sequence_ptr) | |
void | grab(uvm_sequence_base sequence_ptr) | |
void | unlock(uvm_sequence_base sequence_ptr) | |
void | ungrab(uvm_sequence_base sequence_ptr) | |
void | stop_sequences() | |
bit | is_grabbed() | |
uvm_sequence_base | current_grabber() | |
bit | has_do_available() | |
void | set_arbitration(UVM_SEQ_ARB_TYPE val) | |
UVM_SEQ_ARB_TYPE | get_arbitration() | |
void | wait_for_sequences() | |
void | send_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize) | |
void | set_max_zero_time_wait_relevant_count(int new_val) | |
void | grant_queued_locks() | |
void | m_select_sequence() | |
int | m_choose_next_request() | |
void | m_wait_for_arbitration_completed(int request_id) | |
void | m_set_arbitration_completed(int request_id) | |
void | m_lock_req(uvm_sequence_base sequence_ptr, bit lock) | |
void | m_unlock_req(uvm_sequence_base sequence_ptr) | |
void | remove_sequence_from_queues(uvm_sequence_base sequence_ptr) | |
void | m_sequence_exiting(uvm_sequence_base sequence_ptr) | |
void | kill_sequence(uvm_sequence_base sequence_ptr) | |
void | analysis_write(uvm_sequence_item t) | |
int | m_register_sequence(uvm_sequence_base sequence_ptr) | |
void | m_unregister_sequence(int sequence_id) | |
uvm_sequence_base | m_find_sequence(int sequence_id) | |
void | m_update_lists() | |
void | m_wait_arb_not_equal() | |
void | m_wait_for_available_sequence() | |
int | m_get_seq_item_priority(uvm_sequence_request seq_q_entry) | |
void | disable_auto_item_recording() | |
bit | is_auto_item_recording_enabled() | |
void | add_sequence(string type_name) | |
void | remove_sequence(string type_name) | |
void | set_sequences_queue(string[] sequencer_sequence_lib) | |
void | start_default_sequence() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
int | num_sequences() | |
void | m_add_builtin_seqs(bit add_simple) | |
REQ | get_current_item() | Function: get_current_item Returns the request_item currently being executed by the sequencer. If the sequencer is not currently executing an item, this method will return ~null~. The sequencer is executing an item from the time that get_next_item or peek is called until the time that get or item_done is called. Note that a driver that only calls get() will never show a current item, since the item is completed at the same time as it is requested. |
int | get_num_reqs_sent() | |
void | set_num_last_reqs(int max) | |
int | get_num_last_reqs() | |
REQ | last_req(int n) | Function: last_req Returns the last request item by default. If n is not 0, then it will get the n�th before last request item. If n is greater than the last request buffer size, the function will return ~null~. |
int | get_num_rsps_received() | |
void | set_num_last_rsps(int max) | |
int | get_num_last_rsps() | |
RSP | last_rsp(int n) | Function: last_rsp Returns the last response item by default. If n is not 0, then it will get the nth-before-last response item. If n is greater than the last response buffer size, the function will return ~null~. |
void | m_last_rsp_push_front(RSP item) | |
void | put_response(RSP t) | |
void | m_last_req_push_front(REQ item) |
Extends: uvm_sequence_item
| Type | Name | Description |
|---|---|---|
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
anonymous | m_sequence_process | |
bit | m_use_response_handler | |
string | type_name | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new The constructor for uvm_sequence_base. |
bit | is_item() | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
integer | get_tr_handle() | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | body() | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) |
Extends: uvm_sequence_base
| Type | Name | Description |
|---|---|---|
sequencer_t | param_sequencer | |
REQ | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
RSP | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
REQ | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | put_response(uvm_sequence_item response_item) | |
void | do_print(uvm_printer printer) | Function- do_print |
| Type | Name | Description |
|---|---|---|
uvm_sequence_lib_mode | selection_mode | Variable: selection_mode Specifies the mode used to select sequences for execution If you do not have access to an instance of the library, use the configuration resource interface. The following example sets the ~config_seq_lib~ as the default sequence for the 'main' phase on the sequencer to be located at "env.agent.sequencer" and set the selection mode to <UVM_SEQ_LIB_RANDC>. If the settings are being done from within a component, the first argument must be ~this~ and the second argument a path relative to that component. | uvm_config_db #(uvm_object_wrapper)::set(null, | "env.agent.sequencer.main_phase", | "default_sequence", | main_seq_lib::get_type()); | | uvm_config_db #(uvm_sequence_lib_mode)::set(null, | "env.agent.sequencer.main_phase", | "default_sequence.selection_mode", | UVM_SEQ_LIB_RANDC); Alternatively, you may create an instance of the sequence library a priori, initialize all its parameters, randomize it, then set it to run as-is on the sequencer. | main_seq_lib my_seq_lib; | my_seq_lib = new("my_seq_lib"); | | my_seq_lib.selection_mode = UVM_SEQ_LIB_RANDC; | my_seq_lib.min_random_count = 500; | my_seq_lib.max_random_count = 1000; | void'(my_seq_lib.randomize()); | | uvm_config_db #(uvm_sequence_base)::set(null, | "env.agent.sequencer.main_phase", | "default_sequence", | my_seq_lib); | |
int | min_random_count | Variable: min_random_count Sets the minimum number of items to execute. Use the configuration mechanism to set. See <selection_mode> for an example. |
int | max_random_count | Variable: max_random_count Sets the maximum number of items to execute. Use the configuration mechanism to set. See <selection_mode> for an example. |
int | sequences_executed | |
int | sequence_count | |
int | select_rand | |
anonymous | select_randc | |
int[] | seqs_distrib | |
uvm_object_wrapper[] | sequences | |
string | type_name | |
uvm_object_wrapper[] | m_typewide_sequences | |
bit | m_abort | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
REQ | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
RSP | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
| Type | Method | Description |
|---|---|---|
uvm_sequence_library | new(string name) | |
string | get_type_name() | |
int | select_sequence(int max) | |
void | add_typewide_sequence(uvm_object_wrapper seq_type) | |
void | add_typewide_sequences(uvm_object_wrapper[] seq_types) | |
void | add_sequence(uvm_object_wrapper seq_type) | |
void | add_sequences(uvm_object_wrapper[] seq_types) | |
void | remove_sequence(uvm_object_wrapper seq_type) | |
void | get_sequences(uvm_object_wrapper[] seq_types) | |
void | init_sequence_library() | |
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
bit | m_static_check(uvm_object_wrapper seq_type) | |
bit | m_check(uvm_object_wrapper seq_type, this_type lib) | |
bit | m_dyn_check(uvm_object_wrapper seq_type) | |
void | m_get_config() | |
bit | m_add_typewide_sequence(uvm_object_wrapper seq_type) | |
void | execute(uvm_object_wrapper wrap) | |
void | body() | |
void | do_print(uvm_printer printer) | |
void | pre_randomize() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
REQ | get_current_item() | |
void | get_response(RSP response, int transaction_id) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_sequence_lib_mode | selection_mode | |
int | min_random_count | |
int | max_random_count |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name, uvm_sequence_lib_mode mode, int min, int max) |
| Type | Name | Description |
|---|---|---|
int | l_count | |
int | l_exhaustive_seq_kind | |
int | max_kind | |
int | l_kind | |
bit | m_success | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
string | type_name | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_sequence_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
| Type | Method | Description |
|---|---|---|
int | get_count() | |
logic | new(string name) | |
void | body() | |
void | do_copy(uvm_object rhs) | Implement data functions |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_print(uvm_printer printer) | |
void | do_record(uvm_recorder recorder) | void |
uvm_object | create(string name) | |
string | get_type_name() | |
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_sequence_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) |
| Type | Name | Description |
|---|---|---|
int | l_count | |
int | l_exhaustive_seq_kind | |
int | max_kind | |
anonymous | l_kind | |
bit | m_success | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
string | type_name | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_sequence_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | body() | |
void | do_copy(uvm_object rhs) | Implement data functions |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_print(uvm_printer printer) | |
void | do_record(uvm_recorder recorder) | void |
uvm_object | create(string name) | |
string | get_type_name() | |
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_sequence_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) |
| Type | Name | Description |
|---|---|---|
uvm_sequence_item | item | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
string | type_name | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_sequence_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | new |
void | body() | body |
uvm_object | create(string name) | |
string | get_type_name() | |
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_sequence_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) |
CLASS: uvm_tlm_time Canonical time type that can be used in different timescales
This time type is used to represent time values in a canonical form that can bridge initiators and targets located in different timescales and time precisions.
For a detailed explanation of the purpose for this class, see .
| Type | Name | Description |
|---|---|---|
real | m_resolution | ps by default |
real | m_res | |
time | m_time | Number of 'm_res' time units, |
string | m_name |
| Type | Method | Description |
|---|---|---|
void | set_time_resolution(real res) | |
logic | new(string name, real res) | Function: new Create a new canonical time value. The new value is initialized to 0. If a resolution is not specified, the default resolution, as specified by <set_time_resolution()>, is used. |
string | get_name() | Function: get_name Return the name of this instance |
void | reset() | Function: reset Reset the value to 0 |
real | to_m_res(real t, time scaled, real secs) | |
real | get_realtime(time scaled, real secs) | Function: get_realtime Return the current canonical time value, scaled for the caller's timescale ~scaled~ must be a time literal value that corresponds to the number of seconds specified in ~secs~ (1ns by default). It must be a time literal value that is greater or equal to the current timescale. | #(delay.get_realtime(1ns)); | #(delay.get_realtime(1fs, 1.0e-15)); |
void | incr(real t, time scaled, real secs) | Function: incr Increment the time value by the specified number of scaled time unit ~t~ is a time value expressed in the scale and precision of the caller. ~scaled~ must be a time literal value that corresponds to the number of seconds specified in ~secs~ (1ns by default). It must be a time literal value that is greater or equal to the current timescale. | delay.incr(1.5ns, 1ns); | delay.incr(1.5ns, 1ps, 1.0e-12); |
void | decr(real t, time scaled, real secs) | Function: decr Decrement the time value by the specified number of scaled time unit ~t~ is a time value expressed in the scale and precision of the caller. ~scaled~ must be a time literal value that corresponds to the number of seconds specified in ~secs~ (1ns by default). It must be a time literal value that is greater or equal to the current timescale. | delay.decr(200ps, 1ns); |
real | get_abstime(real secs) | Function: get_abstime Return the current canonical time value, in the number of specified time unit, regardless of the current timescale of the caller. ~secs~ is the number of seconds in the desired time unit e.g. 1e-9 for nanoseconds. | $write("%.3f ps\n", delay.get_abstime(1e-12)); |
void | set_abstime(real t, real secs) | Function: set_abstime Set the current canonical time value, to the number of specified time unit, regardless of the current timescale of the caller. ~secs~ is the number of seconds in the time unit in the value ~t~ e.g. 1e-9 for nanoseconds. | delay.set_abstime(1.5, 1e-12)); |
Extends: uvm_sequence_item
| Type | Name | Description |
|---|---|---|
anonymous | m_address | |
uvm_tlm_command_e | m_command | |
anonymous | m_data | |
int | m_length | |
uvm_tlm_response_status_e | m_response_status | |
bit | m_dmi | Variable: m_dmi DMI mode is not yet supported in the UVM TLM2 subset. This variable is provided for completeness and interoperability with SystemC. |
anonymous | m_byte_enable | |
int | m_byte_enable_length | |
int | m_streaming_width | |
uvm_tlm_extension_base[] | m_extensions | |
anonymous | m_rand_exts | |
string | type_name |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | do_print(uvm_printer printer) | Function- do_print |
void | do_copy(uvm_object rhs) | Function- do_copy |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | Function- do_compare |
void | do_pack(uvm_packer packer) | Function- do_pack We only pack m_length bytes of the m_data array, even if m_data is larger than m_length. Same treatment for the byte-enable array. We do not pack the extensions, if any, as we will be unable to unpack them. |
void | do_unpack(uvm_packer packer) | Function- do_unpack We only reallocate m_data/m_byte_enable if the new size is greater than their current size. We do not unpack extensions because we do not know what object types to allocate before we unpack into them. Extensions must be handled by user code. |
void | do_record(uvm_recorder recorder) | Function- do_record |
string | convert2string() | Function- convert2string |
uvm_tlm_command_e | get_command() | |
void | set_command(uvm_tlm_command_e command) | |
bit | is_read() | |
void | set_read() | |
bit | is_write() | |
void | set_write() | |
void | set_address(anonymous addr) | |
bit[] | get_address() | |
void | get_data(byte[] p) | |
void | set_data(byte[] p) | |
int | get_data_length() | |
void | set_data_length(int length) | |
int | get_streaming_width() | |
void | set_streaming_width(int width) | |
void | get_byte_enable(byte[] p) | |
void | set_byte_enable(byte[] p) | |
int | get_byte_enable_length() | |
void | set_byte_enable_length(int length) | |
void | set_dmi_allowed(bit dmi) | |
bit | is_dmi_allowed() | |
uvm_tlm_response_status_e | get_response_status() | |
void | set_response_status(uvm_tlm_response_status_e status) | |
bit | is_response_ok() | |
bit | is_response_error() | |
string | get_response_string() | |
uvm_tlm_extension_base | set_extension(uvm_tlm_extension_base ext) | |
int | get_num_extensions() | |
uvm_tlm_extension_base | get_extension(uvm_tlm_extension_base ext_handle) | |
void | clear_extension(uvm_tlm_extension_base ext_handle) | |
void | clear_extensions() | |
void | pre_randomize() | Function: pre_randomize() Prepare this class instance for randomization |
void | post_randomize() | Function: post_randomize() Clean-up this class instance after randomization |
Extends: uvm_object
Class: uvm_tlm_extension_base
The class uvm_tlm_extension_base is the non-parameterized base class for all generic payload extensions. It includes the utility do_copy() and create(). The pure virtual function get_type_handle() allows you to get a unique handle that represents the derived type. This is implemented in derived classes.
This class is never used directly by users. The <uvm_tlm_extension> class is used instead.
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new |
uvm_tlm_extension_base | get_type_handle() | |
string | get_type_handle_name() | |
void | do_copy(uvm_object rhs) | |
uvm_object | create(string name) |
Extends: uvm_tlm_extension_base
| Type | Name | Description |
|---|---|---|
this_type | m_my_tlm_ext_type |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
this_type | ID() | |
uvm_tlm_extension_base | get_type_handle() | |
string | get_type_handle_name() | |
uvm_object | create(string name) |
| Type | Method | Description |
|---|---|---|
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
void | b_transport(T t, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, IMP imp) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | b_transport(T t, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | b_transport(T t, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
Class: uvm_tlm_b_target_socket_base
IS-A forward imp; has no backward path except via the payload contents.
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
Class: uvm_tlm_b_initiator_socket_base
IS-A forward port; has no backward path except via the payload contents
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | b_transport(T t, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
Class: uvm_tlm_nb_target_socket_base
IS-A forward imp; HAS-A backward port
| Type | Name | Description |
|---|---|---|
uvm_tlm_nb_transport_bw_port | bw_port | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
Class: uvm_tlm_nb_initiator_socket_base
IS-A forward port; HAS-A backward imp
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
Class: uvm_tlm_nb_passthrough_initiator_socket_base
IS-A forward port; HAS-A backward export
| Type | Name | Description |
|---|---|---|
uvm_tlm_nb_transport_bw_export | bw_export | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
Class: uvm_tlm_nb_passthrough_target_socket_base
IS-A forward export; HAS-A backward port
| Type | Name | Description |
|---|---|---|
uvm_tlm_nb_transport_bw_port | bw_port | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
Class: uvm_tlm_b_passthrough_initiator_socket_base
IS-A forward port
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | b_transport(T t, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
Class: uvm_tlm_b_passthrough_target_socket_base
IS-A forward export
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, int min_size, int max_size) | |
string | get_type_name() | |
void | b_transport(T t, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | connect(this_type provider) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | Function: new Construct a new instance of this socket |
void | connect(uvm_port_base provider) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
string | get_type_name() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, IMP imp) | Function: new Construct a new instance of this socket ~imp~ is a reference to the class implementing the b_transport() method. If not specified, it is assume to be the same as ~parent~. |
void | connect(uvm_port_base provider) | |
void | b_transport(T t, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
string | get_type_name() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
uvm_tlm_nb_transport_bw_imp | bw_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, IMP imp) | Function: new Construct a new instance of this socket ~imp~ is a reference to the class implementing the nb_transport_bw() method. If not specified, it is assume to be the same as ~parent~. |
void | connect(uvm_port_base provider) | Function: Connect Connect this socket to the specified <uvm_tlm_nb_target_socket> |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
string | get_type_name() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
IMP | m_imp | |
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list | |
uvm_tlm_nb_transport_bw_port | bw_port |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent, IMP imp) | Function: new Construct a new instance of this socket ~imp~ is a reference to the class implementing the nb_transport_fw() method. If not specified, it is assume to be the same as ~parent~. |
void | connect(uvm_port_base provider) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
string | get_type_name() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | connect(uvm_port_base provider) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
string | get_type_name() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
Class: uvm_tlm_b_passthrough_target_socket
IS-A forward export;
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | connect(uvm_port_base provider) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
string | get_type_name() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list | |
uvm_tlm_nb_transport_bw_export | bw_export |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | connect(uvm_port_base provider) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
string | get_type_name() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
int | m_if_mask | |
uvm_port_base | m_if | REMOVE |
int | m_def_index | |
uvm_port_component | m_comp | |
this_type[] | m_provided_by | |
this_type[] | m_provided_to | |
uvm_port_type_e | m_port_type | |
int | m_min_size | |
int | m_max_size | |
bit | m_resolved | |
this_type[] | m_imp_list | |
uvm_tlm_nb_transport_bw_port | bw_port |
| Type | Method | Description |
|---|---|---|
logic | new(string name, uvm_component parent) | |
void | connect(uvm_port_base provider) | |
uvm_tlm_sync_e | nb_transport_fw(T t, P p, uvm_tlm_time delay) | |
uvm_tlm_sync_e | nb_transport_bw(T t, P p, uvm_tlm_time delay) | |
void | b_transport(T t, uvm_tlm_time delay) | |
string | get_name() | |
string | get_full_name() | |
uvm_component | get_parent() | |
uvm_port_component_base | get_comp() | |
string | get_type_name() | |
int | max_size() | |
int | min_size() | |
bit | is_unbounded() | |
bit | is_port() | |
bit | is_export() | |
bit | is_imp() | |
int | size() | |
void | set_if(int index) | |
int | m_get_if_mask() | |
void | set_default_index(int index) | |
void | debug_connected_to(int level, int max_level) | |
void | debug_provided_to(int level, int max_level) | |
void | get_connected_to(uvm_port_list list) | |
void | get_provided_to(uvm_port_list list) | |
bit | m_check_relationship(this_type provider) | |
void | m_add_list(this_type provider) | |
void | resolve_bindings() | |
uvm_port_base | get_if(int index) |
| Type | Name | Description |
|---|---|---|
uvm_hdl_path_slice[] | slices | Variable: slices Array of individual slices, stored in most-to-least significant order |
| Type | Method | Description |
|---|---|---|
void | set(uvm_hdl_path_slice[] t) | Function: set Initialize the concatenation using an array literal |
void | add_slice(uvm_hdl_path_slice slice) | Function: add_slice Append the specified ~slice~ literal to the path concatenation |
void | add_path(string path, int offset, int size) | Function: add_path Append the specified ~path~ to the path concatenation, for the specified number of bits at the specified ~offset~. |
Extends: uvm_sequence_item
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_elem_kind_e | element_kind | Variable: element_kind Kind of element being accessed: REG, MEM, or FIELD. See <uvm_elem_kind_e>. |
uvm_object | element | Variable: element A handle to the RegModel model element associated with this transaction. Use <element_kind> to determine the type to cast to: <uvm_reg>, <uvm_mem>, or <uvm_reg_field>. |
uvm_access_e | kind | |
anonymous | value | |
uvm_reg_addr_t | offset | |
uvm_status_e | status | Variable: status The result of the transaction: IS_OK, HAS_X, or ERROR. See <uvm_status_e>. |
uvm_reg_map | local_map | Variable: local_map The local map used to obtain addresses. Users may customize address-translation using this map. Access to the sequencer and bus adapter can be obtained by getting this map's root map, then calling <uvm_reg_map::get_sequencer> and <uvm_reg_map::get_adapter>. |
uvm_reg_map | map | Variable: map The original map specified for the operation. The actual used may differ when a test or sequence written at the block level is reused at the system level. |
uvm_path_e | path | Variable: path The path being used: <UVM_FRONTDOOR> or <UVM_BACKDOOR>. |
uvm_sequence_base | parent | |
int | prior | Variable: prior The priority requested of this transfer, as defined by <uvm_sequence_base::start_item>. |
uvm_object | extension | |
string | bd_kind | Variable: bd_kind If path is UVM_BACKDOOR, this member specifies the abstraction kind for the backdoor access, e.g. "RTL" or "GATES". |
string | fname | Variable: fname The file name from where this transaction originated, if provided at the call site. |
int | lineno | Variable: lineno The file name from where this transaction originated, if provided at the call site. |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Create a new instance of this type, giving it the optional ~name~. |
string | convert2string() | |
void | do_copy(uvm_object rhs) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
bit | supports_byte_enable | |
bit | provides_responses | |
uvm_sequence_base | parent_sequence | |
uvm_reg_item | m_item |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
uvm_sequence_item | reg2bus(uvm_reg_bus_op rw) | |
void | bus2reg(uvm_sequence_item bus_item, uvm_reg_bus_op rw) | |
uvm_reg_item | get_item() | |
void | m_set_item(uvm_reg_item item) |
Extends: uvm_reg_adapter
| Type | Name | Description |
|---|---|---|
string | type_name |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
uvm_sequence_item | reg2bus(uvm_reg_bus_op rw) | |
void | bus2reg(uvm_sequence_item bus_item, uvm_reg_bus_op rw) |
| Type | Name | Description |
|---|---|---|
bit[] | addr | |
uvm_reg_item | reg_item |
Extends: uvm_component
| Type | Name | Description |
|---|---|---|
uvm_analysis_imp | bus_in | Variable: bus_in Observed bus transactions of type ~BUSTYPE~ are received from this port and processed. For each incoming transaction, the predictor will attempt to get the register or memory handle corresponding to the observed bus address. If there is a match, the predictor calls the register or memory's predict method, passing in the observed bus data. The register or memory mirror will be updated with this data, subject to its configured access behavior--RW, RO, WO, etc. The predictor will also convert the bus transaction to a generic <uvm_reg_item> and send it out the ~reg_ap~ analysis port. If the register is wider than the bus, the predictor will collect the multiple bus transactions needed to determine the value being read or written. |
uvm_analysis_port | reg_ap | Variable: reg_ap Analysis output port that publishes <uvm_reg_item> transactions converted from bus transactions received on ~bus_in~. |
uvm_reg_map | map | Variable: map The map used to convert a bus address to the corresponding register or memory handle. Must be configured before the run phase. |
uvm_reg_adapter | adapter | Variable: adapter The adapter used to convey the parameters of a bus operation in terms of a canonical <uvm_reg_bus_op> datum. The <uvm_reg_adapter> must be configured before the run phase. |
string | type_name | |
uvm_predict_s[] | m_pending |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
logic | new(string name, uvm_component parent) | Function: new Create a new instance of this type, giving it the optional ~name~ and ~parent~. |
string | get_type_name() | |
void | pre_predict(uvm_reg_item rw) | |
void | write(BUSTYPE tr) | |
void | check_phase(uvm_phase phase) |
| Type | Name | Description |
|---|---|---|
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
string | type_name | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | Function: new Create a new instance, giving it the optional ~name~. |
void | body() | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | put_response(uvm_sequence_item response_item) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
string | get_type_name() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) |
Class: uvm_reg_frontdoor
Facade class for register and memory frontdoor access.
User-defined frontdoor access sequence
Base class for user-defined access to register and memory reads and writes through a physical interface.
By default, different registers and memories are mapped to different addresses in the address space and are accessed via those exclusively through physical addresses.
The frontdoor allows access using a non-linear and/or non-mapped mechanism. Users can extend this class to provide the physical access to these registers.
| Type | Name | Description |
|---|---|---|
uvm_reg_item | rw_info | Variable: rw_info Holds information about the register being read or written |
uvm_sequencer_base | sequencer | Variable: sequencer Sequencer executing the operation |
string | fname | |
int | lineno | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
string | type_name | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new Constructor, new object given optional ~name~. |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object_registry | get_type() | |
uvm_object_wrapper | get_object_type() | |
string | get_type_name() | |
uvm_object | create(string name) | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | body() | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
Extends: uvm_callback
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | pre_write(uvm_reg_item rw) | |
void | post_write(uvm_reg_item rw) | |
void | pre_read(uvm_reg_item rw) | |
void | post_read(uvm_reg_item rw) | |
void | post_predict(uvm_reg_field fld, uvm_reg_data_t previous, uvm_reg_data_t value, uvm_predict_e kind, uvm_path_e path, uvm_reg_map map) | |
void | encode(uvm_reg_data_t[] data) | |
void | decode(uvm_reg_data_t[] data) |
Extends: uvm_reg_cbs
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_reg_read_only_cbs | m_me |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
void | pre_write(uvm_reg_item rw) | |
uvm_reg_read_only_cbs | get() | |
void | add(uvm_reg rg) | |
void | remove(uvm_reg rg) |
Extends: uvm_reg_cbs
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_reg_write_only_cbs | m_me |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
void | pre_read(uvm_reg_item rw) | |
uvm_reg_write_only_cbs | get() | |
void | add(uvm_reg rg) | |
void | remove(uvm_reg rg) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | fname | |
int | lineno | |
unknown[] | m_update_thread | |
string | type_name | |
bit | m_register_cb_uvm_reg_cbs |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | Function: new Create an instance of this class Create an instance of the user-defined backdoor class for the specified register or memory |
void | do_pre_read(uvm_reg_item rw) | |
void | do_post_read(uvm_reg_item rw) | |
void | do_pre_write(uvm_reg_item rw) | |
void | do_post_write(uvm_reg_item rw) | |
void | write(uvm_reg_item rw) | |
void | read(uvm_reg_item rw) | |
void | read_func(uvm_reg_item rw) | |
bit | is_auto_updated(uvm_reg_field field) | |
void | wait_for_change(uvm_object element) | |
void | start_update_thread(uvm_object element) | |
void | kill_update_thread(uvm_object element) | |
bit | has_update_threads() | |
void | pre_read(uvm_reg_item rw) | |
void | post_read(uvm_reg_item rw) | |
void | pre_write(uvm_reg_item rw) | |
void | post_write(uvm_reg_item rw) | |
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) |
Extends: uvm_object
CLASS: uvm_reg_field Field abstraction class
A field represents a set of bits that behave consistently as a single entity.
A field is contained within a single register, but may have different access policies depending on the address map use the access the register (thus the field).
| Type | Name | Description |
|---|---|---|
uvm_reg_data_t | value | Mirrored after randomize() |
uvm_reg_data_t | m_mirrored | What we think is in the HW |
uvm_reg_data_t | m_desired | Mirrored after set() |
string | m_access | |
uvm_reg | m_parent | |
int | m_lsb | |
int | m_size | |
bit | m_volatile | |
uvm_reg_data_t[] | m_reset | |
bit | m_written | |
bit | m_read_in_progress | |
bit | m_write_in_progress | |
string | m_fname | |
int | m_lineno | |
int | m_cover_on | |
bit | m_individually_accessible | |
uvm_check_e | m_check | |
int | m_max_size | |
bit[] | m_policy_names | |
string | type_name | |
bit | m_predefined | |
bit | m_register_cb_uvm_reg_cbs |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_reg_field | new(string name) | |
void | configure(uvm_reg parent, int size, int lsb_pos, string access, bit volatile, uvm_reg_data_t reset, bit has_reset, bit is_rand, bit individually_accessible) | |
string | get_full_name() | |
uvm_reg | get_parent() | |
uvm_reg | get_register() | |
int | get_lsb_pos() | |
int | get_n_bits() | |
int | get_max_size() | |
string | set_access(string mode) | |
bit | define_access(string name) | |
bit | m_predefine_policies() | |
string | get_access(uvm_reg_map map) | |
bit | is_known_access(uvm_reg_map map) | |
void | set_volatility(bit volatile) | |
bit | is_volatile() | |
void | set(uvm_reg_data_t value, string fname, int lineno) | |
uvm_reg_data_t | get(string fname, int lineno) | |
uvm_reg_data_t | get_mirrored_value(string fname, int lineno) | |
void | reset(string kind) | |
uvm_reg_data_t | get_reset(string kind) | |
bit | has_reset(string kind, bit delete) | |
void | set_reset(uvm_reg_data_t value, string kind) | |
bit | needs_update() | |
void | write(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | read(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | poke(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | peek(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | mirror(uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | set_compare(uvm_check_e check) | |
uvm_check_e | get_compare() | |
bit | is_indv_accessible(uvm_path_e path, uvm_reg_map local_map) | |
bit | predict(uvm_reg_data_t value, uvm_reg_byte_en_t be, uvm_predict_e kind, uvm_path_e path, uvm_reg_map map, string fname, int lineno) | |
uvm_reg_data_t | XpredictX(uvm_reg_data_t cur_val, uvm_reg_data_t wr_val, uvm_reg_map map) | |
uvm_reg_data_t | XupdateX() | |
bit | Xcheck_accessX(uvm_reg_item rw, uvm_reg_map_info map_info, string caller) | |
void | do_write(uvm_reg_item rw) | |
void | do_read(uvm_reg_item rw) | |
void | do_predict(uvm_reg_item rw, uvm_predict_e kind, uvm_reg_byte_en_t be) | |
void | pre_randomize() | |
void | post_randomize() | |
void | pre_write(uvm_reg_item rw) | |
void | post_write(uvm_reg_item rw) | |
void | pre_read(uvm_reg_item rw) | |
void | post_read(uvm_reg_item rw) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
uvm_object | clone() | |
void | do_copy(uvm_object rhs) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_pack(uvm_packer packer) | |
void | do_unpack(uvm_packer packer) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | type_name | |
bit | m_register_cb_uvm_vreg_field_cbs | |
uvm_vreg | parent | |
int | lsb | |
int | size | |
string | fname | |
int | lineno | |
bit | read_in_progress | |
bit | write_in_progress |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
uvm_vreg_field | new(string name) | |
void | configure(uvm_vreg parent, int size, int lsb_pos) | |
string | get_full_name() | |
uvm_vreg | get_parent() | |
uvm_vreg | get_register() | |
int | get_lsb_pos_in_register() | |
int | get_n_bits() | |
string | get_access(uvm_reg_map map) | |
void | write(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | read(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | poke(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | peek(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | pre_write(longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map) | |
void | post_write(longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status) | |
void | pre_read(longint idx, uvm_path_e path, uvm_reg_map map) | |
void | post_read(longint idx, uvm_reg_data_t rdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
uvm_object | clone() | |
void | do_copy(uvm_object rhs) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_pack(uvm_packer packer) | |
void | do_unpack(uvm_packer packer) |
Extends: uvm_callback
| Type | Name | Description |
|---|---|---|
string | fname | |
int | lineno |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | pre_write(uvm_vreg_field field, longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map) | |
void | post_write(uvm_vreg_field field, longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status) | |
void | pre_read(uvm_vreg_field field, longint idx, uvm_path_e path, uvm_reg_map map) | |
void | post_read(uvm_vreg_field field, longint idx, uvm_reg_data_t rdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status) |
Extends: uvm_object
CLASS: uvm_reg Register abstraction base class
A register represents a set of fields that are accessible as a single entity.
A register may be mapped to one or more address maps, each with different access rights and policy.
| Type | Name | Description |
|---|---|---|
bit | m_locked | |
uvm_reg_block | m_parent | |
uvm_reg_file | m_regfile_parent | |
int | m_n_bits | |
int | m_n_used_bits | |
bit[] | m_maps | |
uvm_reg_field[] | m_fields | Fields in LSB to MSB order |
int | m_has_cover | |
int | m_cover_on | |
anonymous | m_atomic | |
anonymous | m_process | |
string | m_fname | |
int | m_lineno | |
bit | m_read_in_progress | |
bit | m_write_in_progress | |
bit | m_update_in_progress | |
bit | m_is_busy | |
bit | m_is_locked_by_field | |
uvm_reg_backdoor | m_backdoor | |
int | m_max_size | |
uvm_object_string_pool | m_hdl_paths_pool | |
bit | m_register_cb_uvm_reg_cbs |
| Type | Method | Description |
|---|---|---|
uvm_reg | new(string name, int n_bits, int has_coverage) | |
void | configure(uvm_reg_block blk_parent, uvm_reg_file regfile_parent, string hdl_path) | |
void | set_offset(uvm_reg_map map, uvm_reg_addr_t offset, bit unmapped) | |
void | set_parent(uvm_reg_block blk_parent, uvm_reg_file regfile_parent) | |
void | add_field(uvm_reg_field field) | |
void | add_map(uvm_reg_map map) | |
void | Xlock_modelX() | |
string | get_full_name() | |
uvm_reg_block | get_parent() | |
uvm_reg_block | get_block() | |
uvm_reg_file | get_regfile() | |
int | get_n_maps() | |
bit | is_in_map(uvm_reg_map map) | |
void | get_maps(uvm_reg_map[] maps) | |
uvm_reg_map | get_local_map(uvm_reg_map map, string caller) | |
uvm_reg_map | get_default_map(string caller) | |
string | get_rights(uvm_reg_map map) | |
int | get_n_bits() | |
int | get_n_bytes() | |
int | get_max_size() | |
void | get_fields(uvm_reg_field[] fields) | |
uvm_reg_field | get_field_by_name(string name) | |
string | Xget_fields_accessX(uvm_reg_map map) | |
uvm_reg_addr_t | get_offset(uvm_reg_map map) | |
uvm_reg_addr_t | get_address(uvm_reg_map map) | |
int | get_addresses(uvm_reg_map map, uvm_reg_addr_t[] addr) | |
void | set(uvm_reg_data_t value, string fname, int lineno) | |
uvm_reg_data_t | get(string fname, int lineno) | |
uvm_reg_data_t | get_mirrored_value(string fname, int lineno) | |
bit | needs_update() | |
void | reset(string kind) | |
uvm_reg_data_t | get_reset(string kind) | |
bit | has_reset(string kind, bit delete) | |
void | set_reset(uvm_reg_data_t value, string kind) | |
void | write(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | read(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | poke(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | peek(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | update(uvm_status_e status, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror(uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
bit | predict(uvm_reg_data_t value, uvm_reg_byte_en_t be, uvm_predict_e kind, uvm_path_e path, uvm_reg_map map, string fname, int lineno) | |
bit | is_busy() | |
void | Xset_busyX(bit busy) | |
void | XreadX(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | XatomicX(bit on) | |
bit | Xcheck_accessX(uvm_reg_item rw, uvm_reg_map_info map_info, string caller) | |
bit | Xis_locked_by_fieldX() | |
bit | do_check(uvm_reg_data_t expected, uvm_reg_data_t actual, uvm_reg_map map) | |
void | do_write(uvm_reg_item rw) | |
void | do_read(uvm_reg_item rw) | |
void | do_predict(uvm_reg_item rw, uvm_predict_e kind, uvm_reg_byte_en_t be) | |
void | set_frontdoor(uvm_reg_frontdoor ftdr, uvm_reg_map map, string fname, int lineno) | |
uvm_reg_frontdoor | get_frontdoor(uvm_reg_map map) | |
void | set_backdoor(uvm_reg_backdoor bkdr, string fname, int lineno) | |
uvm_reg_backdoor | get_backdoor(bit inherited) | |
void | clear_hdl_path(string kind) | |
void | add_hdl_path(uvm_hdl_path_slice[] slices, string kind) | |
void | add_hdl_path_slice(string name, int offset, int size, bit first, string kind) | |
bit | has_hdl_path(string kind) | |
void | get_hdl_path(uvm_hdl_path_concat[] paths, string kind) | |
void | get_hdl_path_kinds(string[] kinds) | |
void | get_full_hdl_path(uvm_hdl_path_concat[] paths, string kind, string separator) | |
void | backdoor_read(uvm_reg_item rw) | |
void | backdoor_write(uvm_reg_item rw) | |
uvm_status_e | backdoor_read_func(uvm_reg_item rw) | |
void | backdoor_watch() | |
void | include_coverage(string scope, uvm_reg_cvr_t models, uvm_object accessor) | |
uvm_reg_cvr_t | build_coverage(uvm_reg_cvr_t models) | |
void | add_coverage(uvm_reg_cvr_t models) | |
bit | has_coverage(uvm_reg_cvr_t models) | |
uvm_reg_cvr_t | set_coverage(uvm_reg_cvr_t is_on) | |
bit | get_coverage(uvm_reg_cvr_t is_on) | |
void | sample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map) | |
void | sample_values() | |
void | XsampleX(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map) | |
void | pre_write(uvm_reg_item rw) | |
void | post_write(uvm_reg_item rw) | |
void | pre_read(uvm_reg_item rw) | |
void | post_read(uvm_reg_item rw) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
uvm_object | clone() | |
void | do_copy(uvm_object rhs) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_pack(uvm_packer packer) | |
void | do_unpack(uvm_packer packer) |
Extends: uvm_reg
| Type | Name | Description |
|---|---|---|
uvm_reg | m_idx | |
uvm_reg[] | m_tbl |
| Type | Method | Description |
|---|---|---|
logic | new(string name, int n_bits, int has_cover) | Function: new Create an instance of this class Should not be called directly, other than via super.new(). The value of ~n_bits~ must match the number of bits in the indirect register array. |
void | build() | |
void | configure(uvm_reg idx, uvm_reg[] reg_a, uvm_reg_block blk_parent, uvm_reg_file regfile_parent) | Function: configure Configure the indirect data register. The ~idx~ register specifies the index, in the ~reg_a~ register array, of the register to access. The ~idx~ must be written to first. A read or write operation to this register will subsequently read or write the indexed register in the register array. The number of bits in each register in the register array must be equal to ~n_bits~ of this register. See <uvm_reg::configure()> for the remaining arguments. |
void | add_map(uvm_reg_map map) | |
void | add_frontdoors(uvm_reg_map map) | |
void | do_predict(uvm_reg_item rw, uvm_predict_e kind, uvm_reg_byte_en_t be) | |
uvm_reg_map | get_local_map(uvm_reg_map map, string caller) | |
void | add_field(uvm_reg_field field) | |
void | set(uvm_reg_data_t value, string fname, int lineno) | |
uvm_reg_data_t | get(string fname, int lineno) | |
uvm_reg | get_indirect_reg(string fname, int lineno) | |
bit | needs_update() | |
void | write(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | read(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | poke(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | peek(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | update(uvm_status_e status, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror(uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) |
Extends: uvm_reg_frontdoor
| Type | Name | Description |
|---|---|---|
uvm_reg | m_addr_reg | |
uvm_reg | m_data_reg | |
int | m_idx |
| Type | Method | Description |
|---|---|---|
logic | new(uvm_reg addr_reg, int idx, uvm_reg data_reg) | |
void | body() |
Extends: uvm_reg
| Type | Name | Description |
|---|---|---|
uvm_reg_field | value | |
int | m_set_cnt | |
int | m_size | |
anonymous | fifo |
| Type | Method | Description |
|---|---|---|
logic | new(string name, int size, int n_bits, int has_cover) | Function: new Creates an instance of a FIFO register having ~size~ elements of ~n_bits~ each. |
void | build() | |
void | set_compare(uvm_check_e check) | Function: set_compare Sets the compare policy during a mirror (read) of the DUT FIFO. The DUT read value is checked against its mirror only when both the ~check~ argument in the <mirror()> call and the compare policy for the field is <UVM_CHECK>. |
int | size() | Function: size The number of entries currently in the FIFO. |
int | capacity() | |
void | set(uvm_reg_data_t value, string fname, int lineno) | |
void | update(uvm_status_e status, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
uvm_reg_data_t | get(string fname, int lineno) | |
void | do_predict(uvm_reg_item rw, uvm_predict_e kind, uvm_reg_byte_en_t be) | |
void | pre_write(uvm_reg_item rw) | |
void | pre_read(uvm_reg_item rw) | |
void | post_randomize() |
Extends: uvm_object
CLASS: uvm_reg_file Register file abstraction base class
A register file is a collection of register files and registers used to create regular repeated structures.
Register files are usually instantiated as arrays.
| Type | Name | Description |
|---|---|---|
uvm_reg_block | parent | |
uvm_reg_file | m_rf | |
string | default_hdl_path | |
uvm_object_string_pool | hdl_paths_pool |
| Type | Method | Description |
|---|---|---|
uvm_reg_file | new(string name) | |
void | configure(uvm_reg_block blk_parent, uvm_reg_file regfile_parent, string hdl_path) | |
string | get_full_name() | |
uvm_reg_block | get_parent() | |
uvm_reg_block | get_block() | |
uvm_reg_file | get_regfile() | |
void | clear_hdl_path(string kind) | |
void | add_hdl_path(string path, string kind) | |
bit | has_hdl_path(string kind) | |
void | get_hdl_path(string[] paths, string kind) | |
void | get_full_hdl_path(string[] paths, string kind, string separator) | |
void | set_default_hdl_path(string kind) | |
string | get_default_hdl_path() | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
uvm_object | clone() | |
void | do_copy(uvm_object rhs) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_pack(uvm_packer packer) | |
void | do_unpack(uvm_packer packer) |
| Type | Name | Description |
|---|---|---|
uvm_mem_mam_policy | default_alloc | Variable: default_alloc Region allocation policy This object is repeatedly randomized when allocating new regions. |
uvm_mem | memory | |
uvm_mem_mam_cfg | cfg | |
uvm_mem_region[] | in_use | |
int | for_each_idx | |
string | fname | |
int | lineno |
| Type | Method | Description |
|---|---|---|
uvm_mem_mam | new(string name, uvm_mem_mam_cfg cfg, uvm_mem mem) | |
uvm_mem_mam_cfg | reconfigure(uvm_mem_mam_cfg cfg) | |
uvm_mem_region | reserve_region(anonymous start_offset, int n_bytes, string fname, int lineno) | |
uvm_mem_region | request_region(int n_bytes, uvm_mem_mam_policy alloc, string fname, int lineno) | |
void | release_region(uvm_mem_region region) | |
void | release_all_regions() | |
string | convert2string() | |
uvm_mem_region | for_each(bit reset) | |
uvm_mem | get_memory() |
| Type | Name | Description |
|---|---|---|
bit[] | Xstart_offsetX | Can't be local since function |
bit[] | Xend_offsetX | calls not supported in constraints |
int | len | |
int | n_bytes | |
uvm_mem_mam | parent | |
string | fname | |
int | lineno | |
uvm_vreg | XvregX |
| Type | Method | Description |
|---|---|---|
uvm_mem_region | new(anonymous start_offset, anonymous end_offset, int len, int n_bytes, uvm_mem_mam parent) | |
bit[] | get_start_offset() | |
bit[] | get_end_offset() | |
int | get_len() | |
int | get_n_bytes() | |
void | release_region() | |
uvm_mem | get_memory() | |
uvm_vreg | get_virtual_registers() | |
void | write(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | read(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | burst_write(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t[] value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | burst_read(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t[] value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | poke(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | peek(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
string | convert2string() |
| Type | Name | Description |
|---|---|---|
int | len | variable: len Number of addresses required |
anonymous | start_offset | |
bit[] | min_offset | variable: min_offset Minimum address offset in the managed address space |
bit[] | max_offset | variable: max_offset Maximum address offset in the managed address space |
uvm_mem_region[] | in_use | variable: in_use Regions already allocated in the managed address space |
CLASS: uvm_mem_mam_cfg Specifies the memory managed by an instance of a <uvm_mem_mam> memory allocation manager class.
| Type | Name | Description |
|---|---|---|
int | n_bytes | |
anonymous | start_offset | |
anonymous | end_offset | |
alloc_mode_e | mode | |
locality_e | locality |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
bit | m_register_cb_uvm_vreg_cbs | |
bit | locked | |
uvm_reg_block | parent | |
int | n_bits | |
int | n_used_bits | |
uvm_vreg_field[] | fields | Fields in LSB to MSB order |
uvm_mem | mem | Where is it implemented? |
uvm_reg_addr_t | offset | Start of vreg0 |
int | incr | From start to start of next |
longint | size | number of vregs |
bit | is_static | |
uvm_mem_region | region | Not NULL if implemented via MAM |
anonymous | atomic | Field RMW operations must be atomic |
string | fname | |
int | lineno | |
bit | read_in_progress | |
bit | write_in_progress |
| Type | Method | Description |
|---|---|---|
uvm_vreg | new(string name, int n_bits) | |
void | configure(uvm_reg_block parent, uvm_mem mem, longint size, uvm_reg_addr_t offset, int incr) | |
bit | implement(longint n, uvm_mem mem, uvm_reg_addr_t offset, int incr) | |
uvm_mem_region | allocate(longint n, uvm_mem_mam mam, uvm_mem_mam_policy alloc) | |
uvm_mem_region | get_region() | |
void | release_region() | |
void | set_parent(uvm_reg_block parent) | |
void | Xlock_modelX() | |
void | add_field(uvm_vreg_field field) | |
void | XatomicX(bit on) | |
string | get_full_name() | |
uvm_reg_block | get_parent() | |
uvm_reg_block | get_block() | |
uvm_mem | get_memory() | |
int | get_n_maps() | |
bit | is_in_map(uvm_reg_map map) | |
void | get_maps(uvm_reg_map[] maps) | |
string | get_rights(uvm_reg_map map) | |
string | get_access(uvm_reg_map map) | |
int | get_size() | |
int | get_n_bytes() | |
int | get_n_memlocs() | |
int | get_incr() | |
void | get_fields(uvm_vreg_field[] fields) | |
uvm_vreg_field | get_field_by_name(string name) | |
uvm_reg_addr_t | get_offset_in_memory(longint idx) | |
uvm_reg_addr_t | get_address(longint idx, uvm_reg_map map) | |
void | write(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | read(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | poke(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | peek(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | reset(string kind) | |
void | pre_write(longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map) | |
void | post_write(longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status) | |
void | pre_read(longint idx, uvm_path_e path, uvm_reg_map map) | |
void | post_read(longint idx, uvm_reg_data_t rdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
uvm_object | clone() | |
void | do_copy(uvm_object rhs) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_pack(uvm_packer packer) | |
void | do_unpack(uvm_packer packer) |
Extends: uvm_callback
| Type | Name | Description |
|---|---|---|
string | fname | |
int | lineno |
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | pre_write(uvm_vreg rg, longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map) | |
void | post_write(uvm_vreg rg, longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status) | |
void | pre_read(uvm_vreg rg, longint idx, uvm_path_e path, uvm_reg_map map) | |
void | post_read(uvm_vreg rg, longint idx, uvm_reg_data_t rdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
bit | m_locked | |
bit | m_read_in_progress | |
bit | m_write_in_progress | |
string | m_access | |
longint | m_size | |
uvm_reg_block | m_parent | |
bit[] | m_maps | |
int | m_n_bits | |
uvm_reg_backdoor | m_backdoor | |
bit | m_is_powered_down | |
int | m_has_cover | |
int | m_cover_on | |
string | m_fname | |
int | m_lineno | |
bit[] | m_vregs | |
uvm_object_string_pool | m_hdl_paths_pool | |
int | m_max_size | |
uvm_mem_mam | mam | variable: mam Memory allocation manager Memory allocation manager for the memory corresponding to this abstraction class instance. Can be used to allocate regions of consecutive addresses of specific sizes, such as DMA buffers, or to locate virtual register array. |
bit | m_register_cb_uvm_reg_cbs |
| Type | Method | Description |
|---|---|---|
uvm_mem | new(string name, longint size, int n_bits, string access, int has_coverage) | |
void | configure(uvm_reg_block parent, string hdl_path) | |
void | set_offset(uvm_reg_map map, uvm_reg_addr_t offset, bit unmapped) | |
void | set_parent(uvm_reg_block parent) | |
void | add_map(uvm_reg_map map) | |
void | Xlock_modelX() | |
void | Xadd_vregX(uvm_vreg vreg) | |
void | Xdelete_vregX(uvm_vreg vreg) | |
string | get_full_name() | |
uvm_reg_block | get_parent() | |
uvm_reg_block | get_block() | |
int | get_n_maps() | |
bit | is_in_map(uvm_reg_map map) | |
void | get_maps(uvm_reg_map[] maps) | |
uvm_reg_map | get_local_map(uvm_reg_map map, string caller) | |
uvm_reg_map | get_default_map(string caller) | |
string | get_rights(uvm_reg_map map) | |
string | get_access(uvm_reg_map map) | |
longint | get_size() | |
int | get_n_bytes() | |
int | get_n_bits() | |
int | get_max_size() | |
void | get_virtual_registers(uvm_vreg[] regs) | |
void | get_virtual_fields(uvm_vreg_field[] fields) | |
uvm_vreg | get_vreg_by_name(string name) | |
uvm_vreg_field | get_vfield_by_name(string name) | |
uvm_vreg | get_vreg_by_offset(uvm_reg_addr_t offset, uvm_reg_map map) | |
uvm_reg_addr_t | get_offset(uvm_reg_addr_t offset, uvm_reg_map map) | |
uvm_reg_addr_t | get_address(uvm_reg_addr_t offset, uvm_reg_map map) | |
int | get_addresses(uvm_reg_addr_t offset, uvm_reg_map map, uvm_reg_addr_t[] addr) | |
void | write(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | read(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | burst_write(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t[] value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | burst_read(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t[] value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | poke(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
void | peek(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno) | |
bit | Xcheck_accessX(uvm_reg_item rw, uvm_reg_map_info map_info, string caller) | |
void | do_write(uvm_reg_item rw) | |
void | do_read(uvm_reg_item rw) | |
void | set_frontdoor(uvm_reg_frontdoor ftdr, uvm_reg_map map, string fname, int lineno) | |
uvm_reg_frontdoor | get_frontdoor(uvm_reg_map map) | |
void | set_backdoor(uvm_reg_backdoor bkdr, string fname, int lineno) | |
uvm_reg_backdoor | get_backdoor(bit inherited) | |
void | clear_hdl_path(string kind) | |
void | add_hdl_path(uvm_hdl_path_slice[] slices, string kind) | |
void | add_hdl_path_slice(string name, int offset, int size, bit first, string kind) | |
bit | has_hdl_path(string kind) | |
void | get_hdl_path(uvm_hdl_path_concat[] paths, string kind) | |
void | get_full_hdl_path(uvm_hdl_path_concat[] paths, string kind, string separator) | |
void | get_hdl_path_kinds(string[] kinds) | |
void | backdoor_read(uvm_reg_item rw) | |
void | backdoor_write(uvm_reg_item rw) | |
uvm_status_e | backdoor_read_func(uvm_reg_item rw) | |
void | pre_write(uvm_reg_item rw) | |
void | post_write(uvm_reg_item rw) | |
void | pre_read(uvm_reg_item rw) | |
void | post_read(uvm_reg_item rw) | |
uvm_reg_cvr_t | build_coverage(uvm_reg_cvr_t models) | |
void | add_coverage(uvm_reg_cvr_t models) | |
bit | has_coverage(uvm_reg_cvr_t models) | |
uvm_reg_cvr_t | set_coverage(uvm_reg_cvr_t is_on) | |
bit | get_coverage(uvm_reg_cvr_t is_on) | |
void | sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map map) | |
void | XsampleX(uvm_reg_addr_t addr, bit is_read, uvm_reg_map map) | |
void | do_print(uvm_printer printer) | |
string | convert2string() | |
uvm_object | clone() | |
void | do_copy(uvm_object rhs) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_pack(uvm_packer packer) | |
void | do_unpack(uvm_packer packer) |
| Type | Name | Description |
|---|---|---|
uvm_reg_addr_t | offset | |
string | rights | |
bit | unmapped | |
uvm_reg_addr_t[] | addr | |
uvm_reg_frontdoor | frontdoor | |
uvm_reg_map_addr_range | mem_range | |
bit | is_initialized | if set marks the uvm_reg_map_info as initialized, prevents using an uninitialized map (for instance if the model has not been locked accidently and the maps have not been computed before) |
Extends: uvm_object
Class: uvm_reg_transaction_order_policy
| Type | Method | Description |
|---|---|---|
logic | new(string name) | |
void | order(uvm_reg_bus_op[] q) |
Extends: uvm_object
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_reg_addr_t | m_base_addr | |
int | m_n_bytes | |
uvm_endianness_e | m_endian | |
bit | m_byte_addressing | |
uvm_object_wrapper | m_sequence_wrapper | |
uvm_reg_adapter | m_adapter | |
uvm_sequencer_base | m_sequencer | |
bit | m_auto_predict | |
bit | m_check_on_read | |
uvm_reg_block | m_parent | |
int | m_system_n_bytes | |
uvm_reg_map | m_parent_map | |
uvm_reg_addr_t[] | m_parent_maps | value=offset of this map at parent level |
uvm_reg_addr_t[] | m_submaps | value=offset of submap at this level |
string[] | m_submap_rights | value=rights of submap at this level |
uvm_reg_map_info[] | m_regs_info | |
uvm_reg_map_info[] | m_mems_info | |
uvm_reg[] | m_regs_by_offset | |
uvm_reg[] | m_regs_by_offset_wo | |
uvm_mem[] | m_mems_by_offset | |
uvm_reg_transaction_order_policy | policy | |
uvm_reg_map | m_backdoor |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
void | Xinit_address_mapX() | |
uvm_reg_map | backdoor() | |
uvm_reg_map | new(string name) | |
void | configure(uvm_reg_block parent, uvm_reg_addr_t base_addr, int n_bytes, uvm_endianness_e endian, bit byte_addressing) | |
void | add_reg(uvm_reg rg, uvm_reg_addr_t offset, string rights, bit unmapped, uvm_reg_frontdoor frontdoor) | |
void | add_mem(uvm_mem mem, uvm_reg_addr_t offset, string rights, bit unmapped, uvm_reg_frontdoor frontdoor) | |
void | add_submap(uvm_reg_map child_map, uvm_reg_addr_t offset) | |
void | set_sequencer(uvm_sequencer_base sequencer, uvm_reg_adapter adapter) | |
void | set_submap_offset(uvm_reg_map submap, uvm_reg_addr_t offset) | |
uvm_reg_addr_t | get_submap_offset(uvm_reg_map submap) | |
void | set_base_addr(uvm_reg_addr_t offset) | |
void | reset(string kind) | |
void | add_parent_map(uvm_reg_map parent_map, uvm_reg_addr_t offset) | |
void | Xverify_map_configX() | |
void | m_set_reg_offset(uvm_reg rg, uvm_reg_addr_t offset, bit unmapped) | |
void | m_set_mem_offset(uvm_mem mem, uvm_reg_addr_t offset, bit unmapped) | |
string | get_full_name() | |
uvm_reg_map | get_root_map() | |
uvm_reg_block | get_parent() | |
uvm_reg_map | get_parent_map() | |
uvm_reg_addr_t | get_base_addr(uvm_hier_e hier) | |
int | get_n_bytes(uvm_hier_e hier) | |
int | get_addr_unit_bytes() | |
uvm_endianness_e | get_endian(uvm_hier_e hier) | |
uvm_sequencer_base | get_sequencer(uvm_hier_e hier) | |
uvm_reg_adapter | get_adapter(uvm_hier_e hier) | |
void | get_submaps(uvm_reg_map[] maps, uvm_hier_e hier) | |
void | get_registers(uvm_reg[] regs, uvm_hier_e hier) | |
void | get_fields(uvm_reg_field[] fields, uvm_hier_e hier) | |
void | get_memories(uvm_mem[] mems, uvm_hier_e hier) | |
void | get_virtual_registers(uvm_vreg[] regs, uvm_hier_e hier) | |
void | get_virtual_fields(uvm_vreg_field[] fields, uvm_hier_e hier) | |
uvm_reg_map_info | get_reg_map_info(uvm_reg rg, bit error) | |
uvm_reg_map_info | get_mem_map_info(uvm_mem mem, bit error) | |
int | get_size() | |
int | get_physical_addresses(uvm_reg_addr_t base_addr, uvm_reg_addr_t mem_offset, int n_bytes, uvm_reg_addr_t[] addr) | |
uvm_reg | get_reg_by_offset(uvm_reg_addr_t offset, bit read) | |
uvm_mem | get_mem_by_offset(uvm_reg_addr_t offset) | |
void | set_auto_predict(bit on) | Function: set_auto_predict Sets the auto-predict mode for his map. When ~on~ is ~TRUE~, the register model will automatically update its mirror (what it thinks should be in the DUT) immediately after any bus read or write operation via this map. Before a <uvm_reg::write> or <uvm_reg::read> operation returns, the register's <uvm_reg::predict> method is called to update the mirrored value in the register. When ~on~ is ~FALSE~, bus reads and writes via this map do not automatically update the mirror. For real-time updates to the mirror in this mode, you connect a <uvm_reg_predictor> instance to the bus monitor. The predictor takes observed bus transactions from the bus monitor, looks up the associated <uvm_reg> register given the address, then calls that register's <uvm_reg::predict> method. While more complex, this mode will capture all register read/write activity, including that not directly descendant from calls to <uvm_reg::write> and <uvm_reg::read>. By default, auto-prediction is turned off. |
bit | get_auto_predict() | Function: get_auto_predict Gets the auto-predict mode setting for this map. |
void | set_check_on_read(bit on) | Function: set_check_on_read Sets the check-on-read mode for his map and all of its submaps. When ~on~ is ~TRUE~, the register model will automatically check any value read back from a register or field against the current value in its mirror and report any discrepancy. This effectively combines the functionality of the <uvm_reg::read()> and ~uvm_reg::mirror(UVM_CHECK)~ method. This mode is useful when the register model is used passively. When ~on~ is ~FALSE~, no check is made against the mirrored value. At the end of the read operation, the mirror value is updated based on the value that was read regardless of this mode setting. By default, auto-prediction is turned off. |
bit | get_check_on_read() | Function: get_check_on_read Gets the check-on-read mode setting for this map. |
void | do_bus_write(uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter) | |
void | do_bus_read(uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter) | |
void | do_write(uvm_reg_item rw) | |
void | do_read(uvm_reg_item rw) | |
void | Xget_bus_infoX(uvm_reg_item rw, uvm_reg_map_info map_info, int size, int lsb, int addr_skip) | |
string | convert2string() | |
uvm_object | clone() | |
void | do_print(uvm_printer printer) | |
void | do_copy(uvm_object rhs) | |
void | set_transaction_order_policy(uvm_reg_transaction_order_policy pol) | Function: set_transaction_order_policy set the transaction order policy |
uvm_reg_transaction_order_policy | get_transaction_order_policy() | Function: get_transaction_order_policy set the transaction order policy |
Extends: uvm_object
Class: uvm_reg_block
Block abstraction base class
A block represents a design hierarchy. It can contain registers, register files, memories and sub-blocks.
A block has one or more address maps, each corresponding to a physical interface on the block.
| Type | Name | Description |
|---|---|---|
uvm_reg_block | parent | |
bit[] | m_roots | |
int[] | blks | |
int[] | regs | |
int[] | vregs | |
int[] | mems | |
bit[] | maps | |
uvm_path_e | default_path | Variable: default_path Default access path for the registers and memories in this block. |
string | default_hdl_path | |
uvm_reg_backdoor | backdoor | |
uvm_object_string_pool | hdl_paths_pool | |
string[] | root_hdl_paths | |
bit | locked | |
int | has_cover | |
int | cover_on | |
string | fname | |
int | lineno | |
int | id | |
uvm_reg_map | default_map | Variable: default_map Default address map Default address map for this block, to be used when no address map is specified for a register operation and that register is accessible from more than one address map. It is also the implicit address map for a block with a single, unnamed address map because it has only one physical interface. |
| Type | Method | Description |
|---|---|---|
uvm_reg_block | new(string name, int has_coverage) | |
void | configure(uvm_reg_block parent, string hdl_path) | |
uvm_reg_map | create_map(string name, uvm_reg_addr_t base_addr, int n_bytes, uvm_endianness_e endian, bit byte_addressing) | |
bit | check_data_width(int width) | |
void | set_default_map(uvm_reg_map map) | |
uvm_reg_map | get_default_map() | |
void | set_parent(uvm_reg_block parent) | |
void | add_block(uvm_reg_block blk) | |
void | add_map(uvm_reg_map map) | |
void | add_reg(uvm_reg rg) | |
void | add_vreg(uvm_vreg vreg) | |
void | add_mem(uvm_mem mem) | |
void | lock_model() | |
bit | is_locked() | |
string | get_full_name() | |
uvm_reg_block | get_parent() | |
void | get_root_blocks(uvm_reg_block[] blks) | |
int | find_blocks(string name, uvm_reg_block[] blks, uvm_reg_block root, uvm_object accessor) | |
uvm_reg_block | find_block(string name, uvm_reg_block root, uvm_object accessor) | |
void | get_blocks(uvm_reg_block[] blks, uvm_hier_e hier) | |
void | get_maps(uvm_reg_map[] maps) | |
void | get_registers(uvm_reg[] regs, uvm_hier_e hier) | |
void | get_fields(uvm_reg_field[] fields, uvm_hier_e hier) | |
void | get_memories(uvm_mem[] mems, uvm_hier_e hier) | |
void | get_virtual_registers(uvm_vreg[] regs, uvm_hier_e hier) | |
void | get_virtual_fields(uvm_vreg_field[] fields, uvm_hier_e hier) | |
uvm_reg_block | get_block_by_name(string name) | |
uvm_reg_map | get_map_by_name(string name) | |
uvm_reg | get_reg_by_name(string name) | |
uvm_reg_field | get_field_by_name(string name) | |
uvm_mem | get_mem_by_name(string name) | |
uvm_vreg | get_vreg_by_name(string name) | |
uvm_vreg_field | get_vfield_by_name(string name) | |
uvm_reg_cvr_t | build_coverage(uvm_reg_cvr_t models) | |
void | add_coverage(uvm_reg_cvr_t models) | |
bit | has_coverage(uvm_reg_cvr_t models) | |
uvm_reg_cvr_t | set_coverage(uvm_reg_cvr_t is_on) | |
bit | get_coverage(uvm_reg_cvr_t is_on) | |
void | sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map map) | |
void | sample_values() | |
void | XsampleX(uvm_reg_addr_t addr, bit is_read, uvm_reg_map map) | |
uvm_path_e | get_default_path() | |
void | reset(string kind) | |
bit | needs_update() | |
void | update(uvm_status_e status, uvm_path_e path, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror(uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | write_reg_by_name(uvm_status_e status, string name, uvm_reg_data_t data, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg_by_name(uvm_status_e status, string name, uvm_reg_data_t data, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem_by_name(uvm_status_e status, string name, uvm_reg_addr_t offset, uvm_reg_data_t data, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem_by_name(uvm_status_e status, string name, uvm_reg_addr_t offset, uvm_reg_data_t data, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno) | |
void | readmemh(string filename) | |
void | writememh(string filename) | |
uvm_reg_backdoor | get_backdoor(bit inherited) | |
void | set_backdoor(uvm_reg_backdoor bkdr, string fname, int lineno) | |
void | clear_hdl_path(string kind) | |
void | add_hdl_path(string path, string kind) | |
bit | has_hdl_path(string kind) | |
void | get_hdl_path(string[] paths, string kind) | |
void | get_full_hdl_path(string[] paths, string kind, string separator) | |
void | set_default_hdl_path(string kind) | |
string | get_default_hdl_path() | |
void | set_hdl_path_root(string path, string kind) | |
bit | is_hdl_path_root(string kind) | |
void | do_print(uvm_printer printer) | |
void | do_copy(uvm_object rhs) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
void | do_pack(uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
string | convert2string() | |
uvm_object | clone() | |
void | Xinit_address_mapsX() |
| Type | Name | Description |
|---|---|---|
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | do_block(uvm_reg_block blk) | |
void | reset_blk(uvm_reg_block blk) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
uvm_reg | rg | Variable: rg The register to be tested |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | bash_kth_bit(uvm_reg rg, int k, string mode, uvm_reg_map map, uvm_reg_data_t dc_mask) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
uvm_reg_single_bit_bash_seq | reg_seq | |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | do_block(uvm_reg_block blk) | |
void | reset_blk(uvm_reg_block blk) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
string | type_name | |
uvm_mem | mem | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
uvm_mem_single_walk_seq | mem_seq | |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | do_block(uvm_reg_block blk) | |
void | reset_blk(uvm_reg_block blk) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
uvm_mem | mem | Variable: mem The memory to be tested |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
uvm_mem_single_access_seq | mem_seq | |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | do_block(uvm_reg_block blk) | |
void | reset_blk(uvm_reg_block blk) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
uvm_reg | rg | Variable: rg The register to be tested |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
uvm_reg_single_access_seq | reg_seq | |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | do_block(uvm_reg_block blk) | |
void | reset_blk(uvm_reg_block blk) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | reset_blk(uvm_reg_block blk) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
uvm_reg | rg | Variable: rg The register to be tested |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
uvm_mem | mem | variable: mem The memory to be tested |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
uvm_reg_shared_access_seq | reg_seq | |
uvm_mem_shared_access_seq | mem_seq | |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | do_block(uvm_reg_block blk) | |
void | reset_blk(uvm_reg_block blk) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
string | type_name | |
bit[] | tests | Variable: tests The pre-defined test sequences to be executed. |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
| Type | Name | Description |
|---|---|---|
string[] | abstractions | Variable: abstractions If set, check the HDL paths for the specified design abstractions. If empty, check the HDL path for the default design abstraction, as specified with <uvm_reg_block::set_default_hdl_path()> |
string | type_name | |
bit | use_uvm_seeding | |
string | m_leaf_name | |
int | m_inst_id | |
int | m_inst_count | |
uvm_status_container | __m_uvm_status_container | |
uvm_object[] | uvm_global_copy_map | |
uvm_event_pool | events | |
uvm_event | begin_event | Variable: begin_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. |
uvm_event | end_event | Variable: end_event A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended. For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API. | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ... |
integer | m_transaction_id | |
time | begin_time | |
time | end_time | |
time | accept_time | |
uvm_component | initiator | |
uvm_tr_stream | stream_handle | |
uvm_recorder | tr_recorder | |
int | m_sequence_id | |
bit | m_use_sequence_info | |
int | m_depth | |
uvm_sequencer_base | m_sequencer | |
uvm_sequence_base | m_parent_sequence | |
bit | issued1 | |
bit | issued2 | |
bit | print_sequence_info | |
uvm_sequence_state | m_sequence_state | |
int | m_next_transaction_id | |
int | m_priority | |
uvm_recorder | m_tr_recorder | |
int | m_wait_for_grant_semaphore | |
int[] | m_sqr_seq_ids | |
bit[] | children_array | |
uvm_sequence_item[] | response_queue | |
int | response_queue_depth | |
bit | response_queue_error_report_disabled | |
bit | do_not_randomize | Variable: do_not_randomize If set, prevents the sequence from being randomized before being executed
by the |
unknown | m_sequence_process | |
bit | m_use_response_handler | |
bit | is_rel_default | |
bit | wait_rel_default | |
uvm_get_to_lock_dap | m_automatic_phase_objection_dap | |
uvm_get_to_lock_dap | m_starting_phase_dap | |
uvm_phase | starting_phase | DEPRECATED!! Use get/set_starting_phase accessors instead! |
uvm_phase | m_set_starting_phase | Value set via set_starting_phase |
bit | m_warn_deprecated_set | Ensures we only warn once per sequence |
int | seq_kind | |
uvm_sequencer_param_base | param_sequencer | |
uvm_reg_item | req | Variable: req The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_sequence_item | rsp | Variable: rsp The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field. |
uvm_reg_block | model | Variable: model Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
uvm_reg_adapter | adapter | Variable: adapter Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
uvm_sequencer | reg_seqr | Variable: reg_seqr Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
seq_parent_e | parent_select | |
uvm_sequence_base | upstream_parent |
| Type | Method | Description |
|---|---|---|
type_id | get_type() | |
uvm_object_wrapper | get_object_type() | |
uvm_object | create(string name) | |
string | get_type_name() | |
void | __m_uvm_field_automation(uvm_object tmp_data__, int what__, string str__) | |
logic | new(string name) | |
void | body() | |
void | reset_blk(uvm_reg_block blk) | |
void | do_block(uvm_reg_block blk, string kind) | |
void | check_reg(uvm_reg r, string kind) | |
void | check_mem(uvm_mem m, string kind) | |
void | reseed() | |
void | set_name(string name) | |
string | get_name() | |
string | get_full_name() | |
int | get_inst_id() | |
int | get_inst_count() | |
uvm_object | clone() | |
void | print(uvm_printer printer) | |
string | sprint(uvm_printer printer) | |
void | do_print(uvm_printer printer) | Function- do_print |
string | convert2string() | |
void | record(uvm_recorder recorder) | |
void | do_record(uvm_recorder recorder) | |
void | copy(uvm_object rhs) | |
void | do_copy(uvm_object rhs) | |
bit | compare(uvm_object rhs, uvm_comparer comparer) | |
bit | do_compare(uvm_object rhs, uvm_comparer comparer) | |
int | pack(bit[] bitstream, uvm_packer packer) | |
int | pack_bytes(byte[] bytestream, uvm_packer packer) | |
int | pack_ints(int[] intstream, uvm_packer packer) | |
void | do_pack(uvm_packer packer) | |
int | unpack(bit[] bitstream, uvm_packer packer) | |
int | unpack_bytes(byte[] bytestream, uvm_packer packer) | |
int | unpack_ints(int[] intstream, uvm_packer packer) | |
void | do_unpack(uvm_packer packer) | |
void | set_int_local(string field_name, uvm_bitstream_t value, bit recurse) | |
void | set_string_local(string field_name, string value, bit recurse) | |
void | set_object_local(string field_name, uvm_object value, bit clone, bit recurse) | |
void | m_pack(uvm_packer packer) | |
void | m_unpack_pre(uvm_packer packer) | |
void | m_unpack_post(uvm_packer packer) | |
uvm_report_object | m_get_report_object() | |
void | accept_tr(time accept_time) | |
void | do_accept_tr() | |
integer | begin_tr(time begin_time) | |
integer | begin_child_tr(time begin_time, integer parent_handle) | |
void | do_begin_tr() | |
void | end_tr(time end_time, bit free_handle) | |
void | do_end_tr() | |
integer | get_tr_handle() | |
void | disable_recording() | |
void | enable_recording(uvm_tr_stream stream) | |
bit | is_recording_enabled() | |
bit | is_active() | |
uvm_event_pool | get_event_pool() | |
void | set_initiator(uvm_component initiator) | |
uvm_component | get_initiator() | |
time | get_accept_time() | |
time | get_begin_time() | |
time | get_end_time() | |
void | set_transaction_id(integer id) | |
integer | get_transaction_id() | |
integer | m_begin_tr(time begin_time, integer parent_handle) | |
void | set_sequence_id(int id) | |
int | get_sequence_id() | |
void | set_item_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer) | |
void | set_use_sequence_info(bit value) | |
bit | get_use_sequence_info() | |
void | set_id_info(uvm_sequence_item item) | |
void | set_sequencer(uvm_sequencer_base sequencer) | |
uvm_sequencer_base | get_sequencer() | |
void | set_parent_sequence(uvm_sequence_base parent) | |
uvm_sequence_base | get_parent_sequence() | |
void | set_depth(int value) | |
int | get_depth() | |
bit | is_item() | |
string | get_root_sequence_name() | |
void | m_set_p_sequencer() | |
uvm_sequence_base | get_root_sequence() | |
string | get_sequence_path() | |
uvm_report_object | uvm_get_report_object() | |
int | uvm_report_enabled(int verbosity, uvm_severity severity, string id) | |
void | uvm_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_report_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked) | |
void | uvm_process_report_message(uvm_report_message report_message) | |
uvm_sequence_state_enum | get_sequence_state() | |
void | wait_for_sequence_state(int state_mask) | |
void | start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post) | |
void | pre_start() | |
void | pre_body() | |
void | pre_do(bit is_item) | |
void | mid_do(uvm_sequence_item this_item) | |
void | post_do(uvm_sequence_item this_item) | |
void | post_body() | |
void | post_start() | |
void | m_init_phase_daps(bit create) | Function- m_init_phase_daps Either creates or renames DAPS |
uvm_phase | get_starting_phase() | Function: get_starting_phase Returns the 'starting phase'. If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information. Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_starting_phase(uvm_phase phase) | Function: set_starting_phase Sets the 'starting phase'. Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again. |
void | set_automatic_phase_objection(bit value) | Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit. The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically. For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer); Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again. NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped! |
bit | get_automatic_phase_objection() | Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit. If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called. |
void | m_safe_raise_starting_phase(string description, int count) | m_safe_raise_starting_phase |
void | m_safe_drop_starting_phase(string description, int count) | m_safe_drop_starting_phase |
void | set_priority(int value) | |
int | get_priority() | |
bit | is_relevant() | |
void | wait_for_relevant() | |
void | lock(uvm_sequencer_base sequencer) | |
void | grab(uvm_sequencer_base sequencer) | |
void | unlock(uvm_sequencer_base sequencer) | |
void | ungrab(uvm_sequencer_base sequencer) | |
bit | is_blocked() | |
bit | has_lock() | |
void | kill() | |
void | do_kill() | |
void | m_kill() | |
uvm_sequence_item | create_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name) | |
void | start_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer) | |
void | finish_item(uvm_sequence_item item, int set_priority) | |
void | wait_for_grant(int item_priority, bit lock_request) | |
void | send_request(uvm_sequence_item request, bit rerandomize) | |
void | wait_for_item_done(int transaction_id) | |
void | use_response_handler(bit enable) | |
bit | get_use_response_handler() | |
void | response_handler(uvm_sequence_item response) | |
void | set_response_queue_error_report_disabled(bit value) | |
bit | get_response_queue_error_report_disabled() | |
void | set_response_queue_depth(int value) | |
int | get_response_queue_depth() | |
void | clear_response_queue() | |
void | put_base_response(uvm_sequence_item response) | |
void | put_response(uvm_sequence_item response_item) | |
void | get_base_response(uvm_sequence_item response, int transaction_id) | |
int | num_sequences() | |
int | get_seq_kind(string type_name) | |
uvm_sequence_base | get_sequence(int req_kind) | |
void | do_sequence_kind(int req_kind) | |
uvm_sequence_base | get_sequence_by_name(string seq_name) | |
void | create_and_start_sequence_by_name(string seq_name) | |
int | m_get_sqr_sequence_id(int sequencer_id, bit update_sequence_id) | |
void | m_set_sqr_sequence_id(int sequencer_id, int sequence_id) | |
uvm_reg_item | get_current_item() | |
void | get_response(RSP response, int transaction_id) | |
void | do_reg_item(uvm_reg_item rw) | |
void | write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno) | |
void | poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) | |
void | peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno) |
This design unit is implemented in xbar_main.sv
This file depends on: tlul_fifo_async.sv, tl_main_pkg.sv, tlul_socket_m1.sv, tlul_pkg.sv, lc_ctrl_pkg.sv, tlul_socket_1n.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_main_i | in | logic | |
| clk_fixed_i | in | logic | |
| rst_main_ni | in | logic | |
| rst_fixed_ni | in | logic | |
| tl_corei_i | in | tl_h2d_t | Host interfaces |
| tl_corei_o | out | tl_d2h_t | |
| tl_cored_i | in | tl_h2d_t | |
| tl_cored_o | out | tl_d2h_t | |
| tl_dm_sba_i | in | tl_h2d_t | |
| tl_dm_sba_o | out | tl_d2h_t | |
| tl_rom_o | out | tl_h2d_t | Device interfaces |
| tl_rom_i | in | tl_d2h_t | |
| tl_debug_mem_o | out | tl_h2d_t | |
| tl_debug_mem_i | in | tl_d2h_t | |
| tl_ram_main_o | out | tl_h2d_t | |
| tl_ram_main_i | in | tl_d2h_t | |
| tl_eflash_o | out | tl_h2d_t | |
| tl_eflash_i | in | tl_d2h_t | |
| tl_peri_o | out | tl_h2d_t | |
| tl_peri_i | in | tl_d2h_t | |
| tl_flash_ctrl_o | out | tl_h2d_t | |
| tl_flash_ctrl_i | in | tl_d2h_t | |
| tl_hmac_o | out | tl_h2d_t | |
| tl_hmac_i | in | tl_d2h_t | |
| tl_kmac_o | out | tl_h2d_t | |
| tl_kmac_i | in | tl_d2h_t | |
| tl_aes_o | out | tl_h2d_t | |
| tl_aes_i | in | tl_d2h_t | |
| tl_entropy_src_o | out | tl_h2d_t | |
| tl_entropy_src_i | in | tl_d2h_t | |
| tl_csrng_o | out | tl_h2d_t | |
| tl_csrng_i | in | tl_d2h_t | |
| tl_edn0_o | out | tl_h2d_t | |
| tl_edn0_i | in | tl_d2h_t | |
| tl_edn1_o | out | tl_h2d_t | |
| tl_edn1_i | in | tl_d2h_t | |
| tl_rv_plic_o | out | tl_h2d_t | |
| tl_rv_plic_i | in | tl_d2h_t | |
| tl_otbn_o | out | tl_h2d_t | |
| tl_otbn_i | in | tl_d2h_t | |
| tl_keymgr_o | out | tl_h2d_t | |
| tl_keymgr_i | in | tl_d2h_t | |
| tl_sram_ctrl_main_o | out | tl_h2d_t | |
| tl_sram_ctrl_main_i | in | tl_d2h_t | |
| scanmode_i | in | lc_tx_t |
Instantiation phase
This design unit is implemented in xbar_peri.sv
This file depends on: tlul_pkg.sv, lc_ctrl_pkg.sv, tlul_socket_1n.sv, tl_peri_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_peri_i | in | logic | |
| rst_peri_ni | in | logic | |
| tl_main_i | in | tl_h2d_t | Host interfaces |
| tl_main_o | out | tl_d2h_t | |
| tl_uart0_o | out | tl_h2d_t | Device interfaces |
| tl_uart0_i | in | tl_d2h_t | |
| tl_uart1_o | out | tl_h2d_t | |
| tl_uart1_i | in | tl_d2h_t | |
| tl_uart2_o | out | tl_h2d_t | |
| tl_uart2_i | in | tl_d2h_t | |
| tl_uart3_o | out | tl_h2d_t | |
| tl_uart3_i | in | tl_d2h_t | |
| tl_i2c0_o | out | tl_h2d_t | |
| tl_i2c0_i | in | tl_d2h_t | |
| tl_i2c1_o | out | tl_h2d_t | |
| tl_i2c1_i | in | tl_d2h_t | |
| tl_i2c2_o | out | tl_h2d_t | |
| tl_i2c2_i | in | tl_d2h_t | |
| tl_pattgen_o | out | tl_h2d_t | |
| tl_pattgen_i | in | tl_d2h_t | |
| tl_gpio_o | out | tl_h2d_t | |
| tl_gpio_i | in | tl_d2h_t | |
| tl_spi_device_o | out | tl_h2d_t | |
| tl_spi_device_i | in | tl_d2h_t | |
| tl_spi_host0_o | out | tl_h2d_t | |
| tl_spi_host0_i | in | tl_d2h_t | |
| tl_spi_host1_o | out | tl_h2d_t | |
| tl_spi_host1_i | in | tl_d2h_t | |
| tl_rv_timer_o | out | tl_h2d_t | |
| tl_rv_timer_i | in | tl_d2h_t | |
| tl_usbdev_o | out | tl_h2d_t | |
| tl_usbdev_i | in | tl_d2h_t | |
| tl_pwrmgr_aon_o | out | tl_h2d_t | |
| tl_pwrmgr_aon_i | in | tl_d2h_t | |
| tl_rstmgr_aon_o | out | tl_h2d_t | |
| tl_rstmgr_aon_i | in | tl_d2h_t | |
| tl_clkmgr_aon_o | out | tl_h2d_t | |
| tl_clkmgr_aon_i | in | tl_d2h_t | |
| tl_pinmux_aon_o | out | tl_h2d_t | |
| tl_pinmux_aon_i | in | tl_d2h_t | |
| tl_ram_ret_aon_o | out | tl_h2d_t | |
| tl_ram_ret_aon_i | in | tl_d2h_t | |
| tl_otp_ctrl_o | out | tl_h2d_t | |
| tl_otp_ctrl_i | in | tl_d2h_t | |
| tl_lc_ctrl_o | out | tl_h2d_t | |
| tl_lc_ctrl_i | in | tl_d2h_t | |
| tl_sensor_ctrl_aon_o | out | tl_h2d_t | |
| tl_sensor_ctrl_aon_i | in | tl_d2h_t | |
| tl_alert_handler_o | out | tl_h2d_t | |
| tl_alert_handler_i | in | tl_d2h_t | |
| tl_sram_ctrl_ret_aon_o | out | tl_h2d_t | |
| tl_sram_ctrl_ret_aon_i | in | tl_d2h_t | |
| tl_aon_timer_aon_o | out | tl_h2d_t | |
| tl_aon_timer_aon_i | in | tl_d2h_t | |
| tl_ast_wrapper_o | out | tl_h2d_t | |
| tl_ast_wrapper_i | in | tl_d2h_t | |
| scanmode_i | in | lc_tx_t |
Instantiation phase
This design unit is implemented in aes_core.sv
This file depends on: aes_control.sv, aes_sel_buf_chk.sv, prim_subreg_shadow.sv, uvm_pkg.sv, aes_prng_clearing.sv, aes_cipher_core.sv, aes_pkg.sv, aes_ctr.sv, aes_reg_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AES192Enable | bit | 1 | |
| Masking | bit | 0 | |
| SBoxImpl | sbox_impl_e | SBoxImplLut | |
| SecStartTriggerDelay | int | 0 | |
| SecAllowForcingMasks | bit | 0 | |
| NumShares | int | Masking ? 2 : 1 | derived parameter |
| RndCnstClearingLfsrSeed | clearing_lfsr_seed_t | RndCnstClearingLfsrSeedDefault | |
| RndCnstClearingLfsrPerm | clearing_lfsr_perm_t | RndCnstClearingLfsrPermDefault | |
| RndCnstMaskingLfsrSeed | masking_lfsr_seed_t | RndCnstMaskingLfsrSeedDefault | |
| RndCnstMskgChunkLfsrPerm | mskg_chunk_lfsr_perm_t | RndCnstMskgChunkLfsrPermDefault | |
| NumChunks | int | 128/WidthPRDClearing | Generate clearing signals of appropriate widths. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| entropy_clearing_req_o | out | logic | Entropy request interfaces for clearing and masking PRNGs |
| entropy_clearing_ack_i | in | logic | |
| entropy_clearing_i | in | [WidthPRDClearing-1:0] logic | |
| entropy_masking_req_o | out | logic | |
| entropy_masking_ack_i | in | logic | |
| entropy_masking_i | in | [WidthPRDMasking-1:0] logic | |
| alert_recov_o | out | logic | Alerts |
| alert_fatal_o | out | logic | |
| reg2hw | in | aes_reg2hw_t | Bus Interface |
| hw2reg | out | aes_hw2reg_t |
The clearing PRNG provides pseudo-random data for register clearing purposes.
Cipher core
Shadowed register primitve
Control
This design unit is implemented in aes_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, aes_reg_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 7 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | aes_reg2hw_t | Write |
| hw2reg | in | aes_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Frecov_ctrl_update_err: 0:0
Ffatal_fault: 1:1
Foperation: 0:0
Fmode: 6:1
Fkey_len: 9:7
Fmanual_operation: 10:10
Fforce_zero_masks: 11:11
Fstart: 0:0
Fkey_iv_data_in_clear: 1:1
Fdata_out_clear: 2:2
Fprng_reseed: 3:3
Fidle: 0:0
Fstall: 1:1
Foutput_lost: 2:2
Foutput_valid: 3:3
Finput_ready: 4:4
Falert_recov_ctrl_update_err: 5:5
Falert_fatal_fault: 6:6
This design unit is implemented in alert_handler_accu.sv
This file depends on: uvm_pkg.sv, alert_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| class_en_i | in | logic | class enable |
| clr_i | in | logic | clear the accumulator |
| class_trig_i | in | logic | increments the accu |
| thresh_i | in | [AccuCntDw-1:0] logic | escalation trigger threshold |
| accu_cnt_o | out | [AccuCntDw-1:0] logic | output of current accu value |
| accu_trig_o | out | logic | escalation trigger output |
This design unit is implemented in alert_handler_class.sv
This file depends on: alert_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| alert_trig_i | in | [NAlerts-1:0] logic | alert trigger |
| loc_alert_trig_i | in | [N_LOC_ALERT-1:0] logic | alert trigger |
| alert_en_i | in | [NAlerts-1:0] logic | alert enable |
| loc_alert_en_i | in | [N_LOC_ALERT-1:0] logic | alert enable |
| alert_class_i | in | [CLASS_DW-1:0] [NAlerts-1:0] logic | class assignment |
| loc_alert_class_i | in | [CLASS_DW-1:0] [N_LOC_ALERT-1:0] logic | class assignment |
| alert_cause_o | out | [NAlerts-1:0] logic | alert cause |
| loc_alert_cause_o | out | [N_LOC_ALERT-1:0] logic | alert cause |
| class_trig_o | out | [N_CLASSES-1:0] logic | class triggered |
This design unit is implemented in alert_handler_esc_timer.sv
This file depends on: uvm_pkg.sv, alert_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| en_i | in | logic | enables timeout/escalation |
| clr_i | in | logic | aborts escalation |
| accum_trig_i | in | logic | this will trigger escalation |
| timeout_en_i | in | logic | enables timeout |
| timeout_cyc_i | in | [EscCntDw-1:0] logic | interrupt timeout. 0 = disabled |
| esc_en_i | in | [N_ESC_SEV-1:0] logic | escalation signal enables |
| esc_map_i | in | [PHASE_DW-1:0] [N_ESC_SEV-1:0] logic | escalation signal / phase map |
| phase_cyc_i | in | [EscCntDw-1:0] [N_PHASES-1:0] logic | cycle counts of individual phases |
| esc_trig_o | out | logic | asserted if escalation triggers |
| esc_cnt_o | out | [EscCntDw-1:0] logic | current timeout / escalation count |
| esc_sig_req_o | out | [N_ESC_SEV-1:0] logic | escalation signal outputs |
| esc_state_o | out | cstate_e | current state output 000: idle, 001: irq timeout counting 100: phase0, 101: phase1, 110: phase2, 111: phase3 |
This design unit is implemented in alert_handler_ping_timer.sv
This file depends on: uvm_pkg.sv, prim_lfsr.sv, alert_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RndCnstLfsrSeed | lfsr_seed_t | RndCnstLfsrSeedDefault | Compile time random constants, to be overriden by topgen. |
| RndCnstLfsrPerm | lfsr_perm_t | RndCnstLfsrPermDefault | |
| MaxLenSVA | bit | 1'b1 | Enable this for DV, disable this for long LFSRs in FPV |
| LockupSVA | bit | 1'b1 | Can be disabled in cases where entropy inputs are unused in order to not distort coverage (the SVA will be unreachable in such cases) |
| NModsToPing | int | NAlerts + N_ESC_SEV | |
| IdDw | int | $clog2(NModsToPing) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| entropy_i | in | logic | from TRNG |
| en_i | in | logic | enable ping testing |
| alert_en_i | in | [NAlerts-1:0] logic | determines which alerts to ping |
| ping_timeout_cyc_i | in | [PING_CNT_DW-1:0] logic | timeout in cycles |
| wait_cyc_mask_i | in | [PING_CNT_DW-1:0] logic | wait cycles mask |
| alert_ping_req_o | out | [NAlerts-1:0] logic | request to alert receivers |
| esc_ping_req_o | out | [N_ESC_SEV-1:0] logic | enable to esc senders |
| alert_ping_ok_i | in | [NAlerts-1:0] logic | response from alert receivers |
| esc_ping_ok_i | in | [N_ESC_SEV-1:0] logic | response from esc senders |
| alert_ping_fail_o | out | logic | any of the alert receivers failed |
| esc_ping_fail_o | out | logic | any of the esc senders failed |
This design unit is implemented in alert_handler_reg_pkg.sv
This design unit is implemented in alert_handler_reg_wrap.sv
This file depends on: alert_handler_reg_pkg.sv, alert_pkg.sv, prim_intr_hw.sv, tlul_pkg.sv, alert_handler_reg_top.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Bus Interface (device) |
| tl_o | out | tl_d2h_t | |
| irq_o | out | [N_CLASSES-1:0] logic | interrupt |
| crashdump_o | out | alert_crashdump_t | State information for HW crashdump |
| hw2reg_wrap | in | hw2reg_wrap_t | hw2reg |
| reg2hw_wrap | out | reg2hw_wrap_t | reg2hw |
This design unit is implemented in aon_osc.sv
of aon_osc
| Name | Type | Default Value | Description |
|---|---|---|---|
| AON_EN_RDLY | time | 5us | |
| AonClkPeriod | time | 5000ns | 5000ns (200Khz) |
| Name | Direction | Type | Description |
|---|---|---|---|
| vcore_pok_h_i | in | logic | VCORE POK @3.3V |
| aon_en_i | in | logic | AON Source Clock Enable |
| aon_clk_o | out | logic | AON Clock Output |
This design unit is implemented in aon_timer_core.sv
This file depends on: lc_ctrl_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_aon_i | in | logic | |
| rst_aon_ni | in | logic | |
| lc_escalate_en_i | in | [2:0] lc_tx_t | |
| sleep_mode_i | in | logic | |
| wkup_enable_o | out | logic | Register read outputs |
| wkup_prescaler_o | out | [11:0] logic | |
| wkup_thold_o | out | [31:0] logic | |
| wkup_count_o | out | [31:0] logic | |
| wdog_enable_o | out | logic | |
| wdog_pause_o | out | logic | |
| wdog_bark_thold_o | out | [31:0] logic | |
| wdog_bite_thold_o | out | [31:0] logic | |
| wdog_count_o | out | [31:0] logic | |
| wkup_ctrl_reg_wr_i | in | logic | Register write inputs |
| wkup_ctrl_wr_data_i | in | [12:0] logic | |
| wkup_thold_reg_wr_i | in | logic | |
| wkup_thold_wr_data_i | in | [31:0] logic | |
| wkup_count_reg_wr_i | in | logic | |
| wkup_count_wr_data_i | in | [31:0] logic | |
| wdog_ctrl_reg_wr_i | in | logic | |
| wdog_ctrl_wr_data_i | in | [1:0] logic | |
| wdog_bark_thold_reg_wr_i | in | logic | |
| wdog_bark_thold_wr_data_i | in | [31:0] logic | |
| wdog_bite_thold_reg_wr_i | in | logic | |
| wdog_bite_thold_wr_data_i | in | [31:0] logic | |
| wdog_count_reg_wr_i | in | logic | |
| wdog_count_wr_data_i | in | [31:0] logic | |
| wkup_intr_o | out | logic | |
| wdog_intr_o | out | logic | |
| wdog_reset_req_o | out | logic |
This design unit is implemented in aon_timer_reg_pkg.sv
This design unit is implemented in aon_timer_reg_top.sv
This file depends on: prim_subreg_ext.sv, aon_timer_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 6 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | aon_timer_reg2hw_t | Write |
| hw2reg | in | aon_timer_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fenable: 0:0
Fprescaler: 12:1
Fenable: 0:0
Fpause_in_sleep: 1:1
Fwkup_timer_expired: 0:0
Fwdog_timer_expired: 1:1
Fwkup_timer_expired: 0:0
Fwdog_timer_expired: 1:1
Fwkup_timer_expired: 0:0
Fwdog_timer_expired: 1:1
This design unit is implemented in clkmgr_reg_pkg.sv
This design unit is implemented in clkmgr_reg_top.sv
This file depends on: prim_subreg.sv, uvm_pkg.sv, clkmgr_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 4 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | clkmgr_reg2hw_t | Write |
| hw2reg | in | clkmgr_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fclk_io_div4_peri_en: 0:0
Fclk_io_div2_peri_en: 1:1
Fclk_usb_peri_en: 2:2
Fclk_main_aes_hint: 0:0
Fclk_main_hmac_hint: 1:1
Fclk_main_kmac_hint: 2:2
Fclk_main_otbn_hint: 3:3
Fclk_main_aes_val: 0:0
Fclk_main_hmac_val: 1:1
Fclk_main_kmac_val: 2:2
Fclk_main_otbn_val: 3:3
This design unit is implemented in csrng_core.sv
This file depends on: csrng_pkg.sv, entropy_src_pkg.sv, csrng_state_db.sv, csrng_ctr_drbg_upd.sv, prim_lc_sync.sv, prim_intr_hw.sv, csrng_reg_pkg.sv, csrng_block_encrypt.sv, prim_arbiter_ppc.sv, csrng_ctr_drbg_gen.sv, csrng_ctr_drbg_cmd.sv, aes_pkg.sv, lc_ctrl_pkg.sv, csrng_main_sm.sv, prim_packer_fifo.sv, csrng_cmd_stage.sv
csrng_core
| Name | Type | Default Value | Description |
|---|---|---|---|
| SBoxImpl | sbox_impl_e | aes_pkg::SBoxImplLut | |
| NHwApps | int | 2 | |
| NApps | int | NHwApps + 1 | |
| AppCmdWidth | int | 32 | |
| AppCmdFifoDepth | int | 2 | |
| GenBitsWidth | int | 128 | |
| Cmd | int | 3 | |
| StateId | int | 4 | |
| KeyLen | int | 256 | |
| BlkLen | int | 128 | |
| SeedLen | int | 384 | |
| CtrLen | int | 32 | |
| NBlkEncArbReqs | int | 2 | |
| BlkEncArbWidth | int | KeyLen+BlkLen+StateId+Cmd | |
| NUpdateArbReqs | int | 2 | |
| UpdateArbWidth | int | KeyLen+BlkLen+SeedLen+StateId+Cmd |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| reg2hw | in | csrng_reg2hw_t | |
| hw2reg | out | csrng_hw2reg_t | |
| efuse_sw_app_enable_i | in | logic | Efuse Interface |
| lc_hw_debug_en_i | in | lc_tx_t | Lifecycle broadcast inputs |
| entropy_src_hw_if_o | out | entropy_src_hw_if_req_t | Entropy Interface |
| entropy_src_hw_if_i | in | entropy_src_hw_if_rsp_t | |
| csrng_cmd_i | in | [NHwApps-1:0] csrng_req_t | Application Interfaces |
| csrng_cmd_o | out | [NHwApps-1:0] csrng_rsp_t | |
| alert_test_o | out | logic | Alerts |
| fatal_alert_o | out | logic | |
| intr_cs_cmd_req_done_o | out | logic | |
| intr_cs_entropy_req_o | out | logic | |
| intr_cs_hw_inst_exc_o | out | logic | |
| intr_cs_fatal_err_o | out | logic |
sm to process all instantiation requests
This design unit is implemented in csrng_reg_pkg.sv
This design unit is implemented in csrng_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, csrng_reg_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 6 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | csrng_reg2hw_t | Write |
| hw2reg | in | csrng_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fcs_cmd_req_done: 0:0
Fcs_entropy_req: 1:1
Fcs_hw_inst_exc: 2:2
Fcs_fatal_err: 3:3
Fcs_cmd_req_done: 0:0
Fcs_entropy_req: 1:1
Fcs_hw_inst_exc: 2:2
Fcs_fatal_err: 3:3
Fcs_cmd_req_done: 0:0
Fcs_entropy_req: 1:1
Fcs_hw_inst_exc: 2:2
Fcs_fatal_err: 3:3
Fenable: 0:0
Faes_cipher_disable: 1:1
Ffifo_depth_sts_sel: 19:16
Ffifo_depth_sts: 23:0
Fdiag: 31:31
Fcmd_rdy: 0:0
Fcmd_sts: 1:1
Fgenbits_vld: 0:0
Fgenbits_fips: 1:1
Fsfifo_cmd_err: 0:0
Fsfifo_genbits_err: 1:1
Fsfifo_cmdreq_err: 2:2
Fsfifo_rcstage_err: 3:3
Fsfifo_keyvrc_err: 4:4
Fsfifo_updreq_err: 5:5
Fsfifo_bencreq_err: 6:6
Fsfifo_bencack_err: 7:7
Fsfifo_pdata_err: 8:8
Fsfifo_final_err: 9:9
Fsfifo_gbencack_err: 10:10
Fsfifo_grcstage_err: 11:11
Fsfifo_ggenreq_err: 12:12
Fsfifo_gadstage_err: 13:13
Fsfifo_ggenbits_err: 14:14
Fsfifo_blkenc_err: 15:15
Fcmd_stage_sm_err: 20:20
Fmain_sm_err: 21:21
Fdrbg_gen_sm_err: 22:22
Fdrbg_updbe_sm_err: 23:23
Fdrbg_updob_sm_err: 24:24
Faes_cipher_sm_err: 25:25
Ffifo_write_err: 28:28
Ffifo_read_err: 29:29
Ffifo_state_err: 30:30
This design unit is implemented in dm_csrs.sv
This file depends on: prim_fifo_sync.sv, dm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NrHarts | int | 1 | |
| BusWidth | int | 32 | |
| SelectableHarts | [NrHarts-1:0] logic | {NrHarts{1'b1}} | |
| HartSelLen | int | (NrHarts == 1) ? 1 : $clog2(NrHarts) | the amount of bits we need to represent all harts |
| NrHartsAligned | int | 2**HartSelLen | |
| DataEnd | dm_csr_e | dm::dm_csr_e'(dm::Data0 + {4'h0, dm::DataCount} - 8'h1) | |
| ProgBufEnd | dm_csr_e | dm::dm_csr_e'(dm::ProgBuf0 + {4'h0, dm::ProgBufSize} - 8'h1) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock |
| rst_ni | in | logic | Asynchronous reset active low |
| testmode_i | in | logic | |
| dmi_rst_ni | in | logic | Debug Module Intf reset active-low |
| dmi_req_valid_i | in | logic | |
| dmi_req_ready_o | out | logic | |
| dmi_req_i | in | dmi_req_t | |
| dmi_resp_valid_o | out | logic | every request needs a response one cycle later |
| dmi_resp_ready_i | in | logic | |
| dmi_resp_o | out | dmi_resp_t | |
| ndmreset_o | out | logic | non-debug module reset active-high |
| dmactive_o | out | logic | 1 -> debug-module is active, 0 -> synchronous re-set |
| hartinfo_i | in | [NrHarts-1:0] hartinfo_t | static hartinfo |
| halted_i | in | [NrHarts-1:0] logic | hart is halted |
| unavailable_i | in | [NrHarts-1:0] logic | e.g.: powered down |
| resumeack_i | in | [NrHarts-1:0] logic | hart acknowledged resume request |
| hartsel_o | out | [19:0] logic | hartselect to ctrl module |
| haltreq_o | out | [NrHarts-1:0] logic | request to halt a hart |
| resumereq_o | out | [NrHarts-1:0] logic | request hart to resume |
| clear_resumeack_o | out | logic | |
| cmd_valid_o | out | logic | debugger writing to cmd field |
| cmd_o | out | command_t | abstract command |
| cmderror_valid_i | in | logic | an error occurred |
| cmderror_i | in | cmderr_e | this error occurred |
| cmdbusy_i | in | logic | cmd is currently busy executing |
| progbuf_o | out | [31:0] [dm::ProgBufSize-1:0] logic | to system bus |
| data_o | out | [31:0] [dm::DataCount-1:0] logic | |
| data_i | in | [31:0] [dm::DataCount-1:0] logic | |
| data_valid_i | in | logic | |
| sbaddress_o | out | [BusWidth-1:0] logic | system bus access module (SBA) |
| sbaddress_i | in | [BusWidth-1:0] logic | |
| sbaddress_write_valid_o | out | logic | |
| sbreadonaddr_o | out | logic | control signals in |
| sbautoincrement_o | out | logic | |
| sbaccess_o | out | [2:0] logic | |
| sbreadondata_o | out | logic | data out |
| sbdata_o | out | [BusWidth-1:0] logic | |
| sbdata_read_valid_o | out | logic | |
| sbdata_write_valid_o | out | logic | |
| sbdata_i | in | [BusWidth-1:0] logic | read data in |
| sbdata_valid_i | in | logic | |
| sbbusy_i | in | logic | control signals |
| sberror_valid_i | in | logic | bus error occurred |
| sberror_i | in | [2:0] logic | bus error occurred |
response FIFO
This design unit is implemented in dm_mem.sv
This file depends on: debug_rom_one_scratch.sv, dm_pkg.sv, debug_rom.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NrHarts | int | 1 | |
| BusWidth | int | 32 | |
| SelectableHarts | [NrHarts-1:0] logic | {NrHarts{1'b1}} | |
| DmBaseAddress | int | '0 | |
| DbgAddressBits | int | 12 | |
| HartSelLen | int | (NrHarts == 1) ? 1 : $clog2(NrHarts) | |
| NrHartsAligned | int | 2**HartSelLen | |
| MaxAar | int | (BusWidth == 64) ? 4 : 3 | |
| HasSndScratch | bit | (DmBaseAddress != 0) | |
| LoadBaseAddr | [4:0] logic | (DmBaseAddress == 0) ? 5'd0 : 5'd10 | Depending on whether we are at the zero page or not we either use |
| DataBaseAddr | [DbgAddressBits-1:0] logic | (dm::DataAddr) | |
| DataEndAddr | [DbgAddressBits-1:0] logic | (dm::DataAddr + 4*dm::DataCount - 1) | |
| ProgBufBaseAddr | [DbgAddressBits-1:0] logic | (dm::DataAddr - 4*dm::ProgBufSize) | |
| ProgBufEndAddr | [DbgAddressBits-1:0] logic | (dm::DataAddr - 1) | |
| AbstractCmdBaseAddr | [DbgAddressBits-1:0] logic | (ProgBufBaseAddr - 4*10) | |
| AbstractCmdEndAddr | [DbgAddressBits-1:0] logic | (ProgBufBaseAddr - 1) | |
| WhereToAddr | [DbgAddressBits-1:0] logic | 'h300 | |
| FlagsBaseAddr | [DbgAddressBits-1:0] logic | 'h400 | |
| FlagsEndAddr | [DbgAddressBits-1:0] logic | 'h7FF | |
| HaltedAddr | [DbgAddressBits-1:0] logic | 'h100 | |
| GoingAddr | [DbgAddressBits-1:0] logic | 'h104 | |
| ResumingAddr | [DbgAddressBits-1:0] logic | 'h108 | |
| ExceptionAddr | [DbgAddressBits-1:0] logic | 'h10C |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock |
| rst_ni | in | logic | debug module reset |
| debug_req_o | out | [NrHarts-1:0] logic | |
| hartsel_i | in | [19:0] logic | |
| haltreq_i | in | [NrHarts-1:0] logic | from Ctrl and Status register |
| resumereq_i | in | [NrHarts-1:0] logic | |
| clear_resumeack_i | in | logic | |
| halted_o | out | [NrHarts-1:0] logic | hart acknowledge halt |
| resuming_o | out | [NrHarts-1:0] logic | hart is resuming |
| progbuf_i | in | [31:0] [dm::ProgBufSize-1:0] logic | program buffer to expose |
| data_i | in | [31:0] [dm::DataCount-1:0] logic | data in |
| data_o | out | [31:0] [dm::DataCount-1:0] logic | data out |
| data_valid_o | out | logic | data out is valid |
| cmd_valid_i | in | logic | abstract command interface |
| cmd_i | in | command_t | |
| cmderror_valid_o | out | logic | |
| cmderror_o | out | cmderr_e | |
| cmdbusy_o | out | logic | |
| req_i | in | logic | SRAM interface |
| we_i | in | logic | |
| addr_i | in | [BusWidth-1:0] logic | |
| wdata_i | in | [BusWidth-1:0] logic | |
| be_i | in | [BusWidth/8-1:0] logic | |
| rdata_o | out | [BusWidth-1:0] logic |
This design unit is implemented in dm_sba.sv
This file depends on: dm_pkg.sv
Copyright 2018 ETH Zurich and University of Bologna.
Copyright and related rights are licensed under the Solderpad Hardware
License, Version 0.51 (the “License”); you may not use this file except in
compliance with the License. You may obtain a copy of the License at
http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
or agreed to in writing, software, hardware and materials distributed under
this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied. See the License for the
specific language governing permissions and limitations under the License.
File: dm_sba.sv
Author: Florian Zaruba zarubaf@iis.ee.ethz.ch
Date: 1.8.2018
Description: System Bus Access Module
| Name | Type | Default Value | Description |
|---|---|---|---|
| BusWidth | int | 32 | |
| ReadByteEnable | bit | 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock |
| rst_ni | in | logic | |
| dmactive_i | in | logic | synchronous reset active low |
| master_req_o | out | logic | |
| master_add_o | out | [BusWidth-1:0] logic | |
| master_we_o | out | logic | |
| master_wdata_o | out | [BusWidth-1:0] logic | |
| master_be_o | out | [BusWidth/8-1:0] logic | |
| master_gnt_i | in | logic | |
| master_r_valid_i | in | logic | |
| master_r_rdata_i | in | [BusWidth-1:0] logic | |
| sbaddress_i | in | [BusWidth-1:0] logic | |
| sbaddress_write_valid_i | in | logic | |
| sbreadonaddr_i | in | logic | control signals in |
| sbaddress_o | out | [BusWidth-1:0] logic | |
| sbautoincrement_i | in | logic | |
| sbaccess_i | in | [2:0] logic | |
| sbreadondata_i | in | logic | data in |
| sbdata_i | in | [BusWidth-1:0] logic | |
| sbdata_read_valid_i | in | logic | |
| sbdata_write_valid_i | in | logic | |
| sbdata_o | out | [BusWidth-1:0] logic | read data out |
| sbdata_valid_o | out | logic | |
| sbbusy_o | out | logic | control signals |
| sberror_valid_o | out | logic | bus error occurred |
| sberror_o | out | [2:0] logic | bus error occurred |
This design unit is implemented in dmi_jtag.sv
This file depends on: dmi_cdc.sv, dm_pkg.sv, dmi_jtag_tap.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| IdcodeValue | [31:0] logic | 32'h00000001 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | DMI Clock |
| rst_ni | in | logic | Asynchronous reset active low |
| testmode_i | in | logic | |
| dmi_rst_no | out | logic | hard reset |
| dmi_req_o | out | dmi_req_t | |
| dmi_req_valid_o | out | logic | |
| dmi_req_ready_i | in | logic | |
| dmi_resp_i | in | dmi_resp_t | |
| dmi_resp_ready_o | out | logic | |
| dmi_resp_valid_i | in | logic | |
| tck_i | in | logic | JTAG test clock pad |
| tms_i | in | logic | JTAG test mode select pad |
| trst_ni | in | logic | JTAG test reset pad |
| td_i | in | logic | JTAG test data input pad |
| td_o | out | logic | JTAG test data output pad |
| tdo_oe_o | out | logic | Data out output enable |
This design unit is implemented in edn_core.sv
This file depends on: csrng_pkg.sv, prim_arbiter_ppc.sv, edn_reg_pkg.sv, edn_main_sm.sv, prim_intr_hw.sv, prim_fifo_sync.sv, edn_pkg.sv, prim_packer_fifo.sv, edn_ack_sm.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumEndPoints | int | 4 | |
| BootInsCmd | int | 32'h0000_0001 | |
| BootGenCmd | int | 32'h0000_1003 | |
| RescmdFifoWidth | int | 32 | |
| RescmdFifoDepth | int | 13 | |
| GencmdFifoWidth | int | 32 | |
| GencmdFifoDepth | int | 13 | |
| CSGenBitsWidth | int | 128 | |
| EndPointBusWidth | int | 32 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| reg2hw | in | edn_reg2hw_t | |
| hw2reg | out | edn_hw2reg_t | |
| edn_i | in | [NumEndPoints-1:0] edn_req_t | EDN interfaces |
| edn_o | out | [NumEndPoints-1:0] edn_rsp_t | |
| csrng_cmd_o | out | csrng_req_t | CSRNG Application Interface |
| csrng_cmd_i | in | csrng_rsp_t | |
| alert_test_o | out | logic | Alerts |
| fatal_alert_o | out | logic | |
| intr_edn_cmd_req_done_o | out | logic | Interrupts |
| intr_edn_fatal_err_o | out | logic |
rescmd fifo
gencmd fifo
sm to process csrng commands
This design unit is implemented in edn_reg_pkg.sv
This design unit is implemented in edn_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, edn_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 6 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | edn_reg2hw_t | Write |
| hw2reg | in | edn_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fedn_cmd_req_done: 0:0
Fedn_fatal_err: 1:1
Fedn_cmd_req_done: 0:0
Fedn_fatal_err: 1:1
Fedn_cmd_req_done: 0:0
Fedn_fatal_err: 1:1
Fedn_enable: 0:0
Fcmd_fifo_rst: 1:1
Fauto_req_mode: 2:2
Fboot_req_dis: 3:3
Freq_mode_sm_sts: 0:0
Fboot_inst_ack: 1:1
Finternal_use: 31:31
Fcmd_rdy: 0:0
Fcmd_sts: 1:1
Fsfifo_rescmd_err: 0:0
Fsfifo_gencmd_err: 1:1
Fedn_ack_sm_err: 20:20
Fedn_main_sm_err: 21:21
Ffifo_write_err: 28:28
Ffifo_read_err: 29:29
Ffifo_state_err: 30:30
This design unit is implemented in entropy_src_core.sv
This file depends on: entropy_src_pkg.sv, entropy_src_cntr_reg.sv, entropy_src_bucket_ht.sv, prim_lfsr.sv, entropy_src_ack_sm.sv, entropy_src_reg_pkg.sv, prim_intr_hw.sv, entropy_src_watermark_reg.sv, entropy_src_adaptp_ht.sv, entropy_src_main_sm.sv, entropy_src_repcnt_ht.sv, prim_fifo_sync.sv, entropy_src_markov_ht.sv, prim_packer_fifo.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| EsFifoDepth | int | 2 | |
| Clog2EsFifoDepth | int | $clog2(EsFifoDepth) | |
| PostHTWidth | int | 32 | |
| RngBusWidth | int | 4 | |
| HalfRegWidth | int | 16 | |
| FullRegWidth | int | 32 | |
| EigthRegWidth | int | 4 | |
| SeedLen | int | 384 | |
| PreCondFifoWidth | int | 32 | |
| PreCondFifoDepth | int | 64 | |
| PreCondWidth | int | 64 | |
| Clog2PreCondFifoDepth | int | $clog2(PreCondFifoDepth) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| reg2hw | in | entropy_src_reg2hw_t | |
| hw2reg | out | entropy_src_hw2reg_t | |
| efuse_es_sw_reg_en_i | in | logic | Efuse Interface |
| entropy_src_hw_if_i | in | entropy_src_hw_if_req_t | Entropy Interface |
| entropy_src_hw_if_o | out | entropy_src_hw_if_rsp_t | |
| entropy_src_rng_o | out | entropy_src_rng_req_t | RNG Interface |
| entropy_src_rng_i | in | entropy_src_rng_rsp_t | |
| entropy_src_xht_o | out | entropy_src_xht_req_t | External Health Test Interface |
| entropy_src_xht_i | in | entropy_src_xht_rsp_t | |
| recov_alert_test_o | out | logic | |
| fatal_alert_test_o | out | logic | |
| recov_alert_o | out | logic | |
| fatal_alert_o | out | logic | |
| intr_es_entropy_valid_o | out | logic | |
| intr_es_health_test_failed_o | out | logic | |
| intr_es_fatal_err_o | out | logic |
repcnt fail counter
adaptp fail counter hi and lo
bucket fail counter
markov fail counter hi and lo
extht fail counter hi and lo
TODO: remove temp standin block
This design unit is implemented in entropy_src_reg_pkg.sv
This design unit is implemented in entropy_src_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, entropy_src_reg_pkg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 8 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | entropy_src_reg2hw_t | Write |
| hw2reg | in | entropy_src_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fes_entropy_valid: 0:0
Fes_health_test_failed: 1:1
Fes_fatal_err: 2:2
Fes_entropy_valid: 0:0
Fes_health_test_failed: 1:1
Fes_fatal_err: 2:2
Fes_entropy_valid: 0:0
Fes_health_test_failed: 1:1
Fes_fatal_err: 2:2
Frecov_alert: 0:0
Ffatal_alert: 1:1
Fenable: 1:0
Fboot_bypass_disable: 3:3
Frepcnt_disable: 4:4
Fadaptp_disable: 5:5
Fbucket_disable: 6:6
Fmarkov_disable: 7:7
Fhealth_test_clr: 8:8
Frng_bit_en: 9:9
Frng_bit_sel: 11:10
Fextht_enable: 12:12
Fes_route: 0:0
Fes_type: 1:1
Ffips_window: 15:0
Fbypass_window: 31:16
Ffips_repcnt_thresh: 15:0
Fbypass_repcnt_thresh: 31:16
Ffips_adaptp_hi_thresh: 15:0
Fbypass_adaptp_hi_thresh: 31:16
Ffips_adaptp_lo_thresh: 15:0
Fbypass_adaptp_lo_thresh: 31:16
Ffips_bucket_thresh: 15:0
Fbypass_bucket_thresh: 31:16
Ffips_markov_hi_thresh: 15:0
Fbypass_markov_hi_thresh: 31:16
Ffips_markov_lo_thresh: 15:0
Fbypass_markov_lo_thresh: 31:16
Ffips_extht_hi_thresh: 15:0
Fbypass_extht_hi_thresh: 31:16
Ffips_extht_lo_thresh: 15:0
Fbypass_extht_lo_thresh: 31:16
Ffips_repcnt_hi_watermark: 15:0
Fbypass_repcnt_hi_watermark: 31:16
Ffips_adaptp_hi_watermark: 15:0
Fbypass_adaptp_hi_watermark: 31:16
Ffips_adaptp_lo_watermark: 15:0
Fbypass_adaptp_lo_watermark: 31:16
Ffips_extht_hi_watermark: 15:0
Fbypass_extht_hi_watermark: 31:16
Ffips_extht_lo_watermark: 15:0
Fbypass_extht_lo_watermark: 31:16
Ffips_bucket_hi_watermark: 15:0
Fbypass_bucket_hi_watermark: 31:16
Ffips_markov_hi_watermark: 15:0
Fbypass_markov_hi_watermark: 31:16
Ffips_markov_lo_watermark: 15:0
Fbypass_markov_lo_watermark: 31:16
Fany_fail_count: 3:0
Frepcnt_fail_count: 7:4
Fadaptp_hi_fail_count: 11:8
Fadaptp_lo_fail_count: 15:12
Fbucket_fail_count: 19:16
Fmarkov_hi_fail_count: 23:20
Fmarkov_lo_fail_count: 27:24
Fextht_hi_fail_count: 3:0
Fextht_lo_fail_count: 7:4
Ffw_ov_mode: 0:0
Ffw_ov_fifo_reg_rd: 1:1
Ffw_ov_fifo_reg_wr: 2:2
Fentropy_fifo_depth: 1:0
Fdiag: 31:31
Fsfifo_esrng_err: 0:0
Fsfifo_precon_err: 1:1
Fsfifo_esfinal_err: 2:2
Fes_ack_sm_err: 20:20
Fes_main_sm_err: 21:21
Ffifo_write_err: 28:28
Ffifo_read_err: 29:29
Ffifo_state_err: 30:30
This design unit is implemented in flash_ctrl_arb.sv
This file depends on: flash_ctrl_pkg.sv, flash_ctrl_reg_pkg.sv
flash_ctrl_rd_arb
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| sw_ctrl_i | in | flash_ctrl_reg2hw_control_reg_t | software interface to rd_ctrl / erase_ctrl |
| sw_addr_i | in | [31:0] logic | |
| sw_ack_o | out | logic | |
| sw_err_o | out | logic | |
| sw_rvalid_o | out | logic | software interface to rd_fifo |
| sw_rready_i | in | logic | |
| sw_wvalid_i | in | logic | software interface to prog_fifo |
| sw_wready_o | out | logic | |
| sw_wdata_i | in | [BusWidth-1:0] logic | |
| hw_req_i | in | logic | hardware interface to rd_ctrl / erase_ctrl |
| hw_ctrl_i | in | flash_ctrl_reg2hw_control_reg_t | |
| hw_phase_i | in | flash_lcmgr_phase_e | |
| hw_addr_i | in | [31:0] logic | |
| hw_ack_o | out | logic | |
| hw_err_o | out | logic | |
| hw_rvalid_o | out | logic | hardware interface to rd_fifo |
| hw_rready_i | in | logic | |
| hw_wvalid_i | in | logic | hardware interface to prog_fifo |
| hw_wdata_i | in | [BusWidth-1:0] logic | |
| hw_wready_o | out | logic | |
| muxed_ctrl_o | out | flash_ctrl_reg2hw_control_reg_t | muxed interface to rd_ctrl / erase_ctrl |
| muxed_addr_o | out | [31:0] logic | |
| prog_ack_i | in | logic | |
| prog_err_i | in | logic | |
| rd_ack_i | in | logic | |
| rd_err_i | in | logic | |
| erase_ack_i | in | logic | |
| erase_err_i | in | logic | |
| rd_fifo_rvalid_i | in | logic | muxed interface to rd_fifo |
| rd_fifo_rready_o | out | logic | |
| prog_fifo_wvalid_o | out | logic | muxed interface to prog_fifo |
| prog_fifo_wdata_o | out | [BusWidth-1:0] logic | |
| prog_fifo_wready_i | in | logic | |
| flash_phy_busy_i | in | logic | flash phy initialization ongoing |
| fifo_clr_o | out | logic | clear fifo contents |
| phase_o | out | flash_lcmgr_phase_e | output to memory protection |
| sel_o | out | flash_sel_e | indication that sw has been selected |
This design unit is implemented in flash_ctrl_erase.sv
This file depends on: flash_ctrl_pkg.sv
flash_ctrl_erase
| Name | Type | Default Value | Description |
|---|---|---|---|
| WordsBitWidth | int | $clog2(BusWordsPerPage) | |
| PagesBitWidth | int | $clog2(PagesPerBank) | |
| PageAddrMask | [BusAddrW-1:0] logic | ~(('h1 << WordsBitWidth) - 1'b1) | The *AddrMask below masks out the bits that are not required e.g, assume we have an address 0x5_0004_345C 0x5 represents bank address 0x0004 represents page address PageAddrMask would be 0xF_FFFF_0000 BankAddrMask would be 0xF_0000_0000 |
| BankAddrMask | [BusAddrW-1:0] logic | ~(('h1 << (PagesBitWidth + WordsBitWidth)) - 1'b1) |
| Name | Direction | Type | Description |
|---|---|---|---|
| op_start_i | in | logic | Software Interface |
| op_type_i | in | flash_erase_e | |
| op_addr_i | in | [BusAddrW-1:0] logic | |
| op_done_o | out | logic | |
| op_err_o | out | logic | |
| flash_req_o | out | logic | Flash Macro Interface |
| flash_addr_o | out | [BusAddrW-1:0] logic | |
| flash_op_o | out | flash_erase_e | |
| flash_done_i | in | logic | |
| flash_error_i | in | logic |
This design unit is implemented in flash_ctrl_info_cfg.sv
This file depends on: flash_ctrl_pkg.sv, flash_ctrl_reg_pkg.sv
flash_ctrl_info_cfg
| Name | Type | Default Value | Description |
|---|---|---|---|
| Bank | [BankW-1:0] logic | 0 | |
| InfoSel | int | 0 | |
| CfgBitWidth | int | $bits(info_page_cfg_t) |
| Name | Direction | Type | Description |
|---|---|---|---|
| cfgs_i | in | [InfosPerBank-1:0] info_page_cfg_t | |
| creator_seed_priv_i | in | logic | |
| owner_seed_priv_i | in | logic | |
| iso_flash_wr_en_i | in | logic | |
| iso_flash_rd_en_i | in | logic | |
| cfgs_o | out | [InfosPerBank-1:0] info_page_cfg_t |
This design unit is implemented in flash_ctrl_lcmgr.sv
This file depends on: prim_flop_2sync.sv, top_pkg.sv, prim_lc_sync.sv, otp_ctrl_pkg.sv, flash_ctrl_pkg.sv, prim_sync_reqack.sv, prim_util_pkg.sv, flash_ctrl_reg_pkg.sv, lc_ctrl_pkg.sv
flash_ctrl_lcmgr
| Name | Type | Default Value | Description |
|---|---|---|---|
| RndCnstAddrKey | flash_key_t | RndCnstAddrKeyDefault | |
| RndCnstDataKey | flash_key_t | RndCnstDataKeyDefault | |
| WipeIdxWidth | int | prim_util_pkg::vbits(WipeEntries) | total number of pages to be wiped during RMA entry |
| SeedReads | int | SeedWidth / BusWidth | seed related local params |
| SeedRdsWidth | int | $clog2(SeedReads) | |
| SeedCntWidth | int | $clog2(NumSeeds+1) | |
| NumSeedWidth | int | $clog2(NumSeeds) | |
| PageCntWidth | int | prim_util_pkg::vbits(PagesPerBank + 1) | |
| WordCntWidth | int | prim_util_pkg::vbits(BusWordsPerPage + 1) | |
| BeatCntWidth | int | prim_util_pkg::vbits(WidthMultiple) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clk_otp_i | in | logic | |
| rst_otp_ni | in | logic | |
| init_i | in | logic | initialization command |
| init_done_o | out | logic | |
| provision_en_i | in | logic | only access seeds when provisioned |
| ctrl_o | out | flash_ctrl_reg2hw_control_reg_t | interface to ctrl arb control ports |
| req_o | out | logic | |
| addr_o | out | [top_pkg::TL_AW-1:0] logic | |
| done_i | in | logic | |
| err_i | in | logic | |
| rready_o | out | logic | interface to ctrl_arb data ports |
| rvalid_i | in | logic | |
| wvalid_o | out | logic | |
| wready_i | in | logic | |
| rdata_i | in | [BusWidth-1:0] logic | direct form rd_fifo |
| wdata_o | out | [BusWidth-1:0] logic | direct to wr_fifo |
| rma_req_i | in | lc_tx_t | external rma request This should be simplified to just multi-bit request and multi-bit response |
| rma_ack_o | out | lc_tx_t | |
| seeds_o | out | [SeedWidth-1:0] [NumSeeds-1:0] logic | seeds to the outside world, |
| phase_o | out | flash_lcmgr_phase_e | indicate to memory protection what phase the hw interface is in |
| seed_err_o | out | logic | error status to registers |
| rd_buf_en_o | out | logic | enable read buffer in flash_phy |
| otp_key_req_o | out | flash_otp_key_req_t | request otp keys |
| otp_key_rsp_i | in | flash_otp_key_rsp_t | |
| addr_key_o | out | flash_key_t | |
| data_key_o | out | flash_key_t | |
| edn_req_o | out | logic | entropy interface |
| edn_ack_i | in | logic | |
| lfsr_en_o | out | logic | |
| rand_i | in | [BusWidth-1:0] logic | |
| init_busy_o | out | logic | init ongoing |
req/ack to otp
req/ack to otp
This design unit is implemented in flash_ctrl_prog.sv
This file depends on: flash_ctrl_pkg.sv
flash_ctrl_prog
| Name | Type | Default Value | Description |
|---|---|---|---|
| WindowWidth | int | BusAddrW - BusPgmResWidth | program resolution check if the incoming beat is larger than the maximum program resolution, error immediately and do not allow it to start. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| op_start_i | in | logic | Control Interface |
| op_num_words_i | in | [11:0] logic | |
| op_done_o | out | logic | |
| op_err_o | out | logic | |
| op_addr_i | in | [BusAddrW-1:0] logic | |
| op_type_i | in | flash_prog_e | |
| type_avail_i | in | [ProgTypes-1:0] logic | |
| data_rdy_i | in | logic | FIFO Interface |
| data_i | in | [BusWidth-1:0] logic | |
| data_rd_o | out | logic | |
| flash_req_o | out | logic | Flash Macro Interface |
| flash_addr_o | out | [BusAddrW-1:0] logic | |
| flash_ovfl_o | out | logic | |
| flash_data_o | out | [BusWidth-1:0] logic | |
| flash_last_o | out | logic | last beat of prog data |
| flash_type_o | out | flash_prog_e | |
| flash_done_i | in | logic | |
| flash_error_i | in | logic |
This design unit is implemented in flash_ctrl_rd.sv
This file depends on: flash_ctrl_pkg.sv
flash_ctrl_rd
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| op_start_i | in | logic | Software Interface |
| op_num_words_i | in | [11:0] logic | |
| op_done_o | out | logic | |
| op_err_o | out | logic | |
| op_addr_i | in | [BusAddrW-1:0] logic | |
| data_rdy_i | in | logic | FIFO Interface |
| data_o | out | [BusWidth-1:0] logic | |
| data_wr_o | out | logic | |
| flash_req_o | out | logic | Flash Macro Interface |
| flash_addr_o | out | [BusAddrW-1:0] logic | |
| flash_ovfl_o | out | logic | |
| flash_data_i | in | [BusWidth-1:0] logic | |
| flash_done_i | in | logic | |
| flash_error_i | in | logic |
This design unit is implemented in flash_ctrl_reg_pkg.sv
This design unit is implemented in flash_ctrl_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, flash_ctrl_reg_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 9 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| tl_win_o | out | tl_h2d_t [3] | Output port for window |
| tl_win_i | in | tl_d2h_t [3] | |
| reg2hw | out | flash_ctrl_reg2hw_t | Write |
| hw2reg | in | flash_ctrl_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Create Socket_1n
Fprog_empty: 0:0
Fprog_lvl: 1:1
Frd_full: 2:2
Frd_lvl: 3:3
Fop_done: 4:4
Fprog_empty: 0:0
Fprog_lvl: 1:1
Frd_full: 2:2
Frd_lvl: 3:3
Fop_done: 4:4
Fprog_empty: 0:0
Fprog_lvl: 1:1
Frd_full: 2:2
Frd_lvl: 3:3
Fop_done: 4:4
Frecov_err: 0:0
Frecov_mp_err: 1:1
Frecov_ecc_err: 2:2
Fstart: 0:0
Fop: 5:4
Fprog_sel: 6:6
Ferase_sel: 7:7
Fpartition_sel: 8:8
Finfo_sel: 10:9
Fnum: 27:16
Fnormal: 0:0
Frepair: 1:1
Fen_0: 0:0
Frd_en_0: 1:1
Fprog_en_0: 2:2
Ferase_en_0: 3:3
Fscramble_en_0: 4:4
Fecc_en_0: 5:5
Fhe_en_0: 6:6
Fbase_0: 16:8
Fsize_0: 26:17
Fen_1: 0:0
Frd_en_1: 1:1
Fprog_en_1: 2:2
Ferase_en_1: 3:3
Fscramble_en_1: 4:4
Fecc_en_1: 5:5
Fhe_en_1: 6:6
Fbase_1: 16:8
Fsize_1: 26:17
Fen_2: 0:0
Frd_en_2: 1:1
Fprog_en_2: 2:2
Ferase_en_2: 3:3
Fscramble_en_2: 4:4
Fecc_en_2: 5:5
Fhe_en_2: 6:6
Fbase_2: 16:8
Fsize_2: 26:17
Fen_3: 0:0
Frd_en_3: 1:1
Fprog_en_3: 2:2
Ferase_en_3: 3:3
Fscramble_en_3: 4:4
Fecc_en_3: 5:5
Fhe_en_3: 6:6
Fbase_3: 16:8
Fsize_3: 26:17
Fen_4: 0:0
Frd_en_4: 1:1
Fprog_en_4: 2:2
Ferase_en_4: 3:3
Fscramble_en_4: 4:4
Fecc_en_4: 5:5
Fhe_en_4: 6:6
Fbase_4: 16:8
Fsize_4: 26:17
Fen_5: 0:0
Frd_en_5: 1:1
Fprog_en_5: 2:2
Ferase_en_5: 3:3
Fscramble_en_5: 4:4
Fecc_en_5: 5:5
Fhe_en_5: 6:6
Fbase_5: 16:8
Fsize_5: 26:17
Fen_6: 0:0
Frd_en_6: 1:1
Fprog_en_6: 2:2
Ferase_en_6: 3:3
Fscramble_en_6: 4:4
Fecc_en_6: 5:5
Fhe_en_6: 6:6
Fbase_6: 16:8
Fsize_6: 26:17
Fen_7: 0:0
Frd_en_7: 1:1
Fprog_en_7: 2:2
Ferase_en_7: 3:3
Fscramble_en_7: 4:4
Fecc_en_7: 5:5
Fhe_en_7: 6:6
Fbase_7: 16:8
Fsize_7: 26:17
Frd_en: 0:0
Fprog_en: 1:1
Ferase_en: 2:2
Fscramble_en: 3:3
Fecc_en: 4:4
Fhe_en: 5:5
Fen_0: 0:0
Frd_en_0: 1:1
Fprog_en_0: 2:2
Ferase_en_0: 3:3
Fscramble_en_0: 4:4
Fecc_en_0: 5:5
Fhe_en_0: 6:6
Fen_1: 0:0
Frd_en_1: 1:1
Fprog_en_1: 2:2
Ferase_en_1: 3:3
Fscramble_en_1: 4:4
Fecc_en_1: 5:5
Fhe_en_1: 6:6
Fen_2: 0:0
Frd_en_2: 1:1
Fprog_en_2: 2:2
Ferase_en_2: 3:3
Fscramble_en_2: 4:4
Fecc_en_2: 5:5
Fhe_en_2: 6:6
Fen_3: 0:0
Frd_en_3: 1:1
Fprog_en_3: 2:2
Ferase_en_3: 3:3
Fscramble_en_3: 4:4
Fecc_en_3: 5:5
Fhe_en_3: 6:6
Fen_4: 0:0
Frd_en_4: 1:1
Fprog_en_4: 2:2
Ferase_en_4: 3:3
Fscramble_en_4: 4:4
Fecc_en_4: 5:5
Fhe_en_4: 6:6
Fen_5: 0:0
Frd_en_5: 1:1
Fprog_en_5: 2:2
Ferase_en_5: 3:3
Fscramble_en_5: 4:4
Fecc_en_5: 5:5
Fhe_en_5: 6:6
Fen_6: 0:0
Frd_en_6: 1:1
Fprog_en_6: 2:2
Ferase_en_6: 3:3
Fscramble_en_6: 4:4
Fecc_en_6: 5:5
Fhe_en_6: 6:6
Fen_7: 0:0
Frd_en_7: 1:1
Fprog_en_7: 2:2
Ferase_en_7: 3:3
Fscramble_en_7: 4:4
Fecc_en_7: 5:5
Fhe_en_7: 6:6
Fen_8: 0:0
Frd_en_8: 1:1
Fprog_en_8: 2:2
Ferase_en_8: 3:3
Fscramble_en_8: 4:4
Fecc_en_8: 5:5
Fhe_en_8: 6:6
Fen_9: 0:0
Frd_en_9: 1:1
Fprog_en_9: 2:2
Ferase_en_9: 3:3
Fscramble_en_9: 4:4
Fecc_en_9: 5:5
Fhe_en_9: 6:6
Fen_0: 0:0
Frd_en_0: 1:1
Fprog_en_0: 2:2
Ferase_en_0: 3:3
Fscramble_en_0: 4:4
Fecc_en_0: 5:5
Fhe_en_0: 6:6
Fen_0: 0:0
Frd_en_0: 1:1
Fprog_en_0: 2:2
Ferase_en_0: 3:3
Fscramble_en_0: 4:4
Fecc_en_0: 5:5
Fhe_en_0: 6:6
Fen_1: 0:0
Frd_en_1: 1:1
Fprog_en_1: 2:2
Ferase_en_1: 3:3
Fscramble_en_1: 4:4
Fecc_en_1: 5:5
Fhe_en_1: 6:6
Fen_0: 0:0
Frd_en_0: 1:1
Fprog_en_0: 2:2
Ferase_en_0: 3:3
Fscramble_en_0: 4:4
Fecc_en_0: 5:5
Fhe_en_0: 6:6
Fen_1: 0:0
Frd_en_1: 1:1
Fprog_en_1: 2:2
Ferase_en_1: 3:3
Fscramble_en_1: 4:4
Fecc_en_1: 5:5
Fhe_en_1: 6:6
Fen_2: 0:0
Frd_en_2: 1:1
Fprog_en_2: 2:2
Ferase_en_2: 3:3
Fscramble_en_2: 4:4
Fecc_en_2: 5:5
Fhe_en_2: 6:6
Fen_3: 0:0
Frd_en_3: 1:1
Fprog_en_3: 2:2
Ferase_en_3: 3:3
Fscramble_en_3: 4:4
Fecc_en_3: 5:5
Fhe_en_3: 6:6
Fen_4: 0:0
Frd_en_4: 1:1
Fprog_en_4: 2:2
Ferase_en_4: 3:3
Fscramble_en_4: 4:4
Fecc_en_4: 5:5
Fhe_en_4: 6:6
Fen_5: 0:0
Frd_en_5: 1:1
Fprog_en_5: 2:2
Ferase_en_5: 3:3
Fscramble_en_5: 4:4
Fecc_en_5: 5:5
Fhe_en_5: 6:6
Fen_6: 0:0
Frd_en_6: 1:1
Fprog_en_6: 2:2
Ferase_en_6: 3:3
Fscramble_en_6: 4:4
Fecc_en_6: 5:5
Fhe_en_6: 6:6
Fen_7: 0:0
Frd_en_7: 1:1
Fprog_en_7: 2:2
Ferase_en_7: 3:3
Fscramble_en_7: 4:4
Fecc_en_7: 5:5
Fhe_en_7: 6:6
Fen_8: 0:0
Frd_en_8: 1:1
Fprog_en_8: 2:2
Ferase_en_8: 3:3
Fscramble_en_8: 4:4
Fecc_en_8: 5:5
Fhe_en_8: 6:6
Fen_9: 0:0
Frd_en_9: 1:1
Fprog_en_9: 2:2
Ferase_en_9: 3:3
Fscramble_en_9: 4:4
Fecc_en_9: 5:5
Fhe_en_9: 6:6
Fen_0: 0:0
Frd_en_0: 1:1
Fprog_en_0: 2:2
Ferase_en_0: 3:3
Fscramble_en_0: 4:4
Fecc_en_0: 5:5
Fhe_en_0: 6:6
Fen_0: 0:0
Frd_en_0: 1:1
Fprog_en_0: 2:2
Ferase_en_0: 3:3
Fscramble_en_0: 4:4
Fecc_en_0: 5:5
Fhe_en_0: 6:6
Fen_1: 0:0
Frd_en_1: 1:1
Fprog_en_1: 2:2
Ferase_en_1: 3:3
Fscramble_en_1: 4:4
Fecc_en_1: 5:5
Fhe_en_1: 6:6
Ferase_en_0: 0:0
Ferase_en_1: 1:1
Fdone: 0:0
Ferr: 1:1
Frd_full: 0:0
Frd_empty: 1:1
Fprog_full: 2:2
Fprog_empty: 3:3
Finit_wip: 4:4
Fflash_err: 0:0
Fflash_alert: 1:1
Fmp_err: 2:2
Fecc_single_err: 3:3
Fecc_multi_err: 4:4
Falert_ack: 0:0
Falert_trig: 1:1
Finit_wip: 0:0
Fprog_normal_avail: 1:1
Fprog_repair_avail: 2:2
Fprog: 4:0
Frd: 12:8
This design unit is implemented in flash_mp.sv
This file depends on: uvm_pkg.sv, flash_ctrl_pkg.sv, flash_ctrl_reg_pkg.sv, flash_mp_data_region_sel.sv
flash_erase_ctrl
| Name | Type | Default Value | Description |
|---|---|---|---|
| TotalRegions | int | MpRegions+1 | Total number of regions including default region |
| HwInfoRules | int | 3 | Hardware interface permission table |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| if_sel_i | in | flash_sel_e | interface selection |
| region_cfgs_i | in | [MpRegions:0] mp_region_cfg_t | configuration from sw |
| bank_cfgs_i | in | [NumBanks-1:0] flash_ctrl_reg2hw_mp_bank_cfg_mreg_t | |
| info_page_cfgs_i | in | [InfosPerBank-1:0] [InfoTypes-1:0] [NumBanks-1:0] info_page_cfg_t | |
| erase_suspend_i | in | logic | |
| erase_suspend_done_o | out | logic | |
| req_i | in | logic | interface signals to/from *_ctrl |
| phase_i | in | flash_lcmgr_phase_e | |
| req_addr_i | in | [AllPagesW-1:0] logic | |
| req_part_i | in | flash_part_e | |
| info_sel_i | in | [InfoTypesWidth-1:0] logic | |
| addr_ovfl_i | in | logic | |
| rd_i | in | logic | |
| prog_i | in | logic | |
| pg_erase_i | in | logic | |
| bk_erase_i | in | logic | |
| rd_done_o | out | logic | |
| prog_done_o | out | logic | |
| erase_done_o | out | logic | |
| error_o | out | logic | |
| err_addr_o | out | [AllPagesW-1:0] logic | |
| req_o | out | logic | interface signals to/from flash_phy |
| rd_o | out | logic | |
| prog_o | out | logic | |
| scramble_en_o | out | logic | |
| ecc_en_o | out | logic | |
| he_en_o | out | logic | |
| pg_erase_o | out | logic | |
| bk_erase_o | out | logic | |
| erase_suspend_o | out | logic | |
| rd_done_i | in | logic | |
| prog_done_i | in | logic | |
| erase_done_i | in | logic |
This design unit is implemented in flash_mp_data_region_sel.sv
This file depends on: flash_ctrl_pkg.sv, flash_ctrl_reg_pkg.sv
flash_mp_data_region_sel
| Name | Type | Default Value | Description |
|---|---|---|---|
| Regions | int | 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| req_i | in | logic | |
| phase_i | in | flash_lcmgr_phase_e | |
| addr_i | in | [AllPagesW-1:0] logic | |
| region_attrs_i | in | data_region_attr_t [Regions] | |
| sel_cfg_o | out | mp_region_cfg_t |
This design unit is implemented in flash_phy_core.sv
This file depends on: flash_phy_prog.sv, uvm_pkg.sv, flash_phy_pkg.sv, flash_ctrl_pkg.sv, flash_phy_erase.sv, flash_phy_scramble.sv, flash_phy_rd.sv
flash_phy_core
| Name | Type | Default Value | Description |
|---|---|---|---|
| ArbCnt | int | 4 | |
| CntWidth | int | $clog2(ArbCnt + 1) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| host_req_i | in | logic | host request - read only |
| host_scramble_en_i | in | logic | |
| host_ecc_en_i | in | logic | |
| host_addr_i | in | [BusBankAddrW-1:0] logic | |
| req_i | in | logic | controller request |
| scramble_en_i | in | logic | |
| ecc_en_i | in | logic | |
| he_en_i | in | logic | |
| rd_i | in | logic | |
| prog_i | in | logic | |
| pg_erase_i | in | logic | |
| bk_erase_i | in | logic | |
| erase_suspend_req_i | in | logic | |
| part_i | in | flash_part_e | |
| info_sel_i | in | [InfoTypesWidth-1:0] logic | |
| addr_i | in | [BusBankAddrW-1:0] logic | |
| prog_data_i | in | [BusWidth-1:0] logic | |
| prog_last_i | in | logic | |
| prog_type_i | in | flash_prog_e | |
| addr_key_i | in | [KeySize-1:0] logic | |
| data_key_i | in | [KeySize-1:0] logic | |
| rd_buf_en_i | in | logic | |
| prim_flash_rsp_i | in | flash_phy_prim_flash_rsp_t | |
| prim_flash_req_o | out | flash_phy_prim_flash_req_t | |
| host_req_rdy_o | out | logic | |
| host_req_done_o | out | logic | |
| rd_done_o | out | logic | |
| prog_done_o | out | logic | |
| erase_done_o | out | logic | |
| rd_data_o | out | [BusWidth-1:0] logic | |
| rd_err_o | out | logic | |
| ecc_single_err_o | out | logic | |
| ecc_multi_err_o | out | logic | |
| ecc_addr_o | out | [BusBankAddrW-1:0] logic |
This design unit is implemented in flash_phy_pkg.sv
This file depends on: flash_ctrl_pkg.sv
flash_phy_pkg
This design unit is implemented in gpio_reg_pkg.sv
This design unit is implemented in gpio_reg_top.sv
This file depends on: prim_subreg_ext.sv, gpio_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 6 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | gpio_reg2hw_t | Write |
| hw2reg | in | gpio_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fdata: 15:0
Fmask: 31:16
Fdata: 15:0
Fmask: 31:16
Fdata: 15:0
Fmask: 31:16
Fdata: 15:0
Fmask: 31:16
This design unit is implemented in hmac_core.sv
This file depends on: hmac_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| BlockSize | int | 512 | |
| BlockSizeBits | int | $clog2(BlockSize) | |
| HashWordBits | int | $clog2($bits(sha_word_t)) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| secret_key | in | [255:0] logic | {word0, word1, ..., word7} |
| wipe_secret | in | logic | |
| wipe_v | in | [31:0] logic | |
| hmac_en | in | logic | |
| reg_hash_start | in | logic | |
| reg_hash_process | in | logic | |
| hash_done | out | logic | |
| sha_hash_start | out | logic | |
| sha_hash_process | out | logic | |
| sha_hash_done | in | logic | |
| sha_rvalid | out | logic | fifo |
| sha_rdata | out | sha_fifo_t | |
| sha_rready | in | logic | |
| fifo_rvalid | in | logic | |
| fifo_rdata | in | sha_fifo_t | |
| fifo_rready | out | logic | |
| fifo_wsel | out | logic | 0: from reg, 1: from digest |
| fifo_wvalid | out | logic | |
| fifo_wdata_sel | out | [2:0] logic | 0: digest0 .. 7: digest7 |
| fifo_wready | in | logic | |
| message_length | in | [63:0] logic | |
| sha_message_length | out | [63:0] logic |
This design unit is implemented in hmac_pkg.sv
This design unit is implemented in hmac_reg_pkg.sv
This design unit is implemented in hmac_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, hmac_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 12 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| tl_win_o | out | tl_h2d_t [1] | Output port for window |
| tl_win_i | in | tl_d2h_t [1] | |
| reg2hw | out | hmac_reg2hw_t | Write |
| hw2reg | in | hmac_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Create Socket_1n
Fhmac_done: 0:0
Ffifo_empty: 1:1
Fhmac_err: 2:2
Fhmac_done: 0:0
Ffifo_empty: 1:1
Fhmac_err: 2:2
Fhmac_done: 0:0
Ffifo_empty: 1:1
Fhmac_err: 2:2
Fhmac_en: 0:0
Fsha_en: 1:1
Fendian_swap: 2:2
Fdigest_swap: 3:3
Fhash_start: 0:0
Fhash_process: 1:1
Ffifo_empty: 0:0
Ffifo_full: 1:1
Ffifo_depth: 8:4
This design unit is implemented in i2c_core.sv
This file depends on: i2c_reg_pkg.sv, i2c_fsm.sv, prim_fifo_sync.sv, prim_intr_hw.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| reg2hw | in | i2c_reg2hw_t | |
| hw2reg | out | i2c_hw2reg_t | |
| scl_i | in | logic | |
| scl_o | out | logic | |
| sda_i | in | logic | |
| sda_o | out | logic | |
| intr_fmt_watermark_o | out | logic | |
| intr_rx_watermark_o | out | logic | |
| intr_fmt_overflow_o | out | logic | |
| intr_rx_overflow_o | out | logic | |
| intr_nak_o | out | logic | |
| intr_scl_interference_o | out | logic | |
| intr_sda_interference_o | out | logic | |
| intr_stretch_timeout_o | out | logic | |
| intr_sda_unstable_o | out | logic | |
| intr_trans_complete_o | out | logic | |
| intr_tx_empty_o | out | logic | |
| intr_tx_nonempty_o | out | logic | |
| intr_tx_overflow_o | out | logic | |
| intr_acq_overflow_o | out | logic | |
| intr_ack_stop_o | out | logic | |
| intr_host_timeout_o | out | logic |
This design unit is implemented in i2c_reg_pkg.sv
This design unit is implemented in i2c_reg_top.sv
This file depends on: prim_subreg_ext.sv, i2c_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 7 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | i2c_reg2hw_t | Write |
| hw2reg | in | i2c_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Ffmt_watermark: 0:0
Frx_watermark: 1:1
Ffmt_overflow: 2:2
Frx_overflow: 3:3
Fnak: 4:4
Fscl_interference: 5:5
Fsda_interference: 6:6
Fstretch_timeout: 7:7
Fsda_unstable: 8:8
Ftrans_complete: 9:9
Ftx_empty: 10:10
Ftx_nonempty: 11:11
Ftx_overflow: 12:12
Facq_overflow: 13:13
Fack_stop: 14:14
Fhost_timeout: 15:15
Ffmt_watermark: 0:0
Frx_watermark: 1:1
Ffmt_overflow: 2:2
Frx_overflow: 3:3
Fnak: 4:4
Fscl_interference: 5:5
Fsda_interference: 6:6
Fstretch_timeout: 7:7
Fsda_unstable: 8:8
Ftrans_complete: 9:9
Ftx_empty: 10:10
Ftx_nonempty: 11:11
Ftx_overflow: 12:12
Facq_overflow: 13:13
Fack_stop: 14:14
Fhost_timeout: 15:15
Ffmt_watermark: 0:0
Frx_watermark: 1:1
Ffmt_overflow: 2:2
Frx_overflow: 3:3
Fnak: 4:4
Fscl_interference: 5:5
Fsda_interference: 6:6
Fstretch_timeout: 7:7
Fsda_unstable: 8:8
Ftrans_complete: 9:9
Ftx_empty: 10:10
Ftx_nonempty: 11:11
Ftx_overflow: 12:12
Facq_overflow: 13:13
Fack_stop: 14:14
Fhost_timeout: 15:15
Fenablehost: 0:0
Fenabletarget: 1:1
Ffmtfull: 0:0
Frxfull: 1:1
Ffmtempty: 2:2
Fhostidle: 3:3
Ftargetidle: 4:4
Frxempty: 5:5
Ftxfull: 6:6
Facqfull: 7:7
Ftxempty: 8:8
Facqempty: 9:9
Ffbyte: 7:0
Fstart: 8:8
Fstop: 9:9
Fread: 10:10
Frcont: 11:11
Fnakok: 12:12
Frxrst: 0:0
Ffmtrst: 1:1
Frxilvl: 4:2
Ffmtilvl: 6:5
Facqrst: 7:7
Ftxrst: 8:8
Ffmtlvl: 5:0
Ftxlvl: 13:8
Frxlvl: 21:16
Facqlvl: 29:24
Ftxovrden: 0:0
Fsclval: 1:1
Fsdaval: 2:2
Fscl_rx: 15:0
Fsda_rx: 31:16
Fthigh: 15:0
Ftlow: 31:16
Ft_r: 15:0
Ft_f: 31:16
Ftsu_sta: 15:0
Fthd_sta: 31:16
Ftsu_dat: 15:0
Fthd_dat: 31:16
Ftsu_sto: 15:0
Ft_buf: 31:16
Fval: 30:0
Fen: 31:31
Faddress0: 6:0
Fmask0: 13:7
Faddress1: 20:14
Fmask1: 27:21
Fabyte: 7:0
Fsignal: 9:8
Fenableaddr: 0:0
Fenabletx: 1:1
Fenableacq: 2:2
Fstop: 3:3
This design unit is implemented in ibex_core.sv
This file depends on: ibex_cs_registers.sv, uvm_pkg.sv, prim_clock_gating.sv, ibex_ex_block.sv, ibex_pmp.sv, ibex_register_file_ff.sv, ibex_pkg.sv, ibex_wb_stage.sv, ibex_id_stage.sv, ibex_if_stage.sv, prim_secded_39_32_enc.sv, ibex_register_file_fpga.sv, ibex_load_store_unit.sv, prim_secded_39_32_dec.sv, ibex_register_file_latch.sv
Top level module of the ibex RISC-V core
| Name | Type | Default Value | Description |
|---|---|---|---|
| PMPEnable | bit | 1'b0 | |
| PMPGranularity | int | 0 | |
| PMPNumRegions | int | 4 | |
| MHPMCounterNum | int | 0 | |
| MHPMCounterWidth | int | 40 | |
| RV32E | bit | 1'b0 | |
| RV32M | rv32m_e | ibex_pkg::RV32MFast | |
| RV32B | rv32b_e | ibex_pkg::RV32BNone | |
| RegFile | regfile_e | ibex_pkg::RegFileFF | |
| BranchTargetALU | bit | 1'b0 | |
| WritebackStage | bit | 1'b0 | |
| ICache | bit | 1'b0 | |
| ICacheECC | bit | 1'b0 | |
| BranchPredictor | bit | 1'b0 | |
| DbgTriggerEn | bit | 1'b0 | |
| DbgHwBreakNum | int | 1 | |
| SecureIbex | bit | 1'b0 | |
| DmHaltAddr | int | 32'h1A110800 | |
| DmExceptionAddr | int | 32'h1A110808 | |
| PMP_NUM_CHAN | int | 2 | |
| DataIndTiming | bit | SecureIbex | |
| DummyInstructions | bit | SecureIbex | |
| PCIncrCheck | bit | SecureIbex | |
| ShadowCSR | bit | SecureIbex | |
| SpecBranch | bit | PMPEnable & (PMPNumRegions == 16) | Speculative branch option, trades-off performance against timing. Setting this to 1 eases branch target critical paths significantly but reduces performance by ~3% (based on CoreMark/MHz score). Set by default in the max PMP config which has the tightest budget for branch target timing. |
| RegFileECC | bit | SecureIbex | |
| RegFileDataWidth | int | RegFileECC ? 32 + 7 : 32 | |
| RVFI_STAGES | int | WritebackStage ? 2 : 1 | When writeback stage is present RVFI information is emitted when instruction is finished in third stage but some information must be captured whilst the instruction is in the second stage. Without writeback stage RVFI information is all emitted when instruction retires in second stage. RVFI outputs are all straight from flops. So 2 stage pipeline requires a single set of flops (instr_info => RVFI_out), 3 stage pipeline requires two sets (instr_info => wb => RVFI_out) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock and Reset |
| rst_ni | in | logic | |
| test_en_i | in | logic | enable all clock gates for testing |
| hart_id_i | in | [31:0] logic | |
| boot_addr_i | in | [31:0] logic | |
| instr_req_o | out | logic | Instruction memory interface |
| instr_gnt_i | in | logic | |
| instr_rvalid_i | in | logic | |
| instr_addr_o | out | [31:0] logic | |
| instr_rdata_i | in | [31:0] logic | |
| instr_err_i | in | logic | |
| data_req_o | out | logic | Data memory interface |
| data_gnt_i | in | logic | |
| data_rvalid_i | in | logic | |
| data_we_o | out | logic | |
| data_be_o | out | [3:0] logic | |
| data_addr_o | out | [31:0] logic | |
| data_wdata_o | out | [31:0] logic | |
| data_rdata_i | in | [31:0] logic | |
| data_err_i | in | logic | |
| irq_software_i | in | logic | Interrupt inputs |
| irq_timer_i | in | logic | |
| irq_external_i | in | logic | |
| irq_fast_i | in | [14:0] logic | |
| irq_nm_i | in | logic | non-maskeable interrupt |
| debug_req_i | in | logic | Debug Interface |
| rvfi_valid | out | logic | |
| rvfi_order | out | [63:0] logic | |
| rvfi_insn | out | [31:0] logic | |
| rvfi_trap | out | logic | |
| rvfi_halt | out | logic | |
| rvfi_intr | out | logic | |
| rvfi_mode | out | [1:0] logic | |
| rvfi_ixl | out | [1:0] logic | |
| rvfi_rs1_addr | out | [4:0] logic | |
| rvfi_rs2_addr | out | [4:0] logic | |
| rvfi_rs3_addr | out | [4:0] logic | |
| rvfi_rs1_rdata | out | [31:0] logic | |
| rvfi_rs2_rdata | out | [31:0] logic | |
| rvfi_rs3_rdata | out | [31:0] logic | |
| rvfi_rd_addr | out | [4:0] logic | |
| rvfi_rd_wdata | out | [31:0] logic | |
| rvfi_pc_rdata | out | [31:0] logic | |
| rvfi_pc_wdata | out | [31:0] logic | |
| rvfi_mem_addr | out | [31:0] logic | |
| rvfi_mem_rmask | out | [3:0] logic | |
| rvfi_mem_wmask | out | [3:0] logic | |
| rvfi_mem_rdata | out | [31:0] logic | |
| rvfi_mem_wdata | out | [31:0] logic | |
| fetch_enable_i | in | logic | CPU Control Signals |
| alert_minor_o | out | logic | |
| alert_major_o | out | logic | |
| core_sleep_o | out | logic |
main clock gate of the core generates all clocks except the one for the debug unit which is independent
This design unit is implemented in ibex_tracer.sv
This file depends on: ibex_tracer_pkg.sv
Trace executed instructions in simulation
This tracer takes execution information from the RISC-V Verification Interface (RVFI) and
produces a text file with a human-readable trace.
All traced instructions are written to a log file. By default, the log file is named
trace_core_.log, with being the 8 digit hart ID of the core being traced.
The file name base, defaulting to "trace_core" can be set using the "ibex_tracer_file_base"
plusarg passed to the simulation, e.g. "+ibex_tracer_file_base=ibex_my_trace". The exact syntax
of passing plusargs to a simulation depends on the simulator.
The creation of the instruction trace is enabled by default but can be disabled for a simulation.
This behaviour is controlled by the plusarg "ibex_tracer_enable". Use "ibex_tracer_enable=0" to
disable the tracer.
The trace contains six columns, separated by tabs:
The simulation time
The clock cycle count since reset
The program counter (PC)
The instruction
The decoded instruction in the same format as objdump, together with the accessed registers and
read/written memory values. Jumps and branches show the target address.
This column may be omitted if the instruction does not decode into a long form.
Accessed registers and memory locations.
Significant effort is spent to make the decoding produced by this tracer as similar as possible
to the one produced by objdump. This simplifies the correlation between the static program
information from the objdump-generated disassembly, and the runtime information from this tracer.
| Name | Type | Default Value | Description |
|---|---|---|---|
| RS1 | [4:0] logic | (1 << 0) | Data items accessed during this instruction |
| RS2 | [4:0] logic | (1 << 1) | |
| RS3 | [4:0] logic | (1 << 2) | |
| RD | [4:0] logic | (1 << 3) | |
| MEM | [4:0] logic | (1 << 4) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| hart_id_i | in | [31:0] logic | |
| rvfi_valid | in | logic | RVFI as described at https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md The standard interface does not have _i/_o suffixes. For consistency with the standard the signals in this module don't have the suffixes either. |
| rvfi_order | in | [63:0] logic | |
| rvfi_insn | in | [31:0] logic | |
| rvfi_trap | in | logic | |
| rvfi_halt | in | logic | |
| rvfi_intr | in | logic | |
| rvfi_mode | in | [1:0] logic | |
| rvfi_ixl | in | [1:0] logic | |
| rvfi_rs1_addr | in | [4:0] logic | |
| rvfi_rs2_addr | in | [4:0] logic | |
| rvfi_rs3_addr | in | [4:0] logic | |
| rvfi_rs1_rdata | in | [31:0] logic | |
| rvfi_rs2_rdata | in | [31:0] logic | |
| rvfi_rs3_rdata | in | [31:0] logic | |
| rvfi_rd_addr | in | [4:0] logic | |
| rvfi_rd_wdata | in | [31:0] logic | |
| rvfi_pc_rdata | in | [31:0] logic | |
| rvfi_pc_wdata | in | [31:0] logic | |
| rvfi_mem_addr | in | [31:0] logic | |
| rvfi_mem_rmask | in | [3:0] logic | |
| rvfi_mem_wmask | in | [3:0] logic | |
| rvfi_mem_rdata | in | [31:0] logic | |
| rvfi_mem_wdata | in | [31:0] logic |
This design unit is implemented in io_osc.sv
of io_osc
| Name | Type | Default Value | Description |
|---|---|---|---|
| IO_EN_RDLY | time | 5us | |
| IoClkPeriod | real | 1000000/96 | ~10416.666667ps (96Mhz) |
| Name | Direction | Type | Description |
|---|---|---|---|
| vcore_pok_h_i | in | logic | VCORE POK @3.3V |
| io_en_i | in | logic | IO Source Clock Enable |
| io_clk_o | out | logic | IO Clock Output |
This design unit is implemented in keymgr_cfg_en.sv
keymgr_cfg_en
| Name | Type | Default Value | Description |
|---|---|---|---|
| NonInitClr | bit | 1'b1 | controls whether clear has an effect on output value during non-init |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| init_i | in | logic | |
| en_i | in | logic | |
| set_i | in | logic | |
| clr_i | in | logic | |
| out_o | out | logic |
This design unit is implemented in keymgr_ctrl.sv
This file depends on: prim_flop_2sync.sv, uvm_pkg.sv, keymgr_pkg.sv, otp_ctrl_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| EntropyWidth | int | LfsrWidth / 2 | |
| EntropyRounds | int | KeyWidth / EntropyWidth | |
| CntWidth | int | $clog2(EntropyRounds) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| en_i | in | logic | lifecycle enforcement |
| op_start_i | in | logic | Software interface |
| op_i | in | keymgr_ops_e | |
| op_done_o | out | logic | |
| status_o | out | keymgr_op_status_e | |
| error_o | out | [ErrLastPos-1:0] logic | |
| data_en_o | out | logic | |
| data_valid_o | out | logic | |
| wipe_key_o | out | logic | |
| working_state_o | out | keymgr_working_state_e | |
| sw_binding_unlock_o | out | logic | |
| init_o | out | logic | |
| root_key_i | in | otp_keymgr_key_t | Data input |
| hw_sel_o | out | keymgr_gen_out_e | |
| stage_sel_o | out | keymgr_stage_e | |
| adv_en_o | out | logic | KMAC ctrl interface |
| id_en_o | out | logic | |
| gen_en_o | out | logic | |
| key_o | out | hw_key_req_t | |
| load_key_o | out | logic | |
| kmac_done_i | in | logic | |
| kmac_input_invalid_i | in | logic | asserted when selected data fails criteria check |
| kmac_fsm_err_i | in | logic | asserted when kmac fsm reaches unexpected state |
| kmac_op_err_i | in | logic | asserted when kmac itself reports an error |
| kmac_cmd_err_i | in | logic | asserted when more than one command given to kmac |
| kmac_data_i | in | [KeyWidth-1:0] [Shares-1:0] logic | |
| entropy_i | in | [RandWidth-1:0] [Shares-1:0] logic | prng control interface |
| prng_reseed_ack_i | in | logic | |
| prng_reseed_req_o | out | logic | |
| prng_en_o | out | logic |
This design unit is implemented in keymgr_input_checks.sv
This file depends on: keymgr_pkg.sv
keymgr_input_checks
| Name | Direction | Type | Description |
|---|---|---|---|
| max_key_versions_i | in | [31:0] [2**StageWidth-1:0] logic | |
| stage_sel_i | in | keymgr_stage_e | |
| key_i | in | hw_key_req_t | |
| key_version_i | in | [31:0] logic | |
| creator_seed_i | in | [KeyWidth-1:0] logic | |
| owner_seed_i | in | [KeyWidth-1:0] logic | |
| devid_i | in | [DevIdWidth-1:0] logic | |
| health_state_i | in | [HealthStateWidth-1:0] logic | |
| creator_seed_vld_o | out | logic | |
| owner_seed_vld_o | out | logic | |
| devid_vld_o | out | logic | |
| health_state_vld_o | out | logic | |
| key_version_vld_o | out | logic | |
| key_vld_o | out | logic |
This design unit is implemented in keymgr_kmac_if.sv
This file depends on: uvm_pkg.sv, keymgr_pkg.sv
keymgr_kmac_if
| Name | Type | Default Value | Description |
|---|---|---|---|
| AdvRem | int | AdvDataWidth % KmacDataIfWidth | |
| IdRem | int | IdDataWidth % KmacDataIfWidth | |
| GenRem | int | GenDataWidth % KmacDataIfWidth | |
| AdvRounds | int | AdvDataWidth / KmacDataIfWidth + (AdvRem > 0) | Number of kmac transactions required |
| IdRounds | int | IdDataWidth / KmacDataIfWidth + (IdRem > 0) | |
| GenRounds | int | GenDataWidth / KmacDataIfWidth + (GenRem > 0) | |
| MaxRounds | int | KDFMaxWidth / KmacDataIfWidth | |
| AdvWidth | int | KmacDataIfWidth * AdvRounds | Total transmitted bits, this is the same as *DataWidth if it all fits into kmac data interface |
| IdWidth | int | KmacDataIfWidth * IdRounds | |
| GenWidth | int | KmacDataIfWidth * GenRounds | |
| CntWidth | int | $clog2(MaxRounds) | calculated parameters for number of roudns and interface width |
| IfBytes | int | KmacDataIfWidth / 8 | |
| DecoyCopies | int | KmacDataIfWidth / 32 | |
| DecoyOutputCopies | int | (KeyWidth / 32) * Shares | |
| AdvByteMask | [IfBytes-1:0] logic | (AdvRem > 0) ? (2**(AdvRem/8)-1) : {IfBytes{1'b1}} | byte mask for the last transfer |
| IdByteMask | [IfBytes-1:0] logic | (IdRem > 0) ? (2**(IdRem/8)-1) : {IfBytes{1'b1}} | |
| GenByteMask | [IfBytes-1:0] logic | (GenRem > 0) ? (2**(GenRem/8)-1) : {IfBytes{1'b1}} |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| adv_data_i | in | [AdvDataWidth-1:0] logic | data input interfaces |
| id_data_i | in | [IdDataWidth-1:0] logic | |
| gen_data_i | in | [GenDataWidth-1:0] logic | |
| inputs_invalid_i | in | [3:0] logic | |
| inputs_invalid_o | out | logic | |
| adv_en_i | in | logic | keymgr control to select appropriate inputs |
| id_en_i | in | logic | |
| gen_en_i | in | logic | |
| done_o | out | logic | |
| data_o | out | [KeyWidth-1:0] [Shares-1:0] logic | |
| kmac_data_o | out | kmac_data_req_t | actual connection to kmac |
| kmac_data_i | in | kmac_data_rsp_t | |
| prng_en_o | out | logic | entropy input |
| entropy_i | in | [RandWidth-1:0] [Shares-1:0] logic | |
| fsm_error_o | out | logic | error outputs |
| kmac_error_o | out | logic | |
| cmd_error_o | out | logic |
This design unit is implemented in keymgr_reg_pkg.sv
This design unit is implemented in keymgr_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, keymgr_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 8 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | keymgr_reg2hw_t | Write |
| hw2reg | in | keymgr_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Ffatal_fault_err: 0:0
Frecov_operation_err: 1:1
Fstart: 0:0
Foperation: 6:4
Fdest_sel: 13:12
Finvalid_op: 0:0
Finvalid_cmd: 1:1
Finvalid_kmac_input: 2:2
Finvalid_kmac_data: 3:3
This design unit is implemented in keymgr_reseed_ctrl.sv
This file depends on: keymgr_pkg.sv, prim_sync_reqack.sv, prim_util_pkg.sv, edn_pkg.sv
keymgr_reseed_ctrl
| Name | Type | Default Value | Description |
|---|---|---|---|
| EdnRounds | int | LfsrWidth / EdnWidth | |
| EdnCntWidth | int | prim_util_pkg::vbits(EdnRounds) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clk_edn_i | in | logic | |
| rst_edn_ni | in | logic | |
| reseed_req_i | in | logic | interface to keymgr_ctrl |
| reseed_ack_o | out | logic | |
| reseed_interval_i | in | [15:0] logic | interface to software |
| edn_o | out | edn_req_t | interface to edn |
| edn_i | in | edn_rsp_t | |
| seed_en_o | out | logic | interface to lfsr |
| seed_o | out | [LfsrWidth-1:0] logic |
req/ack interface to edn
This design unit is implemented in keymgr_sideload_key_ctrl.sv
This file depends on: keymgr_sideload_key.sv, uvm_pkg.sv, keymgr_pkg.sv
keymgr_sideload_key_ctrl
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| init_i | in | logic | |
| clr_key_i | in | logic | clear key just deletes the key |
| wipe_key_i | in | logic | wipe key deletes and renders sideloads useless until reboot |
| entropy_i | in | [RandWidth-1:0] [Shares-1:0] logic | |
| dest_sel_i | in | keymgr_key_dest_e | |
| key_sel_i | in | keymgr_gen_out_e | |
| load_key_i | in | logic | |
| data_en_i | in | logic | |
| data_valid_i | in | logic | |
| key_i | in | hw_key_req_t | |
| data_i | in | [KeyWidth-1:0] [Shares-1:0] logic | |
| prng_en_o | out | logic | |
| aes_key_o | out | hw_key_req_t | |
| hmac_key_o | out | hw_key_req_t | |
| kmac_key_o | out | hw_key_req_t |
This design unit is implemented in kmac_core.sv
This file depends on: prim_slicer.sv, kmac_pkg.sv, uvm_pkg.sv, sha3_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| EnMasking | bit | 0 | EnMasking: Enable masking security hardening inside keccak_round If it is enabled, the result digest will be two set of 1600bit. |
| Share | int | (EnMasking) ? 2 : 1 | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| fifo_valid_i | in | logic | From Message FIFO |
| fifo_data_i | in | [MsgWidth-1:0] logic [Share] | |
| fifo_strb_i | in | [MsgStrbW-1:0] logic | |
| fifo_ready_o | out | logic | |
| msg_valid_o | out | logic | to SHA3 Core |
| msg_data_o | out | [MsgWidth-1:0] logic [Share] | |
| msg_strb_o | out | [MsgStrbW-1:0] logic | |
| msg_ready_i | in | logic | |
| kmac_en_i | in | logic | If kmac_en is cleared, Core logic doesn't function but forward incoming mesage to SHA3 core |
| mode_i | in | sha3_mode_e | |
| strength_i | in | keccak_strength_e | |
| key_data_i | in | [MaxKeyLen-1:0] logic [Share] | Key input from CSR |
| key_len_i | in | key_len_e | |
| start_i | in | logic | Controls : same to SHA3 core |
| process_i | in | logic | |
| done_i | in | logic | |
| process_o | out | logic | Control to SHA3 core |
This design unit is implemented in kmac_entropy.sv
This file depends on: kmac_pkg.sv, uvm_pkg.sv, sha3_pkg.sv, prim_lfsr.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| EntropyLfsrW | int | 64 | storage width |
| EntropyStorageW | int | 320 | |
| EntropyMultiply | int | sha3_pkg::StateW / EntropyStorageW | |
| StorageEntries | int | EntropyStorageW / EntropyLfsrW | |
| StorageIndexW | int | $clog2(StorageEntries) | |
| TimerW | int | (EntropyTimerW > EdnWaitTimerW) ? EntropyTimerW : EdnWaitTimerW |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| entropy_req_o | out | logic | EDN interface |
| entropy_ack_i | in | logic | |
| entropy_data_i | in | [MsgWidth-1:0] logic | |
| rand_valid_o | out | logic | Entropy to internal |
| rand_data_o | out | [sha3_pkg::StateW-1:0] logic | |
| rand_consumed_i | in | logic | |
| in_progress_i | in | logic | Status |
| in_keyblock_i | in | logic | |
| mode_i | in | entropy_mode_e | Configurations |
| entropy_ready_i | in | logic | // SW sets ready bit when EDN is ready to accept requests through its app. // interface. |
| fast_process_i | in | logic | // Garbage random value when not processing Keyblock, if this config is // turned on, the logic sending garbage value and never de-assert // rand_valid_o unless it is not processing KeyBlock. |
| seed_update_i | in | logic | // SW update of seed |
| seed_data_i | in | [63:0] logic | |
| entropy_timer_limit_i | in | [EntropyTimerW-1:0] logic | // Timer limit value // If value is 0, timer is disabled |
| wait_timer_limit_i | in | [EdnWaitTimerW-1:0] logic | |
| err_o | out | err_t | Error output |
| err_processed_i | in | logic |
This design unit is implemented in kmac_keymgr.sv
This file depends on: kmac_pkg.sv, uvm_pkg.sv, sha3_pkg.sv, keymgr_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| EnMasking | int | 0 | |
| Share | int | (EnMasking) ? 2 : 1 | derived parameter |
| KeyMgrKeyW | int | $bits(keymgr_key_i.key_share0) | Digest width is same to the key width |
| KeyMgrDigestW | int | $bits(keymgr_data_o.digest_share0) | |
| KeyLen | key_len_e [5] | '{Key128, Key192, Key256, Key384, Key512} | |
| SelKeySize | int | (KeyMgrDigestW == 128) ? 0 : (KeyMgrDigestW == 192) ? 1 : (KeyMgrDigestW == 256) ? 2 : (KeyMgrDigestW == 384) ? 3 : (KeyMgrDigestW == 512) ? 4 : 0 | |
| SideloadedKey | key_len_e | KeyLen[SelKeySize] | |
| OutLenW | int | 24 | Define right_encode(outlen) value here Look at kmac_pkg::key_len_e for the kinds of key size These values should be exactly the same as the key length encodings in kmac_core.sv, with the only difference being that the byte representing the byte-length of the encoded value is in the MSB position due to right encoding instead of in the LSB position (left encoding). |
| EncodedOutLen | [OutLenW-1:0] logic [5] | '{ 24'h 0001_80, 24'h 0001_C0, 24'h 02_0001, 24'h 02_8001, 24'h 02_0002 } | |
| EncodedOutLenMask | [OutLenW-1:0] logic [5] | '{ 24'h 00FFFF, 24'h 00FFFF, 24'h FFFFFF, 24'h FFFFFF, 24'h FFFFFF } |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| reg_key_data_i | in | [MaxKeyLen-1:0] logic [Share] | Secret Key from register |
| reg_key_len_i | in | key_len_e | |
| sw_valid_i | in | logic | Data from Software |
| sw_data_i | in | [MsgWidth-1:0] logic | |
| sw_mask_i | in | [MsgWidth-1:0] logic | |
| sw_ready_o | out | logic | |
| keymgr_key_i | in | hw_key_req_t | KeyMgr Sideload Key interface |
| keymgr_data_i | in | kmac_data_req_t | KeyMgr Data in/ Digest out interface + control signals |
| keymgr_data_o | out | kmac_data_rsp_t | |
| key_data_o | out | [MaxKeyLen-1:0] logic [Share] | to KMAC Core: Secret key |
| key_len_o | out | key_len_e | |
| kmac_valid_o | out | logic | to MSG_FIFO |
| kmac_data_o | out | [MsgWidth-1:0] logic | |
| kmac_mask_o | out | [MsgWidth-1:0] logic | |
| kmac_ready_i | in | logic | |
| keccak_state_valid_i | in | logic | STATE from SHA3 Core |
| keccak_state_i | in | [sha3_pkg::StateW-1:0] logic [Share] | |
| reg_state_valid_o | out | logic | to STATE TL-window if KeyMgr KDF is not enabled, the incoming state goes to register if kdf_en is set, the state value goes to KeyMgr and the output to the register is all zero. |
| reg_state_o | out | [sha3_pkg::StateW-1:0] logic [Share] | |
| keymgr_key_en_i | in | logic | Configurations If key_en is set, the logic uses KeyMgr's sideloaded key as a secret key rather than register values. This only affects when software initiates. If KeyMgr initiates the hash operation, it always uses sideloaded key. |
| sw_cmd_i | in | kmac_cmd_e | Commands Command from software |
| absorbed_i | in | logic | from SHA3 |
| cmd_o | out | kmac_cmd_e | to KMAC |
| absorbed_o | out | logic | to SW |
| error_i | in | logic | Error input This error comes from KMAC/SHA3 engine. KeyMgr interface delivers the error signal to KeyMgr to drop the current op and re-initiate. If error happens, regardless of SW-initiated or KeyMgr-initiated, the error is reported to the ERR_CODE so that SW can look into. |
| error_o | out | err_t | error_o value is pushed to Error FIFO at KMAC/SHA3 top and reported to SW |
This design unit is implemented in kmac_msgfifo.sv
This file depends on: kmac_pkg.sv, uvm_pkg.sv, prim_fifo_sync.sv, prim_packer.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| OutWidth | int | 64 | OutWidth is MsgFIFO data width. prim_packer converts InW to OutW prior to pushing to MsgFIFO |
| MsgDepth | int | 9 | Internal MsgFIFO Entry count |
| MsgDepthW | int | $clog2(MsgDepth+1) | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| fifo_valid_i | in | logic | from REG or KeyMgr Intf input |
| fifo_data_i | in | [OutWidth-1:0] logic | |
| fifo_mask_i | in | [OutWidth-1:0] logic | |
| fifo_ready_o | out | logic | |
| msg_valid_o | out | logic | MSG interface |
| msg_data_o | out | [OutWidth-1:0] logic | |
| msg_strb_o | out | [OutWidth/8-1:0] logic | |
| msg_ready_i | in | logic | |
| fifo_empty_o | out | logic | |
| fifo_full_o | out | logic | |
| fifo_depth_o | out | [MsgDepthW-1:0] logic | |
| clear_i | in | logic | Control |
| process_i | in | logic | process_i --> process_o process_o asserted after all internal messages are flushed out to MSG interface |
| process_o | out | logic |
This design unit is implemented in kmac_pkg.sv
This file depends on: sha3_pkg.sv
This design unit is implemented in kmac_reg_pkg.sv
This design unit is implemented in kmac_reg_top.sv
This file depends on: prim_subreg_ext.sv, kmac_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 12 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| tl_win_o | out | tl_h2d_t [2] | Output port for window |
| tl_win_i | in | tl_d2h_t [2] | |
| reg2hw | out | kmac_reg2hw_t | Write |
| hw2reg | in | kmac_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Create Socket_1n
Fkmac_done: 0:0
Ffifo_empty: 1:1
Fkmac_err: 2:2
Fkmac_done: 0:0
Ffifo_empty: 1:1
Fkmac_err: 2:2
Fkmac_done: 0:0
Ffifo_empty: 1:1
Fkmac_err: 2:2
Fkmac_en: 0:0
Fkstrength: 3:1
Fmode: 5:4
Fmsg_endianness: 8:8
Fstate_endianness: 9:9
Fsideload: 12:12
Fentropy_mode: 17:16
Fentropy_fast_process: 19:19
Fentropy_ready: 24:24
Ferr_processed: 25:25
Fsha3_idle: 0:0
Fsha3_absorb: 1:1
Fsha3_squeeze: 2:2
Ffifo_depth: 12:8
Ffifo_empty: 14:14
Ffifo_full: 15:15
Fentropy_timer: 15:0
Fwait_timer: 31:16
This design unit is implemented in kmac_staterd.sv
This file depends on: tlul_adapter_sram.sv, prim_slicer.sv, kmac_pkg.sv, sha3_pkg.sv, tlul_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AddrW | int | 9 | TL-UL Address Width. Should be bigger than $clog2(kmac_pkg::StateW) * Share |
| EnMasking | int | 0 | EnMasking: Enable masking security hardening inside keccak_round If it is enabled, the result digest will be two set of 1600bit. |
| Share | int | (EnMasking) ? 2 : 1 | derived parameter |
| StateAddrW | int | $clog2(sha3_pkg::StateW/32) | |
| SelAddrW | int | AddrW-2-StateAddrW |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | |
| tl_o | out | tl_d2h_t | |
| state_i | in | [sha3_pkg::StateW-1:0] logic [Share] | State in |
| endian_swap_i | in | logic | Config |
TL Adapter
This design unit is implemented in lc_ctrl_fsm.sv
This file depends on: prim_flop.sv, prim_lc_sender.sv, uvm_pkg.sv, lc_ctrl_state_pkg.sv, lc_ctrl_state_transition.sv, lc_ctrl_signal_decode.sv, lc_ctrl_pkg.sv, lc_ctrl_state_decode.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RndCnstLcKeymgrDivInvalid | lc_keymgr_div_t | LcKeymgrDivWidth'(0) | |
| RndCnstLcKeymgrDivTestDevRma | lc_keymgr_div_t | LcKeymgrDivWidth'(1) | |
| RndCnstLcKeymgrDivProduction | lc_keymgr_div_t | LcKeymgrDivWidth'(2) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | This module is combinational, but we need the clock and reset for the assertions. |
| rst_ni | in | logic | |
| init_req_i | in | logic | Initialization request from power manager. |
| init_done_o | out | logic | |
| idle_o | out | logic | |
| esc_scrap_state_i | in | logic | Escalatio input |
| esc_wipe_secrets_i | in | logic | |
| lc_state_valid_i | in | logic | Life cycle state vector from OTP. |
| lc_state_i | in | lc_state_e | |
| lc_id_state_i | in | lc_id_state_e | |
| lc_cnt_i | in | lc_cnt_e | |
| test_unlock_token_i | in | lc_token_t | Token input from OTP (these are all hash post-images). |
| test_exit_token_i | in | lc_token_t | |
| rma_token_i | in | lc_token_t | |
| trans_cmd_i | in | logic | Transition trigger interface. |
| trans_target_i | in | dec_lc_state_e | |
| dec_lc_state_o | out | dec_lc_state_e | Decoded life cycle state for CSRs. |
| dec_lc_cnt_o | out | dec_lc_cnt_t | |
| dec_lc_id_state_o | out | dec_lc_id_state_e | |
| token_hash_req_o | out | logic | Token hashing interface |
| token_hash_ack_i | in | logic | |
| hashed_token_i | in | lc_token_t | |
| otp_prog_req_o | out | logic | OTP programming interface |
| otp_prog_lc_state_o | out | lc_state_e | |
| otp_prog_lc_cnt_o | out | lc_cnt_e | |
| otp_prog_ack_i | in | logic | |
| otp_prog_err_i | in | logic | |
| trans_success_o | out | logic | Error outputs going to CSRs |
| trans_cnt_oflw_error_o | out | logic | |
| trans_invalid_error_o | out | logic | |
| token_invalid_error_o | out | logic | |
| flash_rma_error_o | out | logic | |
| otp_prog_error_o | out | logic | |
| state_invalid_error_o | out | logic | |
| lc_dft_en_o | out | lc_tx_t | Life cycle broadcast outputs. |
| lc_nvm_debug_en_o | out | lc_tx_t | |
| lc_hw_debug_en_o | out | lc_tx_t | |
| lc_cpu_en_o | out | lc_tx_t | |
| lc_creator_seed_sw_rw_en_o | out | lc_tx_t | |
| lc_owner_seed_sw_rw_en_o | out | lc_tx_t | |
| lc_iso_part_sw_rd_en_o | out | lc_tx_t | |
| lc_iso_part_sw_wr_en_o | out | lc_tx_t | |
| lc_seed_hw_rd_en_o | out | lc_tx_t | |
| lc_keymgr_en_o | out | lc_tx_t | |
| lc_escalate_en_o | out | lc_tx_t | |
| lc_check_byp_en_o | out | lc_tx_t | |
| lc_clk_byp_req_o | out | lc_tx_t | |
| lc_clk_byp_ack_i | in | lc_tx_t | |
| lc_flash_rma_req_o | out | lc_tx_t | Request and feedback to/from flash controller |
| lc_flash_rma_ack_i | in | lc_tx_t | |
| lc_keymgr_div_o | out | lc_keymgr_div_t | State group diversification value for keymgr |
This decodes the state into a format that can be exposed in the CSRs, and flags any errors in the state encoding. Errors will move the main FSM into INVALID right away.
LC transition checker logic and next state generation.
LC signal decoder and broadcasting logic.
Conditional signals set by main FSM.
This design unit is implemented in lc_ctrl_reg_pkg.sv
This design unit is implemented in lc_ctrl_reg_top.sv
This file depends on: prim_subreg_ext.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, lc_ctrl_reg_pkg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 7 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | lc_ctrl_reg2hw_t | Write |
| hw2reg | in | lc_ctrl_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Ffatal_prog_error: 0:0
Ffatal_state_error: 1:1
Fready: 0:0
Ftransition_successful: 1:1
Ftransition_count_error: 2:2
Ftransition_error: 3:3
Ftoken_error: 4:4
Fflash_rma_error: 5:5
Fotp_error: 6:6
Fstate_error: 7:7
Fotp_partition_error: 8:8
This design unit is implemented in otbn_core.sv
This file depends on: otbn_decoder.sv, otbn_controller.sv, otbn_rf_base.sv, otbn_mac_bignum.sv, otbn_rf_bignum_fpga.sv, otbn_instruction_fetch.sv, prim_util_pkg.sv, otbn_alu_bignum.sv, otbn_lsu.sv, otbn_rf_bignum_ff.sv, otbn_pkg.sv, otbn_alu_base.sv
OpenTitan Big Number Accelerator (OTBN) Core
This module is the top-level of the OTBN processing core.
| Name | Type | Default Value | Description |
|---|---|---|---|
| RegFile | regfile_e | RegFileFF | Register file implementation selection, see otbn_pkg.sv. |
| ImemSizeByte | int | 4096 | Size of the instruction memory, in bytes |
| DmemSizeByte | int | 4096 | Size of the data memory, in bytes |
| ImemAddrWidth | int | prim_util_pkg::vbits(ImemSizeByte) | |
| DmemAddrWidth | int | prim_util_pkg::vbits(DmemSizeByte) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| start_i | in | logic | start the operation |
| done_o | out | logic | operation done |
| err_bits_o | out | err_bits_t | valid when done_o is asserted |
| start_addr_i | in | [ImemAddrWidth-1:0] logic | start byte address in IMEM |
| imem_req_o | out | logic | Instruction memory (IMEM) |
| imem_addr_o | out | [ImemAddrWidth-1:0] logic | |
| imem_wdata_o | out | [31:0] logic | |
| imem_rdata_i | in | [31:0] logic | |
| imem_rvalid_i | in | logic | |
| imem_rerror_i | in | logic | |
| dmem_req_o | out | logic | Data memory (DMEM) |
| dmem_write_o | out | logic | |
| dmem_addr_o | out | [DmemAddrWidth-1:0] logic | |
| dmem_wdata_o | out | [WLEN-1:0] logic | |
| dmem_wmask_o | out | [WLEN-1:0] logic | |
| dmem_rdata_i | in | [WLEN-1:0] logic | |
| dmem_rvalid_i | in | logic | |
| dmem_rerror_i | in | logic | |
| edn_req_o | out | logic | Entropy distribution network (EDN) |
| edn_ack_i | in | logic | |
| edn_data_i | in | [EdnDataWidth-1:0] logic |
Instruction fetch unit
Instruction decoder
Controller: coordinate between functional units, prepare their inputs (e.g. by muxing between operand sources), and post-process their outputs as needed.
Load store unit: read and write data from data memory
This design unit is implemented in otbn_reg_pkg.sv
This design unit is implemented in otbn_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, otbn_reg_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 16 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| tl_win_o | out | tl_h2d_t [2] | Output port for window |
| tl_win_i | in | tl_d2h_t [2] | |
| reg2hw | out | otbn_reg2hw_t | Write |
| hw2reg | in | otbn_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Create Socket_1n
Ffatal: 0:0
Frecov: 1:1
Fbad_data_addr: 0:0
Fbad_insn_addr: 1:1
Fcall_stack: 2:2
Fillegal_insn: 3:3
Floop: 4:4
Ffatal_imem: 5:5
Ffatal_dmem: 6:6
Ffatal_reg: 7:7
Fimem_error: 0:0
Fdmem_error: 1:1
Freg_error: 2:2
This design unit is implemented in otp_ctrl_dai.sv
This file depends on: prim_flop.sv, uvm_pkg.sv, prim_arbiter_fixed.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, otp_ctrl_reg_pkg.sv, prim_otp_pkg.sv, prim_util_pkg.sv, lc_ctrl_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| CntWidth | int | OtpByteAddrWidth - $clog2(ScrmblBlockWidth/8) | |
| StateWidth | int | 12 | Encoding generated with ./sparse-fsm-encode.py -d 5 -m 20 -n 12 -s 3011551511 Hamming distance histogram: 0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||| (32.11%) 6: |||||||||||||||||||| (35.26%) 7: |||||||| (15.79%) 8: |||||| (11.58%) 9: | (2.11%) 10: (1.05%) 11: | (2.11%) 12: -- Minimum Hamming distance: 5 Maximum Hamming distance: 11 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| init_req_i | in | logic | Init reqest from power manager |
| init_done_o | out | logic | |
| part_init_req_o | out | logic | Init request going to partitions |
| part_init_done_i | in | [NumPart-1:0] logic | |
| escalate_en_i | in | lc_tx_t | Escalation input. This moves the FSM into a terminal state and locks down the DAI. |
| error_o | out | otp_err_e | Output error state of DAI, to be consumed by OTP error/alert logic. Note that most errors are not recoverable and move the DAI FSM into a terminal error state. |
| part_access_i | in | [NumPart-1:0] part_access_t | Access/lock status from partitions |
| dai_addr_i | in | [OtpByteAddrWidth-1:0] logic | CSR interface |
| dai_cmd_i | in | dai_cmd_e | |
| dai_req_i | in | logic | |
| dai_wdata_i | in | [31:0] [NumDaiWords-1:0] logic | |
| dai_idle_o | out | logic | wired to the status CSRs |
| dai_prog_idle_o | out | logic | wired to lfsr timer and pwrmgr |
| dai_cmd_done_o | out | logic | this is used to raise an IRQ |
| dai_rdata_o | out | [31:0] [NumDaiWords-1:0] logic | |
| otp_req_o | out | logic | OTP interface |
| otp_cmd_o | out | cmd_e | |
| otp_size_o | out | [OtpSizeWidth-1:0] logic | |
| otp_wdata_o | out | [OtpIfWidth-1:0] logic | |
| otp_addr_o | out | [OtpAddrWidth-1:0] logic | |
| otp_gnt_i | in | logic | |
| otp_rvalid_i | in | logic | |
| otp_rdata_i | in | [ScrmblBlockWidth-1:0] logic | |
| otp_err_i | in | err_e | |
| scrmbl_mtx_req_o | out | logic | Scrambling mutex request |
| scrmbl_mtx_gnt_i | in | logic | |
| scrmbl_cmd_o | out | otp_scrmbl_cmd_e | Scrambling datapath interface |
| scrmbl_mode_o | out | digest_mode_e | |
| scrmbl_sel_o | out | [ConstSelWidth-1:0] logic | |
| scrmbl_data_o | out | [ScrmblBlockWidth-1:0] logic | |
| scrmbl_valid_o | out | logic | |
| scrmbl_ready_i | in | logic | |
| scrmbl_valid_i | in | logic | |
| scrmbl_data_i | in | [ScrmblBlockWidth-1:0] logic |
This design unit is implemented in otp_ctrl_kdi.sv
This file depends on: prim_flop.sv, uvm_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, otp_ctrl_reg_pkg.sv, prim_util_pkg.sv, lc_ctrl_pkg.sv, prim_arbiter_tree.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumReq | int | 4 + NumSramKeyReqSlots | LC, 2xFlash, OTBN + SRAM slots |
| StateWidth | int | 10 | Encoding generated with:
$ ./sparse-fsm-encode.py -d 5 -m 11 -n 10 Hamming distance histogram: 0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (54.55%) 6: |||||||||||||||| (45.45%) 7: -- 8: -- 9: -- 10: -- Minimum Hamming distance: 5 Maximum Hamming distance: 6 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| kdi_en_i | in | logic | Pulse to enable this module after OTP partitions have been initialized. |
| escalate_en_i | in | lc_tx_t | Escalation input. This moves the FSM into a terminal state. |
| fsm_err_o | out | logic | FSM is in error state |
| scrmbl_key_seed_valid_i | in | logic | Key seed inputs from OTP |
| flash_data_key_seed_i | in | [FlashKeySeedWidth-1:0] logic | |
| flash_addr_key_seed_i | in | [FlashKeySeedWidth-1:0] logic | |
| sram_data_key_seed_i | in | [SramKeySeedWidth-1:0] logic | |
| edn_req_o | out | logic | EDN interface for requesting entropy |
| edn_ack_i | in | logic | |
| edn_data_i | in | [EdnDataWidth-1:0] logic | |
| lc_otp_token_i | in | lc_otp_token_req_t | Lifecycle hashing request |
| lc_otp_token_o | out | lc_otp_token_rsp_t | |
| flash_otp_key_i | in | flash_otp_key_req_t | Scrambling key requests |
| flash_otp_key_o | out | flash_otp_key_rsp_t | |
| sram_otp_key_i | in | [NumSramKeyReqSlots-1:0] sram_otp_key_req_t | |
| sram_otp_key_o | out | [NumSramKeyReqSlots-1:0] sram_otp_key_rsp_t | |
| otbn_otp_key_i | in | otbn_otp_key_req_t | |
| otbn_otp_key_o | out | otbn_otp_key_rsp_t | |
| scrmbl_mtx_req_o | out | logic | Scrambling mutex request |
| scrmbl_mtx_gnt_i | in | logic | |
| scrmbl_cmd_o | out | otp_scrmbl_cmd_e | Scrambling datapath interface |
| scrmbl_mode_o | out | digest_mode_e | |
| scrmbl_sel_o | out | [ConstSelWidth-1:0] logic | |
| scrmbl_data_o | out | [ScrmblBlockWidth-1:0] logic | |
| scrmbl_valid_o | out | logic | |
| scrmbl_ready_i | in | logic | |
| scrmbl_valid_i | in | logic | |
| scrmbl_data_i | in | [ScrmblBlockWidth-1:0] logic |
This design unit is implemented in otp_ctrl_lci.sv
This file depends on: prim_flop.sv, uvm_pkg.sv, lc_ctrl_state_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, otp_ctrl_reg_pkg.sv, prim_otp_pkg.sv, prim_util_pkg.sv, lc_ctrl_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Info | part_info_t | part_info_t'(0) | Lifecycle partition information |
| NumLcOtpWords | int | Info.size >> OtpAddrShift | |
| CntWidth | int | vbits(NumLcOtpWords) | |
| StateWidth | int | 9 | Encoding generated with ./sparse-fsm-encode.py -d 5 -m 5 -n 9 -s 558234734 Hamming distance histogram: 0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (60.00%) 6: ||||||||||||| (40.00%) 7: -- 8: -- 9: -- Minimum Hamming distance: 5 Maximum Hamming distance: 6 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| lci_en_i | in | logic | |
| escalate_en_i | in | lc_tx_t | Escalation input. This moves the FSM into a terminal state and locks down the partition. |
| lc_req_i | in | logic | Life cycle transition request. In order to perform a state transition, the LC controller signals the new count and state. The OTP wrapper then only programs bits that have not been programmed before. Note that a transition request will fail if the request attempts to clear already programmed bits within OTP. |
| lc_state_i | in | lc_state_e | |
| lc_count_i | in | lc_cnt_e | |
| lc_ack_o | out | logic | |
| lc_err_o | out | logic | |
| error_o | out | otp_err_e | Output error state of partition, to be consumed by OTP error/alert logic. Note that most errors are not recoverable and move the partition FSM into a terminal error state. |
| lci_prog_idle_o | out | logic | |
| otp_req_o | out | logic | OTP interface |
| otp_cmd_o | out | cmd_e | |
| otp_size_o | out | [OtpSizeWidth-1:0] logic | |
| otp_wdata_o | out | [OtpIfWidth-1:0] logic | |
| otp_addr_o | out | [OtpAddrWidth-1:0] logic | |
| otp_gnt_i | in | logic | |
| otp_rvalid_i | in | logic | |
| otp_rdata_i | in | [ScrmblBlockWidth-1:0] logic | |
| otp_err_i | in | err_e |
This design unit is implemented in otp_ctrl_lfsr_timer.sv
This file depends on: prim_flop.sv, uvm_pkg.sv, prim_lfsr.sv, otp_ctrl_pkg.sv, otp_ctrl_reg_pkg.sv, lc_ctrl_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| ReseedLfsrWidth | int | 16 | Entropy reseeding is triggered every time this counter expires. |
| RndCnstLfsrSeed | lfsr_seed_t | RndCnstLfsrSeedDefault | Compile time random constants, to be overriden by topgen. |
| RndCnstLfsrPerm | lfsr_perm_t | RndCnstLfsrPermDefault | |
| StateWidth | int | 9 | Encoding generated with ./sparse-fsm-encode.py -d 5 -m 5 -n 9 -s 628816752 Hamming distance histogram: 0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (60.00%) 6: ||||||||||||| (40.00%) 7: -- 8: -- 9: -- Minimum Hamming distance: 5 Maximum Hamming distance: 6 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| edn_req_o | out | logic | request to EDN |
| edn_ack_i | in | logic | ack from EDN |
| edn_data_i | in | [EdnDataWidth-1:0] logic | from EDN |
| timer_en_i | in | logic | enable timer |
| otp_prog_busy_i | in | logic | indicates whether prog ops are in progress |
| integ_chk_trig_i | in | logic | one-off trigger for integrity check |
| cnsty_chk_trig_i | in | logic | one-off trigger for consistency check |
| chk_pending_o | out | logic | indicates whether there are pending checks |
| timeout_i | in | [31:0] logic | check timeout |
| integ_period_msk_i | in | [31:0] logic | maximum integrity check mask |
| cnsty_period_msk_i | in | [31:0] logic | maximum consistency check mask |
| integ_chk_req_o | out | [NumPart-1:0] logic | request to all partitions |
| cnsty_chk_req_o | out | [NumPart-1:0] logic | request to all partitions |
| integ_chk_ack_i | in | [NumPart-1:0] logic | response from partitions |
| cnsty_chk_ack_i | in | [NumPart-1:0] logic | response from partitions |
| escalate_en_i | in | lc_tx_t | escalation input, moves FSM into ErrorSt |
| chk_timeout_o | out | logic | a check has timed out |
| fsm_err_o | out | logic | the FSM has reached an invalid state |
This design unit is implemented in otp_ctrl_part_buf.sv
This file depends on: prim_flop.sv, uvm_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, otp_ctrl_reg_pkg.sv, prim_otp_pkg.sv, prim_util_pkg.sv, prim_buf.sv, lc_ctrl_pkg.sv, otp_ctrl_ecc_reg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Info | part_info_t | part_info_t'(0) | Partition information. |
| DataDefault | [Info.size*8-1:0] logic | '0 | |
| DigestOffset | int | Info.offset + Info.size - ScrmblBlockWidth/8 | |
| NumScrmblBlocks | int | Info.size / (ScrmblBlockWidth/8) | |
| CntWidth | int | vbits(NumScrmblBlocks) | |
| StateWidth | int | 12 | Encoding generated with ./sparse-fsm-encode.py -d 5 -m 16 -n 12 -s 3370657881 Hamming distance histogram: 0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||| (30.00%) 6: |||||||||||||||||||| (32.50%) 7: ||||||||||| (19.17%) 8: ||||||| (11.67%) 9: || (4.17%) 10: | (2.50%) 11: -- 12: -- Minimum Hamming distance: 5 Maximum Hamming distance: 10 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| init_req_i | in | logic | Pulse to start partition initialisation (required once per power cycle). |
| init_done_o | out | logic | |
| integ_chk_req_i | in | logic | Integrity check requests |
| integ_chk_ack_o | out | logic | |
| cnsty_chk_req_i | in | logic | Consistency check requests |
| cnsty_chk_ack_o | out | logic | |
| escalate_en_i | in | lc_tx_t | Escalation input. This moves the FSM into a terminal state and locks down the partition. |
| check_byp_en_i | in | lc_tx_t | Check bypass enable. This bypasses integrity and consistency checks and acknowledges all incoming check requests (only used by life cycle). |
| error_o | out | otp_err_e | Output error state of partition, to be consumed by OTP error/alert logic. Note that most errors are not recoverable and move the partition FSM into a terminal error state. |
| access_i | in | part_access_t | runtime lock from CSRs |
| access_o | out | part_access_t | |
| digest_o | out | [ScrmblBlockWidth-1:0] logic | Buffered 64bit digest output. |
| data_o | out | [Info.size*8-1:0] logic | |
| otp_req_o | out | logic | OTP interface |
| otp_cmd_o | out | cmd_e | |
| otp_size_o | out | [OtpSizeWidth-1:0] logic | |
| otp_wdata_o | out | [OtpIfWidth-1:0] logic | |
| otp_addr_o | out | [OtpAddrWidth-1:0] logic | |
| otp_gnt_i | in | logic | |
| otp_rvalid_i | in | logic | |
| otp_rdata_i | in | [ScrmblBlockWidth-1:0] logic | |
| otp_err_i | in | err_e | |
| scrmbl_mtx_req_o | out | logic | Scrambling mutex request |
| scrmbl_mtx_gnt_i | in | logic | |
| scrmbl_cmd_o | out | otp_scrmbl_cmd_e | Scrambling datapath interface |
| scrmbl_mode_o | out | digest_mode_e | |
| scrmbl_sel_o | out | [ConstSelWidth-1:0] logic | |
| scrmbl_data_o | out | [ScrmblBlockWidth-1:0] logic | |
| scrmbl_valid_o | out | logic | |
| scrmbl_ready_i | in | logic | |
| scrmbl_valid_i | in | logic | |
| scrmbl_data_i | in | [ScrmblBlockWidth-1:0] logic |
This design unit is implemented in otp_ctrl_part_unbuf.sv
This file depends on: prim_flop.sv, uvm_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, otp_ctrl_reg_pkg.sv, prim_otp_pkg.sv, prim_util_pkg.sv, prim_buf.sv, lc_ctrl_pkg.sv, otp_ctrl_ecc_reg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Info | part_info_t | part_info_t'(0) | Partition information. |
| PartEnd | [OtpByteAddrWidth:0] logic | (OtpByteAddrWidth+1)'(Info.offset) + (OtpByteAddrWidth+1)'(Info.size) | |
| DigestOffset | int | (Info.offset + (Info.size - (ScrmblBlockWidth/8))) | |
| StateWidth | int | 10 | Encoding generated with ./sparse-fsm-encode.py -d 5 -m 7 -n 10 -s 4247417884 Hamming distance histogram: 0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (52.38%) 6: |||||||||||||| (38.10%) 7: | (4.76%) 8: | (4.76%) 9: -- 10: -- Minimum Hamming distance: 5 Maximum Hamming distance: 8 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| init_req_i | in | logic | Pulse to start partition initialisation (required once per power cycle). |
| init_done_o | out | logic | |
| escalate_en_i | in | lc_tx_t | Escalation input. This moves the FSM into a terminal state and locks down the partition. |
| error_o | out | otp_err_e | Output error state of partition, to be consumed by OTP error/alert logic. Note that most errors are not recoverable and move the partition FSM into a terminal error state. |
| access_i | in | part_access_t | runtime lock from CSRs |
| access_o | out | part_access_t | |
| digest_o | out | [ScrmblBlockWidth-1:0] logic | Buffered 64bit digest output. |
| tlul_req_i | in | logic | Interface to TL-UL adapter |
| tlul_gnt_o | out | logic | |
| tlul_addr_i | in | [SwWindowAddrWidth-1:0] logic | |
| tlul_rerror_o | out | [1:0] logic | |
| tlul_rvalid_o | out | logic | |
| tlul_rdata_o | out | [31:0] logic | |
| otp_req_o | out | logic | OTP interface |
| otp_cmd_o | out | cmd_e | |
| otp_size_o | out | [OtpSizeWidth-1:0] logic | |
| otp_wdata_o | out | [OtpIfWidth-1:0] logic | |
| otp_addr_o | out | [OtpAddrWidth-1:0] logic | |
| otp_gnt_i | in | logic | |
| otp_rvalid_i | in | logic | |
| otp_rdata_i | in | [ScrmblBlockWidth-1:0] logic | |
| otp_err_i | in | err_e |
This design unit is implemented in otp_ctrl_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, otp_ctrl_reg_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 14 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| tl_win_o | out | tl_h2d_t [2] | Output port for window |
| tl_win_i | in | tl_d2h_t [2] | |
| reg2hw | out | otp_ctrl_reg2hw_t | Write |
| hw2reg | in | otp_ctrl_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Create Socket_1n
Fotp_operation_done: 0:0
Fotp_error: 1:1
Fotp_operation_done: 0:0
Fotp_error: 1:1
Fotp_operation_done: 0:0
Fotp_error: 1:1
Ffatal_macro_error: 0:0
Ffatal_check_error: 1:1
Fcreator_sw_cfg_error: 0:0
Fowner_sw_cfg_error: 1:1
Fhw_cfg_error: 2:2
Fsecret0_error: 3:3
Fsecret1_error: 4:4
Fsecret2_error: 5:5
Flife_cycle_error: 6:6
Fdai_error: 7:7
Flci_error: 8:8
Ftimeout_error: 9:9
Flfsr_fsm_error: 10:10
Fscrambling_fsm_error: 11:11
Fkey_deriv_fsm_error: 12:12
Fdai_idle: 13:13
Fcheck_pending: 14:14
Ferr_code_0: 2:0
Ferr_code_1: 5:3
Ferr_code_2: 8:6
Ferr_code_3: 11:9
Ferr_code_4: 14:12
Ferr_code_5: 17:15
Ferr_code_6: 20:18
Ferr_code_7: 23:21
Ferr_code_8: 26:24
Frd: 0:0
Fwr: 1:1
Fdigest: 2:2
Fintegrity: 0:0
Fconsistency: 1:1
This design unit is implemented in otp_ctrl_scrmbl.sv
This file depends on: prim_flop.sv, prim_present.sv, uvm_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, prim_util_pkg.sv, prim_cipher_pkg.sv, lc_ctrl_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| StateWidth | int | 9 | Encoding generated with ./sparse-fsm-encode.py -d 5 -m 5 -n 9 -s 2193087944 Hamming distance histogram: 0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (60.00%) 6: ||||||||||||| (40.00%) 7: -- 8: -- 9: -- Minimum Hamming distance: 5 Maximum Hamming distance: 6 |
| CntWidth | int | $clog2(NumPresentRounds+1) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| cmd_i | in | otp_scrmbl_cmd_e | input data and command |
| mode_i | in | digest_mode_e | |
| sel_i | in | [ConstSelWidth-1:0] logic | |
| data_i | in | [ScrmblBlockWidth-1:0] logic | |
| valid_i | in | logic | |
| ready_o | out | logic | |
| data_o | out | [ScrmblBlockWidth-1:0] logic | output data |
| valid_o | out | logic | |
| escalate_en_i | in | lc_tx_t | escalation input and FSM error indication |
| fsm_err_o | out | logic |
This design unit is implemented in pattgen_core.sv
This file depends on: pattgen_chan.sv, pattgen_ctrl_pkg.sv, prim_intr_hw.sv, pattgen_reg_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| reg2hw | in | pattgen_reg2hw_t | |
| hw2reg | out | pattgen_hw2reg_t | |
| pda0_tx_o | out | logic | |
| pcl0_tx_o | out | logic | |
| pda1_tx_o | out | logic | |
| pcl1_tx_o | out | logic | |
| intr_done_ch0_o | out | logic | |
| intr_done_ch1_o | out | logic |
This design unit is implemented in pattgen_reg_pkg.sv
This design unit is implemented in pattgen_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, pattgen_reg_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 6 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | pattgen_reg2hw_t | Write |
| hw2reg | in | pattgen_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fdone_ch0: 0:0
Fdone_ch1: 1:1
Fdone_ch0: 0:0
Fdone_ch1: 1:1
Fdone_ch0: 0:0
Fdone_ch1: 1:1
Fenable_ch0: 0:0
Fenable_ch1: 1:1
Fpolarity_ch0: 2:2
Fpolarity_ch1: 3:3
Flen_ch0: 5:0
Freps_ch0: 15:6
Flen_ch1: 21:16
Freps_ch1: 31:22
This design unit is implemented in pinmux_reg_top.sv
This file depends on: pinmux_reg_pkg.sv, prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 12 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | pinmux_reg2hw_t | Write |
| hw2reg | in | pinmux_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fen_0: 0:0
Fen_1: 1:1
Fen_2: 2:2
Fen_3: 3:3
Fen_4: 4:4
Fen_5: 5:5
Fen_6: 6:6
Fen_7: 7:7
Fen_8: 8:8
Fen_9: 9:9
Fen_10: 10:10
Fen_11: 11:11
Fen_12: 12:12
Fen_13: 13:13
Fen_14: 14:14
Fen_15: 15:15
Fen_16: 16:16
Fen_17: 17:17
Fen_18: 18:18
Fen_19: 19:19
Fen_20: 20:20
Fen_21: 21:21
Fen_22: 22:22
Fen_23: 23:23
Fen_24: 24:24
Fen_25: 25:25
Fen_26: 26:26
Fen_27: 27:27
Fen_28: 28:28
Fen_29: 29:29
Fen_30: 30:30
Fen_31: 31:31
Fen_32: 0:0
Fen_33: 1:1
Fen_34: 2:2
Fen_35: 3:3
Fen_36: 4:4
Fen_37: 5:5
Fen_38: 6:6
Fen_39: 7:7
Fen_40: 8:8
Fen_41: 9:9
Fen_42: 10:10
Fen_43: 11:11
Fen_0: 0:0
Fen_1: 1:1
Fen_2: 2:2
Fen_3: 3:3
Fen_4: 4:4
Fen_5: 5:5
Fen_6: 6:6
Fen_7: 7:7
Fen_8: 8:8
Fen_9: 9:9
Fen_10: 10:10
Fen_11: 11:11
Fen_12: 12:12
Fen_13: 13:13
Fen_14: 14:14
Fen_15: 15:15
Fen_16: 16:16
Fen_17: 17:17
Fen_18: 18:18
Fen_19: 19:19
Fen_20: 20:20
Fmode_0: 2:0
Ffilter_0: 3:3
Fmiodio_0: 4:4
Fmode_1: 2:0
Ffilter_1: 3:3
Fmiodio_1: 4:4
Fmode_2: 2:0
Ffilter_2: 3:3
Fmiodio_2: 4:4
Fmode_3: 2:0
Ffilter_3: 3:3
Fmiodio_3: 4:4
Fmode_4: 2:0
Ffilter_4: 3:3
Fmiodio_4: 4:4
Fmode_5: 2:0
Ffilter_5: 3:3
Fmiodio_5: 4:4
Fmode_6: 2:0
Ffilter_6: 3:3
Fmiodio_6: 4:4
Fmode_7: 2:0
Ffilter_7: 3:3
Fmiodio_7: 4:4
Fcause_0: 0:0
Fcause_1: 1:1
Fcause_2: 2:2
Fcause_3: 3:3
Fcause_4: 4:4
Fcause_5: 5:5
Fcause_6: 6:6
Fcause_7: 7:7
This design unit is implemented in pinmux_strap_sampling.sv
This file depends on: pinmux_reg_pkg.sv, jtag_pkg.sv, uvm_pkg.sv, prim_lc_sync.sv, pinmux_jtag_buf.sv, pinmux_pkg.sv, lc_ctrl_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| mio_in_i | in | [NMioPads-1:0] logic | MIO inputs. TODO(#5221): need tapped IOs for JTAG mux. |
| strap_en_i | in | logic | Used for TAP qualification |
| lc_dft_en_i | in | lc_tx_t | |
| lc_hw_debug_en_i | in | lc_tx_t | |
| dft_strap_test_o | out | dft_strap_test_req_t | Sampled values for DFT straps |
| lc_jtag_o | out | jtag_req_t | Qualified JTAG signals for TAPs |
| lc_jtag_i | in | jtag_rsp_t | |
| rv_jtag_o | out | jtag_req_t | |
| rv_jtag_i | in | jtag_rsp_t | |
| dft_jtag_o | out | jtag_req_t | |
| dft_jtag_i | in | jtag_rsp_t |
Insert hand instantiated buffers for these signals to prevent further optimization.
This design unit is implemented in pinmux_wkup.sv
This file depends on: pinmux_reg_pkg.sv, prim_flop_2sync.sv, prim_filter.sv, pinmux_pkg.sv, prim_pulse_sync.sv
Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0
| Name | Type | Default Value | Description |
|---|---|---|---|
| Cycles | int | 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clk_aon_i | in | logic | Always on clock / reset |
| rst_aon_ni | in | logic | |
| wkup_en_i | in | logic | These signals get synchronized to the slow AON clock within this module. Note that wkup_en_i is assumed to be level encoded. |
| filter_en_i | in | logic | |
| wkup_mode_i | in | wkup_mode_e | |
| wkup_cnt_th_i | in | [WkupCntWidth-1:0] logic | |
| pin_value_i | in | logic | |
| wkup_cause_valid_i | in | logic | Signals to/from cause register. They are synched to/from the AON clock internally |
| wkup_cause_data_i | in | logic | |
| wkup_cause_data_o | out | logic | |
| aon_wkup_req_o | out | logic | This signal is running on the AON clock and is held high as long as the cause register has not been cleared. |
Run this through a 2 stage synchronizer to prevent metastability.
output to CSR
This design unit is implemented in prim_alert_receiver.sv
This file depends on: prim_diff_decode.sv, uvm_pkg.sv, prim_alert_pkg.sv, prim_buf.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AsyncOn | bit | 1'b0 | enables additional synchronization logic |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| ping_req_i | in | logic | this triggers a ping test. keep asserted until ping_ok_o is asserted. |
| ping_ok_o | out | logic | |
| integ_fail_o | out | logic | asserted if signal integrity issue detected |
| alert_o | out | logic | alert output (pulsed high) if a handshake is initiated on alert_p/n and no ping request is outstanding |
| alert_rx_o | out | alert_rx_t | ping input diff pair and ack diff pair |
| alert_tx_i | in | alert_tx_t | alert output diff pair |
This prevents further tool optimizations of the differential signal.
This design unit is implemented in prim_alert_sender.sv
This file depends on: prim_diff_decode.sv, uvm_pkg.sv, prim_alert_pkg.sv, prim_buf.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AsyncOn | bit | 1'b1 | enables additional synchronization logic |
| IsFatal | bit | 1'b0 | alert sender will latch the incoming alert event permanently and keep on sending alert events until the next reset. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| alert_test_i | in | logic | alert test trigger (this will never be latched, even if IsFatal == 1) |
| alert_req_i | in | logic | native alert from the peripheral |
| alert_ack_o | out | logic | |
| alert_state_o | out | logic | state of the alert latching register |
| alert_rx_i | in | alert_rx_t | ping input diff pair and ack diff pair |
| alert_tx_o | out | alert_tx_t | alert output diff pair |
This prevents further tool optimizations of the differential signal.
This design unit is implemented in prim_arbiter_fixed.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| N | int | 8 | |
| DW | int | 32 | |
| EnDataPort | bit | 1 | Configurations EnDataPort: {0, 1}, if 0, input data will be ignored |
| IdxW | int | $clog2(N) | Derived parameters |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | used for assertions only |
| rst_ni | in | logic | |
| req_i | in | [N-1:0] logic | |
| data_i | in | [DW-1:0] logic [N] | |
| gnt_o | out | [N-1:0] logic | |
| idx_o | out | [IdxW-1:0] logic | |
| valid_o | out | logic | |
| data_o | out | [DW-1:0] logic | |
| ready_i | in | logic |
This design unit is implemented in prim_arbiter_tree.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| N | int | 8 | |
| DW | int | 32 | |
| EnDataPort | bit | 1 | Configurations EnDataPort: {0, 1}, if 0, input data will be ignored |
| EnReqStabA | bit | 1 | Non-functional parameter to switch on the request stability assertion |
| IdxW | int | $clog2(N) | Derived parameters |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | [N-1:0] logic | |
| data_i | in | [DW-1:0] logic [N] | |
| gnt_o | out | [N-1:0] logic | |
| idx_o | out | [IdxW-1:0] logic | |
| valid_o | out | logic | |
| data_o | out | [DW-1:0] logic | |
| ready_i | in | logic |
This design unit is implemented in prim_clock_buf.sv
This file depends on: prim_generic_clock_buf.sv, prim_xilinx_clock_buf.sv, prim_pkg.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| Impl | impl_e | prim_pkg::ImplGeneric |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| clk_o | out | logic |
This design unit is implemented in prim_clock_div.sv
This file depends on: prim_flop.sv, uvm_pkg.sv, prim_clock_mux2.sv, prim_clock_inv.sv, prim_clock_buf.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Divisor | int | 2 | |
| ResetValue | logic | 0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| step_down_req_i | in | logic | step down divisor by 2x |
| step_down_ack_o | out | logic | step down acknowledge |
| test_en_i | in | logic | |
| clk_o | out | logic |
anchor point for constraints
This design unit is implemented in prim_clock_gating.sv
This file depends on: prim_xilinx_clock_gating.sv, prim_pkg.sv, prim_generic_clock_gating.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| NoFpgaGate | bit | 1'b0 | this parameter has no function in generic |
| Impl | impl_e | prim_pkg::ImplGeneric |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| en_i | in | logic | |
| test_en_i | in | logic | |
| clk_o | out | logic |
This design unit is implemented in prim_clock_gating_sync.sv
This file depends on: prim_flop_2sync.sv, prim_clock_gating.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| test_en_i | in | logic | |
| async_en_i | in | logic | |
| en_o | out | logic | |
| clk_o | out | logic |
This design unit is implemented in prim_clock_inv.sv
This file depends on: prim_generic_clock_inv.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| HasScanMode | bit | 1'b1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| scanmode_i | in | logic | |
| clk_no | out | logic | Inverted |
This design unit is implemented in prim_clock_mux2.sv
This file depends on: prim_xilinx_clock_mux2.sv, prim_generic_clock_mux2.sv, prim_pkg.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| NoFpgaBufG | bit | 1'b0 | this parameter serves no function in the generic model |
| Impl | impl_e | prim_pkg::ImplGeneric |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk0_i | in | logic | |
| clk1_i | in | logic | |
| sel_i | in | logic | |
| clk_o | out | logic |
This design unit is implemented in prim_edn_req.sv
This file depends on: prim_sync_reqack_data.sv, prim_alert_pkg.sv, edn_pkg.sv, prim_packer_fifo.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| OutWidth | int | 32 | |
| SyncWidth | int | $bits({edn_i.edn_fips, edn_i.edn_bus}) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Design side |
| rst_ni | in | logic | |
| req_i | in | logic | |
| ack_o | out | logic | |
| data_o | out | [OutWidth-1:0] logic | |
| fips_o | out | logic | |
| clk_edn_i | in | logic | EDN side |
| rst_edn_ni | in | logic | |
| edn_o | out | edn_req_t | |
| edn_i | in | edn_rsp_t |
This design unit is implemented in prim_esc_receiver.sv
This file depends on: prim_diff_decode.sv, uvm_pkg.sv, prim_buf.sv, prim_esc_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| esc_en_o | out | logic | escalation enable |
| esc_rx_o | out | esc_rx_t | escalation / ping response |
| esc_tx_i | in | esc_tx_t | escalation output diff pair |
This prevents further tool optimizations of the differential signal.
This design unit is implemented in prim_esc_sender.sv
This file depends on: prim_diff_decode.sv, uvm_pkg.sv, prim_buf.sv, prim_esc_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| ping_req_i | in | logic | this triggers a ping test. keep asserted until ping_ok_o is pulsed high. |
| ping_ok_o | out | logic | |
| integ_fail_o | out | logic | asserted if signal integrity issue detected |
| esc_req_i | in | logic | escalation request signal |
| esc_rx_i | in | esc_rx_t | escalation / ping response |
| esc_tx_o | out | esc_tx_t | escalation output diff pair |
This prevents further tool optimizations of the differential signal.
This design unit is implemented in prim_fifo_async.sv
This file depends on: prim_flop_2sync.sv, uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 16 | |
| Depth | int | 3 | |
| DepthW | int | $clog2(Depth+1) | derived parameter representing 0..Depth |
| PTRV_W | int | $clog2(Depth) | |
| PTR_WIDTH | int | PTRV_W+1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_wr_i | in | logic | write port |
| rst_wr_ni | in | logic | |
| wvalid_i | in | logic | |
| wready_o | out | logic | |
| wdata_i | in | [Width-1:0] logic | |
| wdepth_o | out | [DepthW-1:0] logic | |
| clk_rd_i | in | logic | read port |
| rst_rd_ni | in | logic | |
| rvalid_o | out | logic | |
| rready_i | in | logic | |
| rdata_o | out | [Width-1:0] logic | |
| rdepth_o | out | [DepthW-1:0] logic |
This design unit is implemented in prim_fifo_sync.sv
This file depends on: uvm_pkg.sv, prim_util_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 16 | |
| Pass | bit | 1'b1 | if == 1 allow requests to pass through empty FIFO |
| Depth | int | 4 | |
| OutputZeroIfEmpty | bit | 1'b1 | if == 1 always output 0 when FIFO is empty |
| DepthW | int | prim_util_pkg::vbits(Depth+1) | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clr_i | in | logic | synchronous clear / flush port |
| wvalid_i | in | logic | write port |
| wready_o | out | logic | |
| wdata_i | in | [Width-1:0] logic | |
| rvalid_o | out | logic | read port |
| rready_i | in | logic | |
| rdata_o | out | [Width-1:0] logic | |
| full_o | out | logic | occupancy |
| depth_o | out | [DepthW-1:0] logic |
This design unit is implemented in prim_filter_ctr.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Cycles | int | 4 | |
| CTR_WIDTH | int | $clog2(Cycles) | |
| CYCLESM1 | [CTR_WIDTH-1:0] logic | (CTR_WIDTH)'(Cycles-1) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| enable_i | in | logic | |
| filter_i | in | logic | |
| filter_o | out | logic |
This design unit is implemented in prim_flash.sv
This file depends on: prim_generic_flash.sv, flash_phy_pkg.sv, tlul_pkg.sv, lc_ctrl_pkg.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumBanks | int | 2 | number of banks |
| InfosPerBank | int | 1 | info pages per bank |
| InfoTypes | int | 1 | different info types |
| InfoTypesWidth | int | 1 | different info types |
| PagesPerBank | int | 256 | data pages per bank |
| WordsPerPage | int | 256 | words per page |
| DataWidth | int | 32 | bits per word |
| MetaDataWidth | int | 12 | metadata such as ECC |
| TestModeWidth | int | 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| flash_req_i | in | [NumBanks-1:0] flash_phy_prim_flash_req_t | |
| flash_rsp_o | out | [NumBanks-1:0] flash_phy_prim_flash_rsp_t | |
| prog_type_avail_o | out | [flash_phy_pkg::ProgTypes-1:0] logic | |
| init_busy_o | out | logic | |
| tck_i | in | logic | |
| tdi_i | in | logic | |
| tms_i | in | logic | |
| tdo_o | out | logic | |
| bist_enable_i | in | lc_tx_t | |
| scanmode_i | in | lc_tx_t | |
| scan_en_i | in | logic | |
| scan_rst_ni | in | logic | |
| flash_power_ready_h_i | in | logic | |
| flash_power_down_h_i | in | logic | |
| flash_test_mode_a_i | in | [TestModeWidth-1:0] logic | |
| flash_test_voltage_h_i | in | logic | |
| flash_err_o | out | logic | |
| flash_alert_po | out | logic | |
| flash_alert_no | out | logic | |
| flash_alert_ack_i | in | logic | |
| flash_alert_trig_i | in | logic | |
| tl_i | in | tl_h2d_t | |
| tl_o | out | tl_d2h_t | |
| devmode_i | in | logic |
This design unit is implemented in prim_flop.sv
This file depends on: prim_generic_flop.sv, prim_xilinx_flop.sv, prim_pkg.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 1 | |
| WidthSubOne | int | Width-1 | |
| ResetValue | [WidthSubOne:0] logic | 0 | |
| Impl | impl_e | prim_pkg::ImplGeneric |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| d_i | in | [Width-1:0] logic | |
| q_o | out | [Width-1:0] logic |
This design unit is implemented in prim_flop_2sync.sv
This file depends on: prim_generic_flop_2sync.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 16 | |
| WidthSubOne | int | Width-1 | temp work around #2679 |
| ResetValue | [WidthSubOne:0] logic | '0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | receive clock |
| rst_ni | in | logic | |
| d_i | in | [Width-1:0] logic | |
| q_o | out | [Width-1:0] logic |
This design unit is implemented in prim_generic_flop_2sync.sv
This file depends on: prim_flop.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 16 | |
| WidthSubOne | int | Width-1 | temp work around #2679 |
| ResetValue | [WidthSubOne:0] logic | '0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | receive clock |
| rst_ni | in | logic | |
| d_i | in | [Width-1:0] logic | |
| q_o | out | [Width-1:0] logic |
This design unit is implemented in prim_generic_pad_wrapper.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Variant | int | 0 | currently ignored |
| AttrDw | int | 10 | |
| WarlOnly | bit | 0 | If set to 1, no pad is instantiated and only warl_o is driven |
| Name | Direction | Type | Description |
|---|---|---|---|
| inout_io | inout | logic | bidirectional pad |
| in_o | out | logic | input data |
| ie_i | in | logic | input enable |
| out_i | in | logic | output data |
| oe_i | in | logic | output enable |
| attr_i | in | [AttrDw-1:0] logic | additional attributes |
| warl_o | out | [AttrDw-1:0] logic |
This design unit is implemented in prim_intr_hw.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 1 | |
| FlopOutput | bit | 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | event |
| rst_ni | in | logic | |
| event_intr_i | in | [Width-1:0] logic | |
| reg2hw_intr_enable_q_i | in | [Width-1:0] logic | register interface |
| reg2hw_intr_test_q_i | in | [Width-1:0] logic | |
| reg2hw_intr_test_qe_i | in | logic | |
| reg2hw_intr_state_q_i | in | [Width-1:0] logic | |
| hw2reg_intr_state_de_o | out | logic | |
| hw2reg_intr_state_d_o | out | [Width-1:0] logic | |
| intr_o | out | [Width-1:0] logic | outgoing interrupt |
This design unit is implemented in prim_lc_sender.sv
This file depends on: prim_generic_flop.sv, lc_ctrl_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| lc_en_i | in | lc_tx_t | |
| lc_en_o | out | lc_tx_t |
This design unit is implemented in prim_lc_sync.sv
This file depends on: prim_flop_2sync.sv, uvm_pkg.sv, prim_buf.sv, lc_ctrl_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumCopies | int | 1 | Number of separately buffered output signals. The buffer cells have a don't touch constraint on them such that synthesis tools won't collapse all copies into one signal. |
| AsyncOn | bit | 1 | This instantiates the synchronizer flops if set to 1. In special cases where the receiver is in the same clock domain as the sender, this can be set to 0. However, it is recommended to leave this at 1. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| lc_en_i | in | lc_tx_t | |
| lc_en_o | out | [NumCopies-1:0] lc_tx_t |
This design unit is implemented in prim_lfsr.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| LfsrType | unknown | "GAL_XOR" | Lfsr Type, can be FIB_XNOR or GAL_XOR |
| LfsrDw | int | 32 | Lfsr width |
| EntropyDw | int | 8 | Width of the entropy input to be XOR'd into state (lfsr_qEntropyDw-1:0) |
| StateOutDw | int | 8 | Width of output tap (from lfsr_qStateOutDw-1:0) |
| DefaultSeed | [LfsrDw-1:0] logic | LfsrDw'(1) | Lfsr reset state, must be nonzero! |
| CustomCoeffs | [LfsrDw-1:0] logic | '0 | Custom polynomial coeffs |
| StatePermEn | bit | 1'b0 | If StatePermEn is set to 1, the custom permutation specified via StatePerm is applied to the state output, in order to break linear shifting patterns of the LFSR. |
| StatePerm | [$clog2(LfsrDw)-1:0] [LfsrDw-1:0] logic | '0 | |
| MaxLenSVA | bit | 1'b1 | Enable this for DV, disable this for long LFSRs in FPV |
| LockupSVA | bit | 1'b1 | Can be disabled in cases where seed and entropy inputs are unused in order to not distort coverage (the SVA will be unreachable in such cases) |
| ExtSeedSVA | bit | 1'b1 | |
| GAL_XOR_LUT_OFF | int | 4 | automatically generated with util/design/get-lfsr-coeffs.py script |
| GAL_XOR_COEFFS | [63:0] logic [61] | '{ 64'h9, 64'h12, 64'h21, 64'h41, 64'h8E, 64'h108, 64'h204, 64'h402, 64'h829, 64'h100D, 64'h2015, 64'h4001, 64'h8016, 64'h10004, 64'h20013, 64'h40013, 64'h80004, 64'h100002, 64'h200001, 64'h400010, 64'h80000D, 64'h1000004, 64'h2000023, 64'h4000013, 64'h8000004, 64'h10000002, 64'h20000029, 64'h40000004, 64'h80000057, 64'h100000029, 64'h200000073, 64'h400000002, 64'h80000003B, 64'h100000001F, 64'h2000000031, 64'h4000000008, 64'h800000001C, 64'h10000000004, 64'h2000000001F, 64'h4000000002C, 64'h80000000032, 64'h10000000000D, 64'h200000000097, 64'h400000000010, 64'h80000000005B, 64'h1000000000038, 64'h200000000000E, 64'h4000000000025, 64'h8000000000004, 64'h10000000000023, 64'h2000000000003E, 64'h40000000000023, 64'h8000000000004A, 64'h100000000000016, 64'h200000000000031, 64'h40000000000003D, 64'h800000000000001, 64'h1000000000000013, 64'h2000000000000034, 64'h4000000000000001, 64'h800000000000000D } | |
| FIB_XNOR_LUT_OFF | int | 3 | automatically generated with get-lfsr-coeffs.py script |
| FIB_XNOR_COEFFS | [167:0] logic [166] | '{ 168'h6, 168'hC, 168'h14, 168'h30, 168'h60, 168'hB8, 168'h110, 168'h240, 168'h500, 168'h829, 168'h100D, 168'h2015, 168'h6000, 168'hD008, 168'h12000, 168'h20400, 168'h40023, 168'h90000, 168'h140000, 168'h300000, 168'h420000, 168'hE10000, 168'h1200000, 168'h2000023, 168'h4000013, 168'h9000000, 168'h14000000, 168'h20000029, 168'h48000000, 168'h80200003, 168'h100080000, 168'h204000003, 168'h500000000, 168'h801000000, 168'h100000001F, 168'h2000000031, 168'h4400000000, 168'hA000140000, 168'h12000000000, 168'h300000C0000, 168'h63000000000, 168'hC0000030000, 168'h1B0000000000, 168'h300003000000, 168'h420000000000, 168'hC00000180000, 168'h1008000000000, 168'h3000000C00000, 168'h6000C00000000, 168'h9000000000000, 168'h18003000000000, 168'h30000000030000, 168'h40000040000000, 168'hC0000600000000, 168'h102000000000000, 168'h200004000000000, 168'h600003000000000, 168'hC00000000000000, 168'h1800300000000000, 168'h3000000000000030, 168'h6000000000000000, 168'hD800000000000000, 168'h10000400000000000, 168'h30180000000000000, 168'h60300000000000000, 168'h80400000000000000, 168'h140000028000000000, 168'h300060000000000000, 168'h410000000000000000, 168'h820000000001040000, 168'h1000000800000000000, 168'h3000600000000000000, 168'h6018000000000000000, 168'hC000000018000000000, 168'h18000000600000000000, 168'h30000600000000000000, 168'h40200000000000000000, 168'hC0000000060000000000, 168'h110000000000000000000, 168'h240000000480000000000, 168'h600000000003000000000, 168'h800400000000000000000, 168'h1800000300000000000000, 168'h3003000000000000000000, 168'h4002000000000000000000, 168'hC000000000000000018000, 168'h10000000004000000000000, 168'h30000C00000000000000000, 168'h600000000000000000000C0, 168'hC00C0000000000000000000, 168'h140000000000000000000000, 168'h200001000000000000000000, 168'h400800000000000000000000, 168'hA00000000001400000000000, 168'h1040000000000000000000000, 168'h2004000000000000000000000, 168'h5000000000028000000000000, 168'h8000000004000000000000000, 168'h18600000000000000000000000, 168'h30000000000000000C00000000, 168'h40200000000000000000000000, 168'hC0300000000000000000000000, 168'h100010000000000000000000000, 168'h200040000000000000000000000, 168'h5000000000000000A0000000000, 168'h800000010000000000000000000, 168'h1860000000000000000000000000, 168'h3003000000000000000000000000, 168'h4010000000000000000000000000, 168'hA000000000140000000000000000, 168'h10080000000000000000000000000, 168'h30000000000000000000180000000, 168'h60018000000000000000000000000, 168'hC0000000000000000300000000000, 168'h140005000000000000000000000000, 168'h200000001000000000000000000000, 168'h404000000000000000000000000000, 168'h810000000000000000000000000102, 168'h1000040000000000000000000000000, 168'h3000000000000006000000000000000, 168'h5000000000000000000000000000000, 168'h8000000004000000000000000000000, 168'h18000000000000000000000000030000, 168'h30000000030000000000000000000000, 168'h60000000000000000000000000000000, 168'hA0000014000000000000000000000000, 168'h108000000000000000000000000000000, 168'h240000000000000000000000000000000, 168'h600000000000C00000000000000000000, 168'h800000040000000000000000000000000, 168'h1800000000000300000000000000000000, 168'h2000000000000010000000000000000000, 168'h4008000000000000000000000000000000, 168'hC000000000000000000000000000000600, 168'h10000080000000000000000000000000000, 168'h30600000000000000000000000000000000, 168'h4A400000000000000000000000000000000, 168'h80000004000000000000000000000000000, 168'h180000003000000000000000000000000000, 168'h200001000000000000000000000000000000, 168'h600006000000000000000000000000000000, 168'hC00000000000000006000000000000000000, 168'h1000000000000100000000000000000000000, 168'h3000000000000006000000000000000000000, 168'h6000000003000000000000000000000000000, 168'h8000001000000000000000000000000000000, 168'h1800000000000000000000000000C000000000, 168'h20000000000001000000000000000000000000, 168'h48000000000000000000000000000000000000, 168'hC0000000000000006000000000000000000000, 168'h180000000000000000000000000000000000000, 168'h280000000000000000000000000000005000000, 168'h60000000C000000000000000000000000000000, 168'hC00000000000000000000000000018000000000, 168'h1800000600000000000000000000000000000000, 168'h3000000C00000000000000000000000000000000, 168'h4000000080000000000000000000000000000000, 168'hC000300000000000000000000000000000000000, 168'h10000400000000000000000000000000000000000, 168'h30000000000000000000006000000000000000000, 168'h600000000000000C0000000000000000000000000, 168'hC0060000000000000000000000000000000000000, 168'h180000006000000000000000000000000000000000, 168'h3000000000C0000000000000000000000000000000, 168'h410000000000000000000000000000000000000000, 168'hA00140000000000000000000000000000000000000 } |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| seed_en_i | in | logic | load external seed into the state (takes precedence) |
| seed_i | in | [LfsrDw-1:0] logic | external seed input |
| lfsr_en_i | in | logic | enables the LFSR |
| entropy_i | in | [EntropyDw-1:0] logic | additional entropy to be XOR'ed into the state |
| state_o | out | [StateOutDw-1:0] logic | (partial) LFSR state output |
This design unit is implemented in prim_otp.sv
This file depends on: prim_generic_otp.sv, prim_util_pkg.sv, prim_otp_pkg.sv, tlul_pkg.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 16 | Native OTP word size. This determines the size_i granule. |
| Depth | int | 1024 | |
| SizeWidth | int | 2 | This determines the maximum number of native words that can be transferred accross the interface in one cycle. |
| PwrSeqWidth | int | 2 | Width of the power sequencing signal. |
| TlDepth | int | 16 | Number of Test TL-UL words |
| AddrWidth | int | prim_util_pkg::vbits(Depth) | Derived parameters |
| IfWidth | int | 2**SizeWidth*Width | |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| pwr_seq_o | out | [PwrSeqWidth-1:0] logic | Macro-specific power sequencing signals to/from AST |
| pwr_seq_h_i | in | [PwrSeqWidth-1:0] logic | |
| test_tl_i | in | tl_h2d_t | Test interface |
| test_tl_o | out | tl_d2h_t | |
| ready_o | out | logic | Ready valid handshake for read/write command |
| valid_i | in | logic | |
| size_i | in | [SizeWidth-1:0] logic | #(Native words)-1, e.g. size == 0 for 1 native word. |
| cmd_i | in | cmd_e | 00: read command, 01: write command, 11: init command |
| addr_i | in | [AddrWidth-1:0] logic | |
| wdata_i | in | [IfWidth-1:0] logic | |
| valid_o | out | logic | Response channel |
| rdata_o | out | [IfWidth-1:0] logic | |
| err_o | out | err_e |
This design unit is implemented in prim_otp_pkg.sv
This design unit is implemented in prim_packer.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| InW | int | 32 | |
| OutW | int | 32 | |
| HintByteData | int | 0 | If 1, The input/output are byte granularity |
| Width | int | InW + OutW | storage width |
| ConcatW | int | Width + InW | Input concatenated width |
| PtrW | int | $clog2(ConcatW+1) | |
| IdxW | int | $clog2(InW) + ~|$clog2(InW) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| valid_i | in | logic | |
| data_i | in | [InW-1:0] logic | |
| mask_i | in | [InW-1:0] logic | |
| ready_o | out | logic | |
| valid_o | out | logic | |
| data_o | out | [OutW-1:0] logic | |
| mask_o | out | [OutW-1:0] logic | |
| ready_i | in | logic | |
| flush_i | in | logic | If 1, send out remnant and clear state |
| flush_done_o | out | logic |
This design unit is implemented in prim_packer_fifo.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| InW | int | 32 | |
| OutW | int | 8 | |
| MaxW | int | (InW > OutW) ? InW : OutW | derived parameters |
| MinW | int | (InW < OutW) ? InW : OutW | |
| DepthW | int | $clog2(MaxW/MinW) | |
| WidthRatio | int | MaxW / MinW | |
| FullDepth | [DepthW:0] bit | WidthRatio[DepthW:0] |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clr_i | in | logic | |
| wvalid_i | in | logic | |
| wdata_i | in | [InW-1:0] logic | |
| wready_o | out | logic | |
| rvalid_o | out | logic | |
| rdata_o | out | [OutW-1:0] logic | |
| rready_i | in | logic | |
| depth_o | out | [DepthW:0] logic |
This design unit is implemented in prim_pkg.sv
This design unit is implemented in prim_prince.sv
This file depends on: uvm_pkg.sv, prim_cipher_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| DataWidth | int | 64 | |
| KeyWidth | int | 128 | |
| NumRoundsHalf | int | 5 | The construction is reflective. Total number of rounds is 2*NumRoundsHalf + 2 |
| UseOldKeySched | bit | 1'b0 | This primitive uses the new key schedule proposed in https://eprint.iacr.org/2014/656.pdf Setting this parameter to 1 falls back to the original key schedule. |
| HalfwayDataReg | bit | 1'b0 | This instantiates a data register halfway in the primitive. |
| HalfwayKeyReg | bit | 1'b0 | This instantiates a key register halfway in the primitive. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| valid_i | in | logic | |
| data_i | in | [DataWidth-1:0] logic | |
| key_i | in | [KeyWidth-1:0] logic | |
| dec_i | in | logic | set to 1 for decryption |
| valid_o | out | logic | |
| data_o | out | [DataWidth-1:0] logic |
This design unit is implemented in prim_pulse_sync.sv
This file depends on: prim_flop_2sync.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_src_i | in | logic | source clock domain |
| rst_src_ni | in | logic | |
| src_pulse_i | in | logic | |
| clk_dst_i | in | logic | destination clock domain |
| rst_dst_ni | in | logic | |
| dst_pulse_o | out | logic |
This design unit is implemented in prim_ram_1p_adv.sv
This file depends on: prim_secded_hamming_39_32_dec.sv, prim_secded_22_16_enc.sv, uvm_pkg.sv, prim_secded_hamming_39_32_enc.sv, prim_secded_hamming_22_16_enc.sv, prim_secded_39_32_enc.sv, prim_util_pkg.sv, prim_secded_hamming_22_16_dec.sv, prim_secded_22_16_dec.sv, prim_secded_39_32_dec.sv, prim_ram_1p.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Depth | int | 512 | |
| Width | int | 32 | |
| DataBitsPerMask | int | 1 | Number of data bits per bit of write mask |
| CfgW | int | 8 | WTC, RTC, etc |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| EnableECC | bit | 0 | Enables per-word ECC |
| EnableParity | bit | 0 | Enables per-Byte Parity |
| EnableInputPipeline | bit | 0 | Adds an input register (read latency +1) |
| EnableOutputPipeline | bit | 0 | Adds an output register (read latency +1) |
| HammingECC | bit | 0 | This switch allows to switch to standard Hamming ECC instead of the HSIAO ECC. It is recommended to leave this parameter at its default setting (HSIAO), since this results in a more compact and faster implementation. |
| Aw | int | prim_util_pkg::vbits(Depth) | |
| ParWidth | int | (EnableParity) ? Width/8 : (!EnableECC) ? 0 : (Width <= 4) ? 4 : (Width <= 11) ? 5 : (Width <= 26) ? 6 : (Width <= 57) ? 7 : (Width <= 120) ? 8 : 8 | Calculate ECC width |
| TotalWidth | int | Width + ParWidth | |
| LocalDataBitsPerMask | int | (EnableParity) ? 9 : (EnableECC) ? TotalWidth : DataBitsPerMask | If byte parity is enabled, the write enable bits are used to write memory colums with 8 + 1 = 9 bit width (data plus corresponding parity bit). If ECC is enabled, the DataBitsPerMask is ignored. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | logic | |
| write_i | in | logic | |
| addr_i | in | [Aw-1:0] logic | |
| wdata_i | in | [Width-1:0] logic | |
| wmask_i | in | [Width-1:0] logic | |
| rdata_o | out | [Width-1:0] logic | |
| rvalid_o | out | logic | read response (rdata_o) is valid |
| rerror_o | out | [1:0] logic | Bit1: Uncorrectable, Bit0: Correctable |
| cfg_i | in | [CfgW-1:0] logic | config |
This design unit is implemented in prim_ram_2p_adv.sv
This file depends on: prim_util_pkg.sv, prim_ram_2p_async_adv.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Depth | int | 512 | |
| Width | int | 32 | |
| DataBitsPerMask | int | 1 | Number of data bits per bit of write mask |
| CfgW | int | 8 | WTC, RTC, etc |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| EnableECC | bit | 0 | Enables per-word ECC |
| EnableParity | bit | 0 | Enables per-Byte Parity |
| EnableInputPipeline | bit | 0 | Adds an input register (read latency +1) |
| EnableOutputPipeline | bit | 0 | Adds an output register (read latency +1) |
| HammingECC | bit | 0 | This switch allows to switch to standard Hamming ECC instead of the HSIAO ECC. It is recommended to leave this parameter at its default setting (HSIAO), since this results in a more compact and faster implementation. |
| Aw | int | prim_util_pkg::vbits(Depth) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| a_req_i | in | logic | |
| a_write_i | in | logic | |
| a_addr_i | in | [Aw-1:0] logic | |
| a_wdata_i | in | [Width-1:0] logic | |
| a_wmask_i | in | [Width-1:0] logic | cannot be used with ECC, tie to 1 in that case |
| a_rdata_o | out | [Width-1:0] logic | |
| a_rvalid_o | out | logic | read response (a_rdata_o) is valid |
| a_rerror_o | out | [1:0] logic | Bit1: Uncorrectable, Bit0: Correctable |
| b_req_i | in | logic | |
| b_write_i | in | logic | |
| b_addr_i | in | [Aw-1:0] logic | |
| b_wdata_i | in | [Width-1:0] logic | |
| b_wmask_i | in | [Width-1:0] logic | cannot be used with ECC, tie to 1 in that case |
| b_rdata_o | out | [Width-1:0] logic | |
| b_rvalid_o | out | logic | read response (b_rdata_o) is valid |
| b_rerror_o | out | [1:0] logic | Bit1: Uncorrectable, Bit0: Correctable |
| cfg_i | in | [CfgW-1:0] logic |
This design unit is implemented in prim_ram_2p_async_adv.sv
This file depends on: prim_secded_hamming_39_32_dec.sv, uvm_pkg.sv, prim_secded_hamming_39_32_enc.sv, prim_secded_39_32_enc.sv, prim_util_pkg.sv, prim_ram_2p.sv, prim_secded_39_32_dec.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Depth | int | 512 | |
| Width | int | 32 | |
| DataBitsPerMask | int | 1 | Number of data bits per bit of write mask |
| CfgW | int | 8 | WTC, RTC, etc |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| EnableECC | bit | 0 | Enables per-word ECC |
| EnableParity | bit | 0 | Enables per-Byte Parity |
| EnableInputPipeline | bit | 0 | Adds an input register (read latency +1) |
| EnableOutputPipeline | bit | 0 | Adds an output register (read latency +1) |
| HammingECC | bit | 0 | This switch allows to switch to standard Hamming ECC instead of the HSIAO ECC. It is recommended to leave this parameter at its default setting (HSIAO), since this results in a more compact and faster implementation. |
| Aw | int | prim_util_pkg::vbits(Depth) | |
| ParWidth | int | (EnableParity) ? Width/8 : (!EnableECC) ? 0 : (Width <= 4) ? 4 : (Width <= 11) ? 5 : (Width <= 26) ? 6 : (Width <= 57) ? 7 : (Width <= 120) ? 8 : 8 | Calculate ECC width |
| TotalWidth | int | Width + ParWidth | |
| LocalDataBitsPerMask | int | (EnableParity) ? 9 : (EnableECC) ? TotalWidth : DataBitsPerMask | If byte parity is enabled, the write enable bits are used to write memory colums with 8 + 1 = 9 bit width (data plus corresponding parity bit). If ECC is enabled, the DataBitsPerMask is ignored. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_a_i | in | logic | |
| clk_b_i | in | logic | |
| rst_a_ni | in | logic | |
| rst_b_ni | in | logic | |
| a_req_i | in | logic | |
| a_write_i | in | logic | |
| a_addr_i | in | [Aw-1:0] logic | |
| a_wdata_i | in | [Width-1:0] logic | |
| a_wmask_i | in | [Width-1:0] logic | cannot be used with ECC, tie to 1 in that case |
| a_rdata_o | out | [Width-1:0] logic | |
| a_rvalid_o | out | logic | read response (a_rdata_o) is valid |
| a_rerror_o | out | [1:0] logic | Bit1: Uncorrectable, Bit0: Correctable |
| b_req_i | in | logic | |
| b_write_i | in | logic | |
| b_addr_i | in | [Aw-1:0] logic | |
| b_wdata_i | in | [Width-1:0] logic | |
| b_wmask_i | in | [Width-1:0] logic | cannot be used with ECC, tie to 1 in that case |
| b_rdata_o | out | [Width-1:0] logic | |
| b_rvalid_o | out | logic | read response (b_rdata_o) is valid |
| b_rerror_o | out | [1:0] logic | Bit1: Uncorrectable, Bit0: Correctable |
| cfg_i | in | [CfgW-1:0] logic | config |
This design unit is implemented in prim_rom.sv
This file depends on: prim_generic_rom.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 32 | |
| Depth | int | 2048 | 8kB default |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| Aw | int | $clog2(Depth) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| req_i | in | logic | |
| addr_i | in | [Aw-1:0] logic | |
| rdata_o | out | [Width-1:0] logic |
This design unit is implemented in prim_sram_arbiter.sv
This file depends on: prim_arbiter_ppc.sv, uvm_pkg.sv, prim_fifo_sync.sv, prim_arbiter_tree.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| N | int | 4 | |
| SramDw | int | 32 | |
| SramAw | int | 12 | |
| ArbiterImpl | unknown | "PPC" | |
| ARB_DW | int | $bits(req_t) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | [N-1:0] logic | |
| req_addr_i | in | [SramAw-1:0] logic [N] | |
| req_write_i | in | logic [N] | |
| req_wdata_i | in | [SramDw-1:0] logic [N] | |
| gnt_o | out | [N-1:0] logic | |
| rsp_rvalid_o | out | [N-1:0] logic | Pulse |
| rsp_rdata_o | out | [SramDw-1:0] logic [N] | |
| rsp_error_o | out | [1:0] logic [N] | |
| sram_req_o | out | logic | SRAM Interface |
| sram_addr_o | out | [SramAw-1:0] logic | |
| sram_write_o | out | logic | |
| sram_wdata_o | out | [SramDw-1:0] logic | |
| sram_rvalid_i | in | logic | |
| sram_rdata_i | in | [SramDw-1:0] logic | |
| sram_rerror_i | in | [1:0] logic |
Request FIFO
This design unit is implemented in prim_subreg.sv
This file depends on: prim_subreg_arb.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| DW | int | 32 | |
| SWACCESS | unknown | "RW" | {RW, RO, WO, W1C, W1S, W0C, RC} |
| RESVAL | [DW-1:0] logic | '0 | Reset value |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| we | in | logic | From SW: valid for RW, WO, W1C, W1S, W0C, RC In case of RC, Top connects Read Pulse to we |
| wd | in | [DW-1:0] logic | |
| de | in | logic | From HW: valid for HRW, HWO |
| d | in | [DW-1:0] logic | |
| qe | out | logic | output to HW and Reg Read |
| q | out | [DW-1:0] logic | |
| qs | out | [DW-1:0] logic |
This design unit is implemented in prim_subst_perm.sv
This file depends on: prim_cipher_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| DataWidth | int | 64 | |
| NumRounds | int | 31 | |
| Decrypt | bit | 0 | 0: encrypt, 1: decrypt |
| Name | Direction | Type | Description |
|---|---|---|---|
| data_i | in | [DataWidth-1:0] logic | |
| key_i | in | [DataWidth-1:0] logic | |
| data_o | out | [DataWidth-1:0] logic |
This design unit is implemented in prim_sync_reqack_data.sv
This file depends on: uvm_pkg.sv, prim_sync_reqack.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 1 | |
| DataSrc2Dst | bit | 1'b1 | Direction of data flow: 1'b1 = SRC to DST, 1'b0 = DST to SRC |
| DataReg | bit | 1'b0 | Enable optional register stage for data, only usable with DataSrc2Dst == 1'b0. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_src_i | in | logic | REQ side, SRC domain |
| rst_src_ni | in | logic | REQ side, SRC domain |
| clk_dst_i | in | logic | ACK side, DST domain |
| rst_dst_ni | in | logic | ACK side, DST domain |
| src_req_i | in | logic | REQ side, SRC domain |
| src_ack_o | out | logic | REQ side, SRC domain |
| dst_req_o | out | logic | ACK side, DST domain |
| dst_ack_i | in | logic | ACK side, DST domain |
| data_i | in | [Width-1:0] logic | |
| data_o | out | [Width-1:0] logic |
REQ/ACK synchronizer primitive //
This design unit is implemented in prim_sync_slow_fast.sv
This file depends on: prim_flop_2sync.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 32 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_slow_i | in | logic | |
| clk_fast_i | in | logic | |
| rst_fast_ni | in | logic | |
| wdata_i | in | [Width-1:0] logic | Slow domain |
| rdata_o | out | [Width-1:0] logic | Fast domain |
Synchronize the slow clock to the fast domain
This design unit is implemented in prim_xilinx_pad_wrapper.sv
This file depends on: IOBUF.v
| Name | Type | Default Value | Description |
|---|---|---|---|
| Variant | int | 0 | currently ignored |
| AttrDw | int | 10 | |
| WarlOnly | bit | 0 | If set to 1, no pad is instantiated and only warl_o is driven |
| Name | Direction | Type | Description |
|---|---|---|---|
| inout_io | inout | logic | bidirectional pad |
| in_o | out | logic | input data |
| ie_i | in | logic | input enable |
| out_i | in | logic | output data |
| oe_i | in | logic | output enable |
| attr_i | in | [AttrDw-1:0] logic | additional attributes |
| warl_o | out | [AttrDw-1:0] logic |
This design unit is implemented in pwrmgr_cdc.sv
This file depends on: prim_flop_2sync.sv, prim_pulse_sync.sv, pwrmgr_reg_pkg.sv, pwrmgr_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_slow_i | in | logic | Clocks and resets |
| clk_i | in | logic | |
| rst_slow_ni | in | logic | |
| rst_ni | in | logic | |
| slow_req_pwrup_i | in | logic | slow domain signals, |
| slow_ack_pwrdn_i | in | logic | |
| slow_pwrup_cause_toggle_i | in | logic | |
| slow_pwrup_cause_i | in | pwrup_cause_e | |
| slow_wakeup_en_o | out | [NumWkups-1:0] logic | |
| slow_reset_en_o | out | [NumRstReqs-1:0] logic | |
| slow_main_pd_no | out | logic | |
| slow_io_clk_en_o | out | logic | |
| slow_core_clk_en_o | out | logic | |
| slow_usb_clk_en_lp_o | out | logic | |
| slow_usb_clk_en_active_o | out | logic | |
| slow_req_pwrdn_o | out | logic | |
| slow_ack_pwrup_o | out | logic | |
| slow_ast_o | out | pwr_ast_rsp_t | |
| slow_peri_reqs_o | out | pwr_peri_t | |
| slow_peri_reqs_masked_i | in | pwr_peri_t | |
| req_pwrdn_i | in | logic | fast domain signals |
| ack_pwrup_i | in | logic | |
| cfg_cdc_sync_i | in | logic | |
| wakeup_en_i | in | [NumWkups-1:0] logic | |
| reset_en_i | in | [NumRstReqs-1:0] logic | |
| main_pd_ni | in | logic | |
| io_clk_en_i | in | logic | |
| core_clk_en_i | in | logic | |
| usb_clk_en_lp_i | in | logic | |
| usb_clk_en_active_i | in | logic | |
| ack_pwrdn_o | out | logic | |
| req_pwrup_o | out | logic | |
| pwrup_cause_o | out | pwrup_cause_e | |
| peri_reqs_o | out | pwr_peri_t | |
| cdc_sync_done_o | out | logic | |
| peri_i | in | pwr_peri_t | peripheral inputs, mixed domains |
| flash_i | in | pwr_flash_rsp_t | |
| flash_o | out | pwr_flash_rsp_t | |
| otp_i | in | pwr_otp_rsp_t | otp interface |
| otp_o | out | pwr_otp_rsp_t | |
| ast_i | in | pwr_ast_rsp_t | AST inputs, unknown domain |
Even though this is multi-bit, the bits are individual request lines. So there is no general concern about recombining as there is no intent to use them in a related manner.
Some of the AST signals are multi-bits themselves (such as clk_val) thus they need to be delayed one more stage to check for stability
synchronize inputs from flash
This design unit is implemented in pwrmgr_fsm.sv
This file depends on: prim_flop.sv, uvm_pkg.sv, pwrmgr_reg_pkg.sv, pwrmgr_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| OffDomainSelStart | int | ALWAYS_ON_DOMAIN + 1 | when there are multiple on domains, the latter 1 should become another parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_pwrup_i | in | logic | interface with slow_fsm |
| pwrup_cause_i | in | pwrup_cause_e | |
| ack_pwrup_o | out | logic | |
| req_pwrdn_o | out | logic | |
| ack_pwrdn_i | in | logic | |
| low_power_entry_i | in | logic | |
| main_pd_ni | in | logic | |
| reset_reqs_i | in | [NumRstReqs:0] logic | |
| wkup_o | out | logic | generate wake interrupt |
| wkup_record_o | out | logic | enable wakeup recording |
| fall_through_o | out | logic | |
| abort_o | out | logic | |
| clr_hint_o | out | logic | |
| clr_cfg_lock_o | out | logic | |
| pwr_rst_o | out | pwr_rst_req_t | rstmgr |
| pwr_rst_i | in | pwr_rst_rsp_t | |
| ips_clk_en_o | out | logic | clkmgr |
| clk_en_status_i | in | logic | |
| otp_init_o | out | logic | otp |
| otp_done_i | in | logic | |
| otp_idle_i | in | logic | |
| lc_init_o | out | logic | lc |
| lc_done_i | in | logic | |
| lc_idle_i | in | logic | |
| flash_init_o | out | logic | flash |
| flash_done_i | in | logic | |
| flash_idle_i | in | logic |
This design unit is implemented in pwrmgr_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, pwrmgr_reg_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 6 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | pwrmgr_reg2hw_t | Write |
| hw2reg | in | pwrmgr_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Flow_power_hint: 0:0
Fcore_clk_en: 4:4
Fio_clk_en: 5:5
Fusb_clk_en_lp: 6:6
Fusb_clk_en_active: 7:7
Fmain_pd_n: 8:8
Fen_0: 0:0
Fen_1: 1:1
Fen_2: 2:2
Fval_0: 0:0
Fval_1: 1:1
Fval_2: 2:2
Freasons: 2:0
Ffall_through: 3:3
Fabort: 4:4
This design unit is implemented in pwrmgr_slow_fsm.sv
This file depends on: pwrmgr_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wakeup_i | in | logic | sync'ed requests from peripherals |
| reset_req_i | in | logic | |
| req_pwrup_o | out | logic | interface with fast fsm |
| pwrup_cause_toggle_o | out | logic | |
| pwrup_cause_o | out | pwrup_cause_e | |
| ack_pwrup_i | in | logic | |
| req_pwrdn_i | in | logic | |
| ack_pwrdn_o | out | logic | |
| main_pd_ni | in | logic | low power entry configuration |
| io_clk_en_i | in | logic | |
| core_clk_en_i | in | logic | |
| usb_clk_en_lp_i | in | logic | |
| usb_clk_en_active_i | in | logic | |
| ast_i | in | pwr_ast_rsp_t | AST interface |
| ast_o | out | pwr_ast_req_t |
This design unit is implemented in pwrmgr_wake_info.sv
This file depends on: pwrmgr_reg_pkg.sv, pwrmgr_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wr_i | in | logic | |
| data_i | in | [TotalWakeWidth-1:0] logic | |
| start_capture_i | in | logic | |
| record_dis_i | in | logic | |
| wakeups_i | in | [NumWkups-1:0] logic | |
| fall_through_i | in | logic | |
| abort_i | in | logic | |
| info_o | out | [TotalWakeWidth-1:0] logic |
This design unit is implemented in rng_osc.sv
of rng_osc
| Name | Type | Default Value | Description |
|---|---|---|---|
| RNG_EN_RDLY | time | 5us |
| Name | Direction | Type | Description |
|---|---|---|---|
| vcaon_pok_i | in | logic | VCAON POK @1.1V |
| rng_en_i | in | logic | RNG Source Clock Enable |
| rng_clk_o | out | logic | RNG Clock Output |
This design unit is implemented in rstmgr_crash_info.sv
This file depends on: uvm_pkg.sv, rstmgr_pkg.sv, rstmgr_reg_pkg.sv
rstmgr_crash_info
| Name | Type | Default Value | Description |
|---|---|---|---|
| CrashDumpWidth | int | 32 | |
| CrashRemainder | int | CrashDumpWidth % RdWidth > 0 ? 1 : 0 | |
| CrashStoreSlot | int | CrashDumpWidth / RdWidth + CrashRemainder | |
| SlotCntWidth | int | $clog2(CrashStoreSlot) | |
| TotalWidth | int | CrashStoreSlot * RdWidth |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| dump_i | in | [CrashDumpWidth-1:0] logic | |
| dump_capture_i | in | logic | |
| slot_sel_i | in | [IdxWidth-1:0] logic | |
| slots_cnt_o | out | [IdxWidth-1:0] logic | |
| slot_o | out | [RdWidth-1:0] logic |
This design unit is implemented in rstmgr_ctrl.sv
This file depends on: prim_flop.sv, prim_flop_2sync.sv, rstmgr_pkg.sv
rstmgr_ctrl
| Name | Type | Default Value | Description |
|---|---|---|---|
| PowerDomains | int | 2 | |
| OffDomains | int | PowerDomains - 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| rst_req_i | in | [PowerDomains-1:0] logic | |
| rst_parent_ni | in | [PowerDomains-1:0] logic | parent reset |
| rst_no | out | [PowerDomains-1:0] logic |
always on handling
This design unit is implemented in rstmgr_por.sv
This file depends on: prim_flop.sv, prim_flop_2sync.sv, prim_clock_mux2.sv
rstmgr_por
| Name | Type | Default Value | Description |
|---|---|---|---|
| FilterStages | int | 3 | |
| StretchCount | int | 32 | |
| CtrWidth | int | $clog2(StretchCount+1) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| scan_rst_ni | in | logic | |
| scanmode_i | in | logic | |
| rst_no | out | logic |
sync the POR
This design unit is implemented in rstmgr_reg_pkg.sv
This design unit is implemented in rstmgr_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, rstmgr_reg_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 6 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | rstmgr_reg2hw_t | Write |
| hw2reg | in | rstmgr_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fpor: 0:0
Flow_power_exit: 1:1
Fndm_reset: 2:2
Fhw_req: 4:3
Fen: 0:0
Findex: 7:4
Fen: 0:0
Findex: 7:4
Fen_0: 0:0
Fen_1: 1:1
Fen_2: 2:2
Fen_3: 3:3
Fen_4: 4:4
Fen_5: 5:5
Fen_6: 6:6
Fval_0: 0:0
Fval_1: 1:1
Fval_2: 2:2
Fval_3: 3:3
Fval_4: 4:4
Fval_5: 5:5
Fval_6: 6:6
This design unit is implemented in rv_plic_gateway.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| N_SOURCE | int | 32 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| src_i | in | [N_SOURCE-1:0] logic | |
| le_i | in | [N_SOURCE-1:0] logic | Level0 Edge1 |
| claim_i | in | [N_SOURCE-1:0] logic | $onehot0(claim_i) |
| complete_i | in | [N_SOURCE-1:0] logic | $onehot0(complete_i) |
| ip_o | out | [N_SOURCE-1:0] logic |
This design unit is implemented in rv_plic_reg_pkg.sv
This design unit is implemented in rv_plic_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, rv_plic_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 10 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | rv_plic_reg2hw_t | Write |
| hw2reg | in | rv_plic_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fp_0: 0:0
Fp_1: 1:1
Fp_2: 2:2
Fp_3: 3:3
Fp_4: 4:4
Fp_5: 5:5
Fp_6: 6:6
Fp_7: 7:7
Fp_8: 8:8
Fp_9: 9:9
Fp_10: 10:10
Fp_11: 11:11
Fp_12: 12:12
Fp_13: 13:13
Fp_14: 14:14
Fp_15: 15:15
Fp_16: 16:16
Fp_17: 17:17
Fp_18: 18:18
Fp_19: 19:19
Fp_20: 20:20
Fp_21: 21:21
Fp_22: 22:22
Fp_23: 23:23
Fp_24: 24:24
Fp_25: 25:25
Fp_26: 26:26
Fp_27: 27:27
Fp_28: 28:28
Fp_29: 29:29
Fp_30: 30:30
Fp_31: 31:31
Fp_32: 0:0
Fp_33: 1:1
Fp_34: 2:2
Fp_35: 3:3
Fp_36: 4:4
Fp_37: 5:5
Fp_38: 6:6
Fp_39: 7:7
Fp_40: 8:8
Fp_41: 9:9
Fp_42: 10:10
Fp_43: 11:11
Fp_44: 12:12
Fp_45: 13:13
Fp_46: 14:14
Fp_47: 15:15
Fp_48: 16:16
Fp_49: 17:17
Fp_50: 18:18
Fp_51: 19:19
Fp_52: 20:20
Fp_53: 21:21
Fp_54: 22:22
Fp_55: 23:23
Fp_56: 24:24
Fp_57: 25:25
Fp_58: 26:26
Fp_59: 27:27
Fp_60: 28:28
Fp_61: 29:29
Fp_62: 30:30
Fp_63: 31:31
Fp_64: 0:0
Fp_65: 1:1
Fp_66: 2:2
Fp_67: 3:3
Fp_68: 4:4
Fp_69: 5:5
Fp_70: 6:6
Fp_71: 7:7
Fp_72: 8:8
Fp_73: 9:9
Fp_74: 10:10
Fp_75: 11:11
Fp_76: 12:12
Fp_77: 13:13
Fp_78: 14:14
Fp_79: 15:15
Fp_80: 16:16
Fp_81: 17:17
Fp_82: 18:18
Fp_83: 19:19
Fp_84: 20:20
Fp_85: 21:21
Fp_86: 22:22
Fp_87: 23:23
Fp_88: 24:24
Fp_89: 25:25
Fp_90: 26:26
Fp_91: 27:27
Fp_92: 28:28
Fp_93: 29:29
Fp_94: 30:30
Fp_95: 31:31
Fp_96: 0:0
Fp_97: 1:1
Fp_98: 2:2
Fp_99: 3:3
Fp_100: 4:4
Fp_101: 5:5
Fp_102: 6:6
Fp_103: 7:7
Fp_104: 8:8
Fp_105: 9:9
Fp_106: 10:10
Fp_107: 11:11
Fp_108: 12:12
Fp_109: 13:13
Fp_110: 14:14
Fp_111: 15:15
Fp_112: 16:16
Fp_113: 17:17
Fp_114: 18:18
Fp_115: 19:19
Fp_116: 20:20
Fp_117: 21:21
Fp_118: 22:22
Fp_119: 23:23
Fp_120: 24:24
Fp_121: 25:25
Fp_122: 26:26
Fp_123: 27:27
Fp_124: 28:28
Fp_125: 29:29
Fp_126: 30:30
Fp_127: 31:31
Fp_128: 0:0
Fp_129: 1:1
Fp_130: 2:2
Fp_131: 3:3
Fp_132: 4:4
Fp_133: 5:5
Fp_134: 6:6
Fp_135: 7:7
Fp_136: 8:8
Fp_137: 9:9
Fp_138: 10:10
Fp_139: 11:11
Fp_140: 12:12
Fp_141: 13:13
Fp_142: 14:14
Fp_143: 15:15
Fp_144: 16:16
Fp_145: 17:17
Fp_146: 18:18
Fp_147: 19:19
Fp_148: 20:20
Fp_149: 21:21
Fp_150: 22:22
Fp_151: 23:23
Fp_152: 24:24
Fp_153: 25:25
Fp_154: 26:26
Fp_155: 27:27
Fp_156: 28:28
Fp_157: 29:29
Fp_158: 30:30
Fp_159: 31:31
Fp_160: 0:0
Fp_161: 1:1
Fp_162: 2:2
Fp_163: 3:3
Fp_164: 4:4
Fp_165: 5:5
Fp_166: 6:6
Fp_167: 7:7
Fp_168: 8:8
Fp_169: 9:9
Fp_170: 10:10
Fle_0: 0:0
Fle_1: 1:1
Fle_2: 2:2
Fle_3: 3:3
Fle_4: 4:4
Fle_5: 5:5
Fle_6: 6:6
Fle_7: 7:7
Fle_8: 8:8
Fle_9: 9:9
Fle_10: 10:10
Fle_11: 11:11
Fle_12: 12:12
Fle_13: 13:13
Fle_14: 14:14
Fle_15: 15:15
Fle_16: 16:16
Fle_17: 17:17
Fle_18: 18:18
Fle_19: 19:19
Fle_20: 20:20
Fle_21: 21:21
Fle_22: 22:22
Fle_23: 23:23
Fle_24: 24:24
Fle_25: 25:25
Fle_26: 26:26
Fle_27: 27:27
Fle_28: 28:28
Fle_29: 29:29
Fle_30: 30:30
Fle_31: 31:31
Fle_32: 0:0
Fle_33: 1:1
Fle_34: 2:2
Fle_35: 3:3
Fle_36: 4:4
Fle_37: 5:5
Fle_38: 6:6
Fle_39: 7:7
Fle_40: 8:8
Fle_41: 9:9
Fle_42: 10:10
Fle_43: 11:11
Fle_44: 12:12
Fle_45: 13:13
Fle_46: 14:14
Fle_47: 15:15
Fle_48: 16:16
Fle_49: 17:17
Fle_50: 18:18
Fle_51: 19:19
Fle_52: 20:20
Fle_53: 21:21
Fle_54: 22:22
Fle_55: 23:23
Fle_56: 24:24
Fle_57: 25:25
Fle_58: 26:26
Fle_59: 27:27
Fle_60: 28:28
Fle_61: 29:29
Fle_62: 30:30
Fle_63: 31:31
Fle_64: 0:0
Fle_65: 1:1
Fle_66: 2:2
Fle_67: 3:3
Fle_68: 4:4
Fle_69: 5:5
Fle_70: 6:6
Fle_71: 7:7
Fle_72: 8:8
Fle_73: 9:9
Fle_74: 10:10
Fle_75: 11:11
Fle_76: 12:12
Fle_77: 13:13
Fle_78: 14:14
Fle_79: 15:15
Fle_80: 16:16
Fle_81: 17:17
Fle_82: 18:18
Fle_83: 19:19
Fle_84: 20:20
Fle_85: 21:21
Fle_86: 22:22
Fle_87: 23:23
Fle_88: 24:24
Fle_89: 25:25
Fle_90: 26:26
Fle_91: 27:27
Fle_92: 28:28
Fle_93: 29:29
Fle_94: 30:30
Fle_95: 31:31
Fle_96: 0:0
Fle_97: 1:1
Fle_98: 2:2
Fle_99: 3:3
Fle_100: 4:4
Fle_101: 5:5
Fle_102: 6:6
Fle_103: 7:7
Fle_104: 8:8
Fle_105: 9:9
Fle_106: 10:10
Fle_107: 11:11
Fle_108: 12:12
Fle_109: 13:13
Fle_110: 14:14
Fle_111: 15:15
Fle_112: 16:16
Fle_113: 17:17
Fle_114: 18:18
Fle_115: 19:19
Fle_116: 20:20
Fle_117: 21:21
Fle_118: 22:22
Fle_119: 23:23
Fle_120: 24:24
Fle_121: 25:25
Fle_122: 26:26
Fle_123: 27:27
Fle_124: 28:28
Fle_125: 29:29
Fle_126: 30:30
Fle_127: 31:31
Fle_128: 0:0
Fle_129: 1:1
Fle_130: 2:2
Fle_131: 3:3
Fle_132: 4:4
Fle_133: 5:5
Fle_134: 6:6
Fle_135: 7:7
Fle_136: 8:8
Fle_137: 9:9
Fle_138: 10:10
Fle_139: 11:11
Fle_140: 12:12
Fle_141: 13:13
Fle_142: 14:14
Fle_143: 15:15
Fle_144: 16:16
Fle_145: 17:17
Fle_146: 18:18
Fle_147: 19:19
Fle_148: 20:20
Fle_149: 21:21
Fle_150: 22:22
Fle_151: 23:23
Fle_152: 24:24
Fle_153: 25:25
Fle_154: 26:26
Fle_155: 27:27
Fle_156: 28:28
Fle_157: 29:29
Fle_158: 30:30
Fle_159: 31:31
Fle_160: 0:0
Fle_161: 1:1
Fle_162: 2:2
Fle_163: 3:3
Fle_164: 4:4
Fle_165: 5:5
Fle_166: 6:6
Fle_167: 7:7
Fle_168: 8:8
Fle_169: 9:9
Fle_170: 10:10
Fe_0: 0:0
Fe_1: 1:1
Fe_2: 2:2
Fe_3: 3:3
Fe_4: 4:4
Fe_5: 5:5
Fe_6: 6:6
Fe_7: 7:7
Fe_8: 8:8
Fe_9: 9:9
Fe_10: 10:10
Fe_11: 11:11
Fe_12: 12:12
Fe_13: 13:13
Fe_14: 14:14
Fe_15: 15:15
Fe_16: 16:16
Fe_17: 17:17
Fe_18: 18:18
Fe_19: 19:19
Fe_20: 20:20
Fe_21: 21:21
Fe_22: 22:22
Fe_23: 23:23
Fe_24: 24:24
Fe_25: 25:25
Fe_26: 26:26
Fe_27: 27:27
Fe_28: 28:28
Fe_29: 29:29
Fe_30: 30:30
Fe_31: 31:31
Fe_32: 0:0
Fe_33: 1:1
Fe_34: 2:2
Fe_35: 3:3
Fe_36: 4:4
Fe_37: 5:5
Fe_38: 6:6
Fe_39: 7:7
Fe_40: 8:8
Fe_41: 9:9
Fe_42: 10:10
Fe_43: 11:11
Fe_44: 12:12
Fe_45: 13:13
Fe_46: 14:14
Fe_47: 15:15
Fe_48: 16:16
Fe_49: 17:17
Fe_50: 18:18
Fe_51: 19:19
Fe_52: 20:20
Fe_53: 21:21
Fe_54: 22:22
Fe_55: 23:23
Fe_56: 24:24
Fe_57: 25:25
Fe_58: 26:26
Fe_59: 27:27
Fe_60: 28:28
Fe_61: 29:29
Fe_62: 30:30
Fe_63: 31:31
Fe_64: 0:0
Fe_65: 1:1
Fe_66: 2:2
Fe_67: 3:3
Fe_68: 4:4
Fe_69: 5:5
Fe_70: 6:6
Fe_71: 7:7
Fe_72: 8:8
Fe_73: 9:9
Fe_74: 10:10
Fe_75: 11:11
Fe_76: 12:12
Fe_77: 13:13
Fe_78: 14:14
Fe_79: 15:15
Fe_80: 16:16
Fe_81: 17:17
Fe_82: 18:18
Fe_83: 19:19
Fe_84: 20:20
Fe_85: 21:21
Fe_86: 22:22
Fe_87: 23:23
Fe_88: 24:24
Fe_89: 25:25
Fe_90: 26:26
Fe_91: 27:27
Fe_92: 28:28
Fe_93: 29:29
Fe_94: 30:30
Fe_95: 31:31
Fe_96: 0:0
Fe_97: 1:1
Fe_98: 2:2
Fe_99: 3:3
Fe_100: 4:4
Fe_101: 5:5
Fe_102: 6:6
Fe_103: 7:7
Fe_104: 8:8
Fe_105: 9:9
Fe_106: 10:10
Fe_107: 11:11
Fe_108: 12:12
Fe_109: 13:13
Fe_110: 14:14
Fe_111: 15:15
Fe_112: 16:16
Fe_113: 17:17
Fe_114: 18:18
Fe_115: 19:19
Fe_116: 20:20
Fe_117: 21:21
Fe_118: 22:22
Fe_119: 23:23
Fe_120: 24:24
Fe_121: 25:25
Fe_122: 26:26
Fe_123: 27:27
Fe_124: 28:28
Fe_125: 29:29
Fe_126: 30:30
Fe_127: 31:31
Fe_128: 0:0
Fe_129: 1:1
Fe_130: 2:2
Fe_131: 3:3
Fe_132: 4:4
Fe_133: 5:5
Fe_134: 6:6
Fe_135: 7:7
Fe_136: 8:8
Fe_137: 9:9
Fe_138: 10:10
Fe_139: 11:11
Fe_140: 12:12
Fe_141: 13:13
Fe_142: 14:14
Fe_143: 15:15
Fe_144: 16:16
Fe_145: 17:17
Fe_146: 18:18
Fe_147: 19:19
Fe_148: 20:20
Fe_149: 21:21
Fe_150: 22:22
Fe_151: 23:23
Fe_152: 24:24
Fe_153: 25:25
Fe_154: 26:26
Fe_155: 27:27
Fe_156: 28:28
Fe_157: 29:29
Fe_158: 30:30
Fe_159: 31:31
Fe_160: 0:0
Fe_161: 1:1
Fe_162: 2:2
Fe_163: 3:3
Fe_164: 4:4
Fe_165: 5:5
Fe_166: 6:6
Fe_167: 7:7
Fe_168: 8:8
Fe_169: 9:9
Fe_170: 10:10
This design unit is implemented in rv_plic_target.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| N_SOURCE | int | 32 | |
| MAX_PRIO | int | 7 | |
| SrcWidth | int | $clog2(N_SOURCE+1) | derived parameter |
| PrioWidth | int | $clog2(MAX_PRIO+1) | derived parameter |
| NumLevels | int | $clog2(N_SOURCE) | align to powers of 2 for simplicity a full binary tree with N levels has 2N + 2N-1 nodes |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| ip_i | in | [N_SOURCE-1:0] logic | |
| ie_i | in | [N_SOURCE-1:0] logic | |
| prio_i | in | [PrioWidth-1:0] logic [N_SOURCE] | |
| threshold_i | in | [PrioWidth-1:0] logic | |
| irq_o | out | logic | |
| irq_id_o | out | [SrcWidth-1:0] logic |
This design unit is implemented in rv_timer_reg_pkg.sv
This design unit is implemented in rv_timer_reg_top.sv
This file depends on: rv_timer_reg_pkg.sv, prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 9 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | rv_timer_reg2hw_t | Write |
| hw2reg | in | rv_timer_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fprescale: 11:0
Fstep: 23:16
This design unit is implemented in sensor_ctrl_pkg.sv
This file depends on: sensor_ctrl_reg_pkg.sv
sensor_ctrl_pkg
This design unit is implemented in sensor_ctrl_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, sensor_ctrl_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 5 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | sensor_ctrl_reg2hw_t | Write |
| hw2reg | in | sensor_ctrl_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Frecov_as: 0:0
Frecov_cg: 1:1
Frecov_gd: 2:2
Frecov_ts_hi: 3:3
Frecov_ts_lo: 4:4
Frecov_ls: 5:5
Frecov_ot: 6:6
Fval_0: 1:0
Fval_1: 3:2
Fval_2: 5:4
Fval_3: 7:6
Fval_4: 9:8
Fval_5: 11:10
Fval_6: 13:12
Fval_0: 0:0
Fval_1: 1:1
Fval_2: 2:2
Fval_3: 3:3
Fval_4: 4:4
Fval_5: 5:5
Fval_6: 6:6
Fval_0: 0:0
Fval_1: 1:1
Fval_2: 2:2
Fval_3: 3:3
Fval_4: 4:4
Fval_5: 5:5
Fval_6: 6:6
This design unit is implemented in sha2.sv
This file depends on: hmac_pkg.sv, sha2_pad.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wipe_secret | in | logic | |
| wipe_v | in | sha_word_t | |
| fifo_rvalid | in | logic | FIFO read signal |
| fifo_rdata | in | sha_fifo_t | |
| fifo_rready | out | logic | |
| sha_en | in | logic | If disabled, it clears internal content. |
| hash_start | in | logic | |
| hash_process | in | logic | |
| hash_done | out | logic | |
| message_length | in | [63:0] logic | bits but byte based |
| digest | out | [7:0] sha_word_t |
This design unit is implemented in sha3.sv
This file depends on: uvm_pkg.sv, sha3_pkg.sv, sha3pad.sv, keccak_round.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| EnMasking | bit | 0 | Enable Masked Keccak if 1 |
| Share | int | (EnMasking) ? 2 : 1 | derived parameter |
| ReuseShare | bit | 0 | Configurations Decide if implements Re-use the adjacent shares as entropy in DOM AND logic |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| msg_valid_i | in | logic | MSG interface |
| msg_data_i | in | [MsgWidth-1:0] logic [Share] | |
| msg_strb_i | in | [MsgStrbW-1:0] logic | one strobe for shares |
| msg_ready_o | out | logic | |
| rand_valid_i | in | logic | Entropy interface |
| rand_data_i | in | [StateW-1:0] logic | |
| rand_consumed_o | out | logic | |
| ns_data_i | in | [NSRegisterSize*8-1:0] logic | See sha3_pkg for details |
| mode_i | in | sha3_mode_e | see sha3pad for details |
| strength_i | in | keccak_strength_e | see sha3pad for details |
| start_i | in | logic | see sha3pad for details |
| process_i | in | logic | see sha3pad for details |
| run_i | in | logic | run_i is a pulse signal to trigger the keccak_round manually by SW.
It is used to run additional keccak_f after sponge absorbing is completed.
See |
| done_i | in | logic | see sha3pad for details |
| absorbed_o | out | logic | |
| squeezing_o | out | logic | |
| block_processed_o | out | logic | Indicate of one block processed. KMAC main state tracks the progression based on this signal. |
| sha3_fsm_o | out | sha3_st_e | |
| state_valid_o | out | logic | digest output
This value is valid only after all absorbing process is completed.
In invalid state, the output |
| state_o | out | [StateW-1:0] logic [Share] | |
| error_o | out | err_t | error_o value is pushed to Error FIFO at KMAC/SHA3 top and reported to SW |
SHA3 pad logic
Keccak round logic
This design unit is implemented in sha3_pkg.sv
This design unit is implemented in spi_device_pkg.sv
This file depends on: spi_device_reg_pkg.sv
This design unit is implemented in spi_device_reg_pkg.sv
This design unit is implemented in spi_device_reg_top.sv
This file depends on: prim_subreg_ext.sv, spi_device_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 13 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| tl_win_o | out | tl_h2d_t [1] | Output port for window |
| tl_win_i | in | tl_d2h_t [1] | |
| reg2hw | out | spi_device_reg2hw_t | Write |
| hw2reg | in | spi_device_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Create Socket_1n
Frxf: 0:0
Frxlvl: 1:1
Ftxlvl: 2:2
Frxerr: 3:3
Frxoverflow: 4:4
Ftxunderflow: 5:5
Frxf: 0:0
Frxlvl: 1:1
Ftxlvl: 2:2
Frxerr: 3:3
Frxoverflow: 4:4
Ftxunderflow: 5:5
Frxf: 0:0
Frxlvl: 1:1
Ftxlvl: 2:2
Frxerr: 3:3
Frxoverflow: 4:4
Ftxunderflow: 5:5
Fabort: 0:0
Fmode: 5:4
Frst_txfifo: 16:16
Frst_rxfifo: 17:17
Fcpol: 0:0
Fcpha: 1:1
Ftx_order: 2:2
Frx_order: 3:3
Ftimer_v: 15:8
Frxlvl: 15:0
Ftxlvl: 31:16
Frxlvl: 7:0
Ftxlvl: 23:16
Frxf_full: 0:0
Frxf_empty: 1:1
Ftxf_full: 2:2
Ftxf_empty: 3:3
Fabort_done: 4:4
Fcsb: 5:5
Frptr: 15:0
Fwptr: 31:16
Frptr: 15:0
Fwptr: 31:16
Fbase: 15:0
Flimit: 31:16
Fbase: 15:0
Flimit: 31:16
This design unit is implemented in spi_fwm_rxf_ctrl.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| FifoDw | int | 8 | |
| SramAw | int | 11 | |
| SramDw | int | 32 | |
| NumBytes | int | SramDw/FifoDw | derived parameter |
| SDW | int | $clog2(NumBytes) | derived parameter |
| PtrW | int | SramAw + SDW + 1 | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| base_index_i | in | [SramAw-1:0] logic | Configuration |
| limit_index_i | in | [SramAw-1:0] logic | |
| timer_v | in | [7:0] logic | |
| rptr | in | [PtrW-1:0] logic | |
| wptr | out | [PtrW-1:0] logic | |
| depth | out | [PtrW-1:0] logic | |
| full | out | logic | |
| fifo_valid | in | logic | |
| fifo_ready | out | logic | |
| fifo_rdata | in | [FifoDw-1:0] logic | |
| sram_req | out | logic | |
| sram_write | out | logic | |
| sram_addr | out | [SramAw-1:0] logic | |
| sram_wdata | out | [SramDw-1:0] logic | |
| sram_gnt | in | logic | |
| sram_rvalid | in | logic | |
| sram_rdata | in | [SramDw-1:0] logic | |
| sram_error | in | [1:0] logic |
This design unit is implemented in spi_fwm_txf_ctrl.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| FifoDw | int | 8 | |
| SramAw | int | 11 | |
| SramDw | int | 32 | |
| NumBytes | int | SramDw/FifoDw | derived parameter |
| SDW | int | $clog2(NumBytes) | derived parameter |
| PtrW | int | SramAw + SDW + 1 | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| base_index_i | in | [SramAw-1:0] logic | Configuration |
| limit_index_i | in | [SramAw-1:0] logic | |
| abort | in | logic | Abort State Machine if TX Async at stuck |
| wptr | in | [PtrW-1:0] logic | |
| rptr | out | [PtrW-1:0] logic | |
| depth | out | [PtrW-1:0] logic | |
| fifo_valid | out | logic | |
| fifo_ready | in | logic | |
| fifo_wdata | out | [FifoDw-1:0] logic | |
| sram_req | out | logic | |
| sram_write | out | logic | |
| sram_addr | out | [SramAw-1:0] logic | |
| sram_wdata | out | [SramDw-1:0] logic | |
| sram_gnt | in | logic | |
| sram_rvalid | in | logic | |
| sram_rdata | in | [SramDw-1:0] logic | |
| sram_error | in | [1:0] logic |
This design unit is implemented in spi_fwmode.sv
This file depends on: spi_device_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| mode_i | in | spi_mode_e | Only works at mode_i == FwMode |
| rx_wvalid_o | out | logic | RX, TX FIFO interface |
| rx_wready_i | in | logic | |
| rx_data_o | out | spi_byte_t | |
| tx_rvalid_i | in | logic | |
| tx_rready_o | out | logic | |
| tx_data_i | in | spi_byte_t | |
| rx_overflow_o | out | logic | |
| tx_underflow_o | out | logic | |
| rx_data_valid_i | in | logic | Serial to Parallel |
| rx_data_i | in | spi_byte_t | |
| io_mode_o | out | io_mode_e | |
| tx_wvalid_o | out | logic | Parallel to SPI |
| tx_data_o | out | spi_byte_t | |
| tx_wready_i | in | logic |
This design unit is implemented in spi_host_reg_pkg.sv
This design unit is implemented in spi_host_reg_top.sv
This file depends on: prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, spi_host_reg_pkg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 2 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | spi_host_reg2hw_t | Write |
| hw2reg | in | spi_host_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fdata: 3:0
Fsck: 4:4
Fcsb: 5:5
Fdir: 6:6
This design unit is implemented in spi_p2s.sv
This file depends on: uvm_pkg.sv, spi_device_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Bits | int | $bits(spi_byte_t) | |
| BitWidth | int | $clog2(Bits) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| data_valid_i | in | logic | Input byte interface |
| data_i | in | spi_byte_t | |
| data_sent_o | out | logic | |
| csb_i | in | logic | for line floating |
| s_en_o | out | [3:0] logic | |
| s_o | out | [3:0] logic | |
| cpha_i | in | logic | Configuration If CPHA=1, then the first byte should be delayed. But this does not matter in SPI Flash. Only applicable to Generic mode |
| order_i | in | logic | Control txorder: controls which bit goes out first. |
| io_mode_i | in | io_mode_e | IO mode |
This design unit is implemented in spi_s2p.sv
This file depends on: uvm_pkg.sv, spi_device_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Length | int | 8 + 32 + 8 + 2048 | Definitions // Maximum Length of a transaction is: 8 bit opcode + 24 or 32 bit address + max 8 bit dummy cycle + 256B payload |
| BitCntW | int | $clog2(Length+1) | |
| Bits | int | $bits(spi_byte_t) | |
| BitWidth | int | $clog2(Bits) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | inverted CSb input |
| s_i | in | [3:0] logic | SPI data |
| data_valid_o | out | logic | to following logic |
| data_o | out | spi_byte_t | |
| bitcnt_o | out | [11:0] logic | up to 256B payload |
| order_i | in | logic | Configuration |
| io_mode_i | in | io_mode_e |
This design unit is implemented in sram_ctrl_reg_pkg.sv
This design unit is implemented in sram_ctrl_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, sram_ctrl_reg_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 5 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | sram_ctrl_reg2hw_t | Write |
| hw2reg | in | sram_ctrl_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Ferror: 0:0
Fescalated: 1:1
Fscr_key_valid: 2:2
Fscr_key_seed_valid: 3:3
This design unit is implemented in sys_osc.sv
of sys_osc
| Name | Type | Default Value | Description |
|---|---|---|---|
| SYS_EN_RDLY | time | 5us | |
| SysClkPeriod | real | 10000 | 10000ps (100Mhz) |
| Name | Direction | Type | Description |
|---|---|---|---|
| vcore_pok_h_i | in | logic | VCORE POK @3.3V |
| sys_en_i | in | logic | System Source Clock Enable |
| sys_jen_i | in | logic | System Source Clock Jitter Enable |
| sys_clk_o | out | logic | System Clock Output |
This design unit is implemented in timer_core.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| N | int | 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| active | in | logic | |
| prescaler | in | [11:0] logic | |
| step | in | [7:0] logic | |
| tick | out | logic | |
| mtime_d | out | [63:0] logic | |
| mtime | in | [63:0] logic | |
| mtimecmp | in | [63:0] logic [N] | |
| intr | out | [N-1:0] logic |
This design unit is implemented in tl_peri_pkg.sv
This design unit is implemented in tlul_adapter_host.sv
This file depends on: prim_secded_64_57_enc.sv, uvm_pkg.sv, top_pkg.sv, tlul_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| MAX_REQS | int | 2 | |
| WordSize | int | $clog2(top_pkg::TL_DBW) | |
| OutstandingReqCntW | int | (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | logic | |
| gnt_o | out | logic | |
| addr_i | in | [top_pkg::TL_AW-1:0] logic | |
| we_i | in | logic | |
| wdata_i | in | [top_pkg::TL_DW-1:0] logic | |
| be_i | in | [top_pkg::TL_DBW-1:0] logic | |
| type_i | in | tl_type_e | |
| valid_o | out | logic | |
| rdata_o | out | [top_pkg::TL_DW-1:0] logic | |
| err_o | out | logic | |
| tl_o | out | tl_h2d_t | |
| tl_i | in | tl_d2h_t |
This design unit is implemented in tlul_adapter_reg.sv
This file depends on: tlul_err.sv, uvm_pkg.sv, top_pkg.sv, tlul_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RegAw | int | 8 | |
| RegDw | int | 32 | Shall be matched with TL_DW |
| RegBw | int | RegDw/8 | |
| IW | int | $bits(tl_i.a_source) | |
| SZW | int | $bits(tl_i.a_size) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | TL-UL interface |
| tl_o | out | tl_d2h_t | |
| re_o | out | logic | Register interface |
| we_o | out | logic | |
| addr_o | out | [RegAw-1:0] logic | |
| wdata_o | out | [RegDw-1:0] logic | |
| be_o | out | [RegBw-1:0] logic | |
| rdata_i | in | [RegDw-1:0] logic | |
| error_i | in | logic |
tl_err : separate checker
This design unit is implemented in tlul_err.sv
This file depends on: uvm_pkg.sv, tlul_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| IW | int | $bits(tl_i.a_source) | |
| SZW | int | $bits(tl_i.a_size) | |
| DW | int | $bits(tl_i.a_data) | |
| MW | int | $bits(tl_i.a_mask) | |
| SubAW | int | $clog2(DW/8) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | |
| err_o | out | logic |
This design unit is implemented in tlul_fifo_async.sv
This file depends on: uvm_pkg.sv, tlul_pkg.sv, prim_fifo_async.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| ReqDepth | int | 3 | |
| RspDepth | int | 3 | |
| REQFIFO_WIDTH | int | $bits(tlul_pkg::tl_h2d_t)-2 | Put everything on the request side into one FIFO |
| RSPFIFO_WIDTH | int | $bits(tlul_pkg::tl_d2h_t) -2 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_h_i | in | logic | |
| rst_h_ni | in | logic | |
| clk_d_i | in | logic | |
| rst_d_ni | in | logic | |
| tl_h_i | in | tl_h2d_t | |
| tl_h_o | out | tl_d2h_t | |
| tl_d_o | out | tl_h2d_t | |
| tl_d_i | in | tl_d2h_t |
This design unit is implemented in tlul_fifo_sync.sv
This file depends on: top_pkg.sv, prim_fifo_sync.sv, tlul_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| ReqPass | bit | 1'b1 | |
| RspPass | bit | 1'b1 | |
| ReqDepth | int | 2 | |
| RspDepth | int | 2 | |
| SpareReqW | int | 1 | |
| SpareRspW | int | 1 | |
| REQFIFO_WIDTH | int | $bits(tlul_pkg::tl_h2d_t) -2 + SpareReqW | Put everything on the request side into one FIFO |
| RSPFIFO_WIDTH | int | $bits(tlul_pkg::tl_d2h_t) -2 + SpareRspW |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_h_i | in | tl_h2d_t | |
| tl_h_o | out | tl_d2h_t | |
| tl_d_o | out | tl_h2d_t | |
| tl_d_i | in | tl_d2h_t | |
| spare_req_i | in | [SpareReqW-1:0] logic | |
| spare_req_o | out | [SpareReqW-1:0] logic | |
| spare_rsp_i | in | [SpareRspW-1:0] logic | |
| spare_rsp_o | out | [SpareRspW-1:0] logic |
This design unit is implemented in tlul_socket_1n.sv
This file depends on: tlul_err_resp.sv, uvm_pkg.sv, top_pkg.sv, tlul_pkg.sv, tlul_fifo_sync.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| N | int | 4 | |
| HReqPass | bit | 1'b1 | |
| HRspPass | bit | 1'b1 | |
| DReqPass | [N-1:0] bit | {N{1'b1}} | |
| DRspPass | [N-1:0] bit | {N{1'b1}} | |
| HReqDepth | [3:0] bit | 4'h2 | |
| HRspDepth | [3:0] bit | 4'h2 | |
| DReqDepth | [N*4-1:0] bit | {N{4'h2}} | |
| DRspDepth | [N*4-1:0] bit | {N{4'h2}} | |
| NWD | int | $clog2(N+1) | derived parameter |
| MaxOutstanding | int | 2**top_pkg::TL_AIW | Up to 256 ounstanding |
| OutstandingW | int | $clog2(MaxOutstanding+1) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_h_i | in | tl_h2d_t | |
| tl_h_o | out | tl_d2h_t | |
| tl_d_o | out | tl_h2d_t [N] | |
| tl_d_i | in | tl_d2h_t [N] | |
| dev_select_i | in | [NWD-1:0] logic |
This design unit is implemented in tlul_socket_m1.sv
This file depends on: uvm_pkg.sv, prim_arbiter_ppc.sv, top_pkg.sv, tlul_pkg.sv, tlul_fifo_sync.sv, prim_arbiter_tree.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| M | int | 4 | |
| HReqPass | [M-1:0] bit | {M{1'b1}} | |
| HRspPass | [M-1:0] bit | {M{1'b1}} | |
| HReqDepth | [M*4-1:0] bit | {M{4'h2}} | |
| HRspDepth | [M*4-1:0] bit | {M{4'h2}} | |
| DReqPass | bit | 1'b1 | |
| DRspPass | bit | 1'b1 | |
| DReqDepth | [3:0] bit | 4'h2 | |
| DRspDepth | [3:0] bit | 4'h2 | |
| IDW | int | top_pkg::TL_AIW | Signals tl_h_i/o0 | tl_h_i/o1 | ... | tl_h_i/oM-1 | | | u_hostfifo0 u_hostfifo1 u_hostfifoM-1 | | | hreq_fifo_o(i) / hrsp_fifo_i(i) Required ID width to distinguish between host ports Used in response steering |
| STIDW | int | $clog2(M) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_h_i | in | tl_h2d_t [M] | |
| tl_h_o | out | tl_d2h_t [M] | |
| tl_d_o | out | tl_h2d_t | |
| tl_d_i | in | tl_d2h_t |
Device Req/Rsp FIFO
This design unit is implemented in uart_core.sv
This file depends on: prim_flop_2sync.sv, uart_tx.sv, uart_reg_pkg.sv, prim_fifo_sync.sv, uart_rx.sv, prim_intr_hw.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NcoWidth | int | $bits(reg2hw.ctrl.nco.q) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| reg2hw | in | uart_reg2hw_t | |
| hw2reg | out | uart_hw2reg_t | |
| rx | in | logic | |
| tx | out | logic | |
| intr_tx_watermark_o | out | logic | |
| intr_rx_watermark_o | out | logic | |
| intr_tx_empty_o | out | logic | |
| intr_rx_overflow_o | out | logic | |
| intr_rx_frame_err_o | out | logic | |
| intr_rx_break_err_o | out | logic | |
| intr_rx_timeout_o | out | logic | |
| intr_rx_parity_err_o | out | logic |
This design unit is implemented in uart_reg_pkg.sv
This design unit is implemented in uart_reg_top.sv
This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, uart_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 6 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | uart_reg2hw_t | Write |
| hw2reg | in | uart_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Ftx_watermark: 0:0
Frx_watermark: 1:1
Ftx_empty: 2:2
Frx_overflow: 3:3
Frx_frame_err: 4:4
Frx_break_err: 5:5
Frx_timeout: 6:6
Frx_parity_err: 7:7
Ftx_watermark: 0:0
Frx_watermark: 1:1
Ftx_empty: 2:2
Frx_overflow: 3:3
Frx_frame_err: 4:4
Frx_break_err: 5:5
Frx_timeout: 6:6
Frx_parity_err: 7:7
Ftx_watermark: 0:0
Frx_watermark: 1:1
Ftx_empty: 2:2
Frx_overflow: 3:3
Frx_frame_err: 4:4
Frx_break_err: 5:5
Frx_timeout: 6:6
Frx_parity_err: 7:7
Ftx: 0:0
Frx: 1:1
Fnf: 2:2
Fslpbk: 4:4
Fllpbk: 5:5
Fparity_en: 6:6
Fparity_odd: 7:7
Frxblvl: 9:8
Fnco: 31:16
Ftxfull: 0:0
Frxfull: 1:1
Ftxempty: 2:2
Ftxidle: 3:3
Frxidle: 4:4
Frxempty: 5:5
Frxrst: 0:0
Ftxrst: 1:1
Frxilvl: 4:2
Ftxilvl: 6:5
Ftxlvl: 5:0
Frxlvl: 21:16
Ftxen: 0:0
Ftxval: 1:1
Fval: 23:0
Fen: 31:31
This design unit is implemented in usb_osc.sv
of usb_osc
| Name | Type | Default Value | Description |
|---|---|---|---|
| USB_EN_RDLY | time | 5us | |
| USB_VAL_RDLY | time | 80ns | |
| USB_VAL_FDLY | time | 80ns | |
| UsbClkPeriod | real | 1000000/48 | ~20833.33333ps (48Mhz) |
| Name | Direction | Type | Description |
|---|---|---|---|
| vcore_pok_h_i | in | logic | VCORE POK @3.3V |
| usb_en_i | in | logic | USB Source Clock Enable |
| usb_ref_val_i | in | logic | USB Reference Valid |
| usb_clk_o | out | logic | USB Clock Output |
This design unit is implemented in usbdev_aon_wake.sv
This file depends on: usbdev_pkg.sv, prim_flop_2sync.sv, prim_filter.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_aon_i | in | logic | |
| rst_aon_ni | in | logic | |
| usb_out_of_rst_alw_i | in | logic | signals tagged upwr are only valid when this is set |
| usb_dp_async_alw_i | in | logic | These come from the chip pin |
| usb_dn_async_alw_i | in | logic | |
| usb_dppullup_en_alw_i | in | logic | These come from post pinmux sleep handling logic |
| usb_dnpullup_en_alw_i | in | logic | |
| usb_aon_wake_en_upwr_i | in | logic | Register signals from IP |
| usb_aon_woken_upwr_i | in | logic | |
| usb_suspended_upwr_i | in | logic | Status from IP, must be valid for long enough for aon clock to catch (>15us) |
| wake_req_alw_o | out | logic | wake/powerup request |
| state_debug_o | out | awk_state_e | state debug information |
aon clock is ~200kHz so 4 cycle filter is about 20us as well as noise debounce this gives the main IP time to detect resume if it didn't turn off
This design unit is implemented in usbdev_flop_2syncpulse.sv
This file depends on: prim_flop_2sync.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 16 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | receive clock |
| rst_ni | in | logic | |
| d_i | in | [Width-1:0] logic | |
| q_o | out | [Width-1:0] logic |
This design unit is implemented in usbdev_iomux.sv
This file depends on: usbdev_reg_pkg.sv, prim_flop_2sync.sv, prim_generic_clock_mux2.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clk_usb_48mhz_i | in | logic | use usb_ prefix for signals in this clk |
| rst_usb_48mhz_ni | in | logic | |
| sys_hw2reg_sense_o | out | usbdev_hw2reg_phy_pins_sense_reg_t | Register interface (system clk) |
| sys_reg2hw_drive_i | in | usbdev_reg2hw_phy_pins_drive_reg_t | |
| sys_reg2hw_config_i | in | usbdev_reg2hw_phy_config_reg_t | |
| sys_usb_sense_o | out | logic | |
| cio_usb_d_i | in | logic | External USB Interface(s) (async) |
| cio_usb_dp_i | in | logic | |
| cio_usb_dn_i | in | logic | |
| cio_usb_d_o | out | logic | |
| cio_usb_se0_o | out | logic | |
| cio_usb_dp_o | out | logic | |
| cio_usb_dn_o | out | logic | |
| cio_usb_oe_o | out | logic | |
| cio_usb_tx_mode_se_o | out | logic | |
| cio_usb_sense_i | in | logic | |
| cio_usb_dp_pullup_en_o | out | logic | |
| cio_usb_dn_pullup_en_o | out | logic | |
| cio_usb_suspend_o | out | logic | |
| usb_rx_d_o | out | logic | Internal USB Interface (usb clk) |
| usb_rx_dp_o | out | logic | |
| usb_rx_dn_o | out | logic | |
| usb_tx_d_i | in | logic | |
| usb_tx_se0_i | in | logic | |
| usb_tx_oe_i | in | logic | |
| usb_pwr_sense_o | out | logic | |
| usb_pullup_en_i | in | logic | |
| usb_suspend_i | in | logic |
USB pins sense (to sysclk)
USB input pins (to usbclk)
Use explicit muxes for the critical output signals, we do this to avoid glitches from synthesized logic on these signals. Clock muxes should be used here to achieve the best match between rising and falling edges on an ASIC. This mismatch on the data line degrades performance in the JK-KJ jitter test.
This design unit is implemented in usbdev_reg_pkg.sv
This design unit is implemented in usbdev_reg_top.sv
This file depends on: usbdev_reg_pkg.sv, prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 12 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| tl_win_o | out | tl_h2d_t [1] | Output port for window |
| tl_win_i | in | tl_d2h_t [1] | |
| reg2hw | out | usbdev_reg2hw_t | Write |
| hw2reg | in | usbdev_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Create Socket_1n
Fpkt_received: 0:0
Fpkt_sent: 1:1
Fdisconnected: 2:2
Fhost_lost: 3:3
Flink_reset: 4:4
Flink_suspend: 5:5
Flink_resume: 6:6
Fav_empty: 7:7
Frx_full: 8:8
Fav_overflow: 9:9
Flink_in_err: 10:10
Frx_crc_err: 11:11
Frx_pid_err: 12:12
Frx_bitstuff_err: 13:13
Fframe: 14:14
Fconnected: 15:15
Flink_out_err: 16:16
Fpkt_received: 0:0
Fpkt_sent: 1:1
Fdisconnected: 2:2
Fhost_lost: 3:3
Flink_reset: 4:4
Flink_suspend: 5:5
Flink_resume: 6:6
Fav_empty: 7:7
Frx_full: 8:8
Fav_overflow: 9:9
Flink_in_err: 10:10
Frx_crc_err: 11:11
Frx_pid_err: 12:12
Frx_bitstuff_err: 13:13
Fframe: 14:14
Fconnected: 15:15
Flink_out_err: 16:16
Fpkt_received: 0:0
Fpkt_sent: 1:1
Fdisconnected: 2:2
Fhost_lost: 3:3
Flink_reset: 4:4
Flink_suspend: 5:5
Flink_resume: 6:6
Fav_empty: 7:7
Frx_full: 8:8
Fav_overflow: 9:9
Flink_in_err: 10:10
Frx_crc_err: 11:11
Frx_pid_err: 12:12
Frx_bitstuff_err: 13:13
Fframe: 14:14
Fconnected: 15:15
Flink_out_err: 16:16
Fenable: 0:0
Fdevice_address: 22:16
Fframe: 10:0
Fhost_lost: 11:11
Flink_state: 14:12
Fsense: 15:15
Fav_depth: 18:16
Fav_full: 23:23
Frx_depth: 26:24
Frx_empty: 31:31
Fbuffer: 4:0
Fsize: 14:8
Fsetup: 19:19
Fep: 23:20
Fsetup_0: 0:0
Fsetup_1: 1:1
Fsetup_2: 2:2
Fsetup_3: 3:3
Fsetup_4: 4:4
Fsetup_5: 5:5
Fsetup_6: 6:6
Fsetup_7: 7:7
Fsetup_8: 8:8
Fsetup_9: 9:9
Fsetup_10: 10:10
Fsetup_11: 11:11
Fout_0: 0:0
Fout_1: 1:1
Fout_2: 2:2
Fout_3: 3:3
Fout_4: 4:4
Fout_5: 5:5
Fout_6: 6:6
Fout_7: 7:7
Fout_8: 8:8
Fout_9: 9:9
Fout_10: 10:10
Fout_11: 11:11
Fsent_0: 0:0
Fsent_1: 1:1
Fsent_2: 2:2
Fsent_3: 3:3
Fsent_4: 4:4
Fsent_5: 5:5
Fsent_6: 6:6
Fsent_7: 7:7
Fsent_8: 8:8
Fsent_9: 9:9
Fsent_10: 10:10
Fsent_11: 11:11
Fstall_0: 0:0
Fstall_1: 1:1
Fstall_2: 2:2
Fstall_3: 3:3
Fstall_4: 4:4
Fstall_5: 5:5
Fstall_6: 6:6
Fstall_7: 7:7
Fstall_8: 8:8
Fstall_9: 9:9
Fstall_10: 10:10
Fstall_11: 11:11
Fbuffer_0: 4:0
Fsize_0: 14:8
Fpend_0: 30:30
Frdy_0: 31:31
Fbuffer_1: 4:0
Fsize_1: 14:8
Fpend_1: 30:30
Frdy_1: 31:31
Fbuffer_2: 4:0
Fsize_2: 14:8
Fpend_2: 30:30
Frdy_2: 31:31
Fbuffer_3: 4:0
Fsize_3: 14:8
Fpend_3: 30:30
Frdy_3: 31:31
Fbuffer_4: 4:0
Fsize_4: 14:8
Fpend_4: 30:30
Frdy_4: 31:31
Fbuffer_5: 4:0
Fsize_5: 14:8
Fpend_5: 30:30
Frdy_5: 31:31
Fbuffer_6: 4:0
Fsize_6: 14:8
Fpend_6: 30:30
Frdy_6: 31:31
Fbuffer_7: 4:0
Fsize_7: 14:8
Fpend_7: 30:30
Frdy_7: 31:31
Fbuffer_8: 4:0
Fsize_8: 14:8
Fpend_8: 30:30
Frdy_8: 31:31
Fbuffer_9: 4:0
Fsize_9: 14:8
Fpend_9: 30:30
Frdy_9: 31:31
Fbuffer_10: 4:0
Fsize_10: 14:8
Fpend_10: 30:30
Frdy_10: 31:31
Fbuffer_11: 4:0
Fsize_11: 14:8
Fpend_11: 30:30
Frdy_11: 31:31
Fiso_0: 0:0
Fiso_1: 1:1
Fiso_2: 2:2
Fiso_3: 3:3
Fiso_4: 4:4
Fiso_5: 5:5
Fiso_6: 6:6
Fiso_7: 7:7
Fiso_8: 8:8
Fiso_9: 9:9
Fiso_10: 10:10
Fiso_11: 11:11
Fclear_0: 0:0
Fclear_1: 1:1
Fclear_2: 2:2
Fclear_3: 3:3
Fclear_4: 4:4
Fclear_5: 5:5
Fclear_6: 6:6
Fclear_7: 7:7
Fclear_8: 8:8
Fclear_9: 9:9
Fclear_10: 10:10
Fclear_11: 11:11
Frx_dp_i: 0:0
Frx_dn_i: 1:1
Frx_d_i: 2:2
Ftx_dp_o: 8:8
Ftx_dn_o: 9:9
Ftx_d_o: 10:10
Ftx_se0_o: 11:11
Ftx_oe_o: 12:12
Fsuspend_o: 13:13
Fpwr_sense: 16:16
Fdp_o: 0:0
Fdn_o: 1:1
Fd_o: 2:2
Fse0_o: 3:3
Foe_o: 4:4
Ftx_mode_se_o: 5:5
Fdp_pullup_en_o: 6:6
Fdn_pullup_en_o: 7:7
Fsuspend_o: 8:8
Fen: 16:16
Frx_differential_mode: 0:0
Ftx_differential_mode: 1:1
Feop_single_bit: 2:2
Foverride_pwr_sense_en: 3:3
Foverride_pwr_sense_val: 4:4
Fpinflip: 5:5
Fusb_ref_disable: 6:6
Ftx_osc_test_mode: 7:7
Fwake_en: 0:0
Fwake_ack: 1:1
This design unit is implemented in usbdev_usbif.sv
This file depends on: usbdev_linkstate.sv, usb_fs_nb_pe.sv
This module runs on the 48MHz USB clock
| Name | Type | Default Value | Description |
|---|---|---|---|
| NEndpoints | int | 12 | |
| AVFifoWidth | int | 4 | |
| RXFifoWidth | int | 4 | |
| MaxPktSizeByte | int | 64 | |
| NBuf | int | 4 | |
| SramAw | int | 4 | |
| NBufWidth | int | $clog2(NBuf) | derived parameter |
| PktW | int | $clog2(MaxPktSizeByte) | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_48mhz_i | in | logic | 48MHz USB clock |
| rst_ni | in | logic | |
| usb_d_i | in | logic | Pins (synchronous) |
| usb_dp_i | in | logic | |
| usb_dn_i | in | logic | |
| usb_d_o | out | logic | |
| usb_se0_o | out | logic | |
| usb_oe_o | out | logic | |
| usb_pullup_en_o | out | logic | |
| usb_sense_i | in | logic | |
| rx_setup_i | in | [NEndpoints-1:0] logic | receive (OUT or SETUP) side |
| rx_out_i | in | [NEndpoints-1:0] logic | |
| rx_stall_i | in | [NEndpoints-1:0] logic | |
| av_rvalid_i | in | logic | |
| av_rready_o | out | logic | |
| av_rdata_i | in | [AVFifoWidth - 1:0] logic | |
| event_av_empty_o | out | logic | |
| rx_wvalid_o | out | logic | |
| rx_wready_i | in | logic | |
| rx_wdata_o | out | [RXFifoWidth - 1:0] logic | |
| event_rx_full_o | out | logic | |
| setup_received_o | out | logic | |
| out_endpoint_o | out | [3:0] logic | |
| out_endpoint_val_o | out | logic | |
| in_buf_i | in | [NBufWidth - 1:0] logic | transmit (IN) side |
| in_size_i | in | [PktW:0] logic | |
| in_stall_i | in | [NEndpoints-1:0] logic | |
| in_rdy_i | in | [NEndpoints-1:0] logic | |
| set_sent_o | out | logic | |
| in_endpoint_o | out | [3:0] logic | |
| in_endpoint_val_o | out | logic | |
| mem_req_o | out | logic | memory interface |
| mem_write_o | out | logic | |
| mem_addr_o | out | [SramAw-1:0] logic | |
| mem_wdata_o | out | [31:0] logic | |
| mem_rdata_i | in | [31:0] logic | |
| enable_i | in | logic | control |
| devaddr_i | in | [6:0] logic | |
| clr_devaddr_o | out | logic | |
| ep_iso_i | in | [NEndpoints-1:0] logic | |
| cfg_eop_single_bit_i | in | logic | 1: detect a single SE0 bit as EOP |
| cfg_rx_differential_i | in | logic | 1: use differential rx data on usb_d_i |
| tx_osc_test_mode_i | in | logic | Oscillator test mode: constant JK output |
| data_toggle_clear_i | in | [NEndpoints-1:0] logic | Clear the data toggles for an EP |
| frame_start_o | out | logic | status |
| frame_o | out | [10:0] logic | |
| link_state_o | out | [2:0] logic | |
| link_disconnect_o | out | logic | |
| link_connect_o | out | logic | |
| link_reset_o | out | logic | |
| link_active_o | out | logic | |
| link_suspend_o | out | logic | |
| link_resume_o | out | logic | |
| link_in_err_o | out | logic | |
| link_out_err_o | out | logic | |
| host_lost_o | out | logic | |
| rx_crc_err_o | out | logic | |
| rx_pid_err_o | out | logic | |
| rx_bitstuff_err_o | out | logic |
This design unit is implemented in aes_cipher_core.sv
This file depends on: aes_mix_columns.sv, aes_sel_buf_chk.sv, uvm_pkg.sv, aes_prng_masking.sv, aes_sub_bytes.sv, aes_cipher_control.sv, aes_shift_rows.sv, aes_pkg.sv, aes_key_expand.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AES192Enable | bit | 1 | |
| Masking | bit | 0 | |
| SBoxImpl | sbox_impl_e | SBoxImplLut | |
| SecAllowForcingMasks | bit | 0 | |
| NumShares | int | Masking ? 2 : 1 | derived parameter |
| RndCnstMaskingLfsrSeed | masking_lfsr_seed_t | RndCnstMaskingLfsrSeedDefault | |
| RndCnstMskgChunkLfsrPerm | mskg_chunk_lfsr_perm_t | RndCnstMskgChunkLfsrPermDefault | |
| NumChunks | int | 128/WidthPRDClearing | Generate clearing signals of appropriate widths. |
| WidthPRDRow | int | 4*WidthPRDSBox | Extract randomness for masking the input data. The masking PRNG is used for generating both the PRD for the S-Boxes/SubBytes operation as well as for the input data masks. When using any of the masked Canright S-Box implementations, it is important that the SubBytes input masks (generated by the PRNG in Round X-1) and the SubBytes output masks (generated by the PRNG in Round X) are independent. Inside the PRNG, this is achieved by using multiple, separately re-seeded LFSR chunks and by selecting the separate LFSR chunks in alternating fashion. Since the input data masks become the SubBytes input masks in the first round, we select the same 8 bit lanes for the input data masks which are also used to form the SubBytes output mask for the masked Canright S-Box implementations, i.e., the 8 LSBs of the per S-Box PRD. In particular, we have: prd_masking = { prd_key_expand, ... , sb_prd4, sb_out_mask4, sb_prd0, sb_out_mask0 } Where sb_out_maskx contains the SubBytes output mask for byte x (when using a masked Canright S-Box implementation) and sb_prdx contains additional PRD consumed by SubBytes for byte x. When using a masked S-Box implementation other than Canright, we still select the 8 LSBs of the per-S-Box PRD to form the input data mask of the corresponding byte. We do this to distribute the input data masks over all LFSR chunks of the masking PRNG. We do the extraction on a row basis. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| in_valid_i | in | logic | Input handshake signals |
| in_ready_o | out | logic | |
| out_valid_o | out | logic | Output handshake signals |
| out_ready_i | in | logic | |
| cfg_valid_i | in | logic | Used for gating assertions only. |
| op_i | in | ciph_op_e | |
| key_len_i | in | key_len_e | |
| crypt_i | in | logic | |
| crypt_o | out | logic | |
| dec_key_gen_i | in | logic | |
| dec_key_gen_o | out | logic | |
| key_clear_i | in | logic | |
| key_clear_o | out | logic | |
| data_out_clear_i | in | logic | Re-use the cipher core muxes. |
| data_out_clear_o | out | logic | |
| alert_o | out | logic | |
| prd_clearing_i | in | [WidthPRDClearing-1:0] logic | Pseudo-random data for register clearing |
| force_zero_masks_i | in | logic | Useful for SCA only. |
| data_in_mask_o | out | [7:0] [3:0] [3:0] logic | |
| entropy_req_o | out | logic | |
| entropy_ack_i | in | logic | |
| entropy_i | in | [WidthPRDMasking-1:0] logic | |
| state_init_i | in | [7:0] [3:0] [3:0] logic [NumShares] | I/O data & initial key |
| key_init_i | in | [31:0] [7:0] logic [NumShares] | |
| state_o | out | [7:0] [3:0] [3:0] logic [NumShares] |
Cipher data path
Key expand data path
Control
This design unit is implemented in aes_control.sv
This file depends on: prim_flop.sv, aes_reg_status.sv, uvm_pkg.sv, aes_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| SecStartTriggerDelay | int | 0 | |
| StateWidth | int | 6 | Types
$ ./sparse-fsm-encode.py -d 3 -m 6 -n 6 Hamming distance histogram: 0: -- 1: -- 2: -- 3: |||||||||||||||||||| (53.33%) 4: ||||||||||||||| (40.00%) 5: || (6.67%) 6: -- Minimum Hamming distance: 3 Maximum Hamming distance: 5 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| ctrl_qe_i | in | logic | Main control signals |
| ctrl_we_o | out | logic | |
| ctrl_err_storage_i | in | logic | |
| op_i | in | aes_op_e | |
| mode_i | in | aes_mode_e | |
| cipher_op_i | in | ciph_op_e | |
| manual_operation_i | in | logic | |
| start_i | in | logic | |
| key_iv_data_in_clear_i | in | logic | |
| data_out_clear_i | in | logic | |
| prng_reseed_i | in | logic | |
| mux_sel_err_i | in | logic | |
| alert_fatal_i | in | logic | |
| alert_o | out | logic | |
| key_init_qe_i | in | [7:0] logic [2] | I/O register read/write enables |
| iv_qe_i | in | [3:0] logic | |
| data_in_qe_i | in | [3:0] logic | |
| data_out_re_i | in | [3:0] logic | |
| data_in_we_o | out | logic | |
| data_out_we_o | out | logic | |
| data_in_prev_sel_o | out | dip_sel_e | Previous input data register |
| data_in_prev_we_o | out | logic | |
| state_in_sel_o | out | si_sel_e | Cipher I/O muxes |
| add_state_in_sel_o | out | add_si_sel_e | |
| add_state_out_sel_o | out | add_so_sel_e | |
| ctr_incr_o | out | logic | Counter |
| ctr_ready_i | in | logic | |
| ctr_we_i | in | [7:0] logic | |
| cipher_in_valid_o | out | logic | Cipher core control and sync |
| cipher_in_ready_i | in | logic | |
| cipher_out_valid_i | in | logic | |
| cipher_out_ready_o | out | logic | |
| cipher_crypt_o | out | logic | |
| cipher_crypt_i | in | logic | |
| cipher_dec_key_gen_o | out | logic | |
| cipher_dec_key_gen_i | in | logic | |
| cipher_key_clear_o | out | logic | |
| cipher_key_clear_i | in | logic | |
| cipher_data_out_clear_o | out | logic | |
| cipher_data_out_clear_i | in | logic | |
| key_init_sel_o | out | key_init_sel_e | Initial key registers |
| key_init_we_o | out | [7:0] logic [2] | |
| iv_sel_o | out | iv_sel_e | IV registers |
| iv_we_o | out | [7:0] logic | |
| prng_data_req_o | out | logic | Pseudo-random number generator interface |
| prng_data_ack_i | in | logic | |
| prng_reseed_req_o | out | logic | |
| prng_reseed_ack_i | in | logic | |
| start_o | out | logic | Trigger register |
| start_we_o | out | logic | |
| key_iv_data_in_clear_o | out | logic | |
| key_iv_data_in_clear_we_o | out | logic | |
| data_out_clear_o | out | logic | |
| data_out_clear_we_o | out | logic | |
| prng_reseed_o | out | logic | |
| prng_reseed_we_o | out | logic | |
| output_valid_o | out | logic | Status register |
| output_valid_we_o | out | logic | |
| input_ready_o | out | logic | |
| input_ready_we_o | out | logic | |
| idle_o | out | logic | |
| idle_we_o | out | logic | |
| stall_o | out | logic | |
| stall_we_o | out | logic | |
| output_lost_i | in | logic | |
| output_lost_o | out | logic | |
| output_lost_we_o | out | logic |
We only use clean initial keys. Either software/counter has updated
all initial key registers, or
none of the initial key registers but the registers were updated in the past.
We only use clean and unused IVs. Either software/counter has updated
all IV registers, or
none of the IV registers but the registers were updated in the past and this particular IV has not yet been used.
This design unit is implemented in aes_ctr.sv
This file depends on: prim_flop.sv, uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| StateWidth | int | 5 | Types
$ ./sparse-fsm-encode.py -d 3 -m 3 -n 5 Hamming distance histogram: 0: -- 1: -- 2: -- 3: |||||||||||||||||||| (66.67%) 4: |||||||||| (33.33%) 5: -- Minimum Hamming distance: 3 Maximum Hamming distance: 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| incr_i | in | logic | |
| ready_o | out | logic | |
| alert_o | out | logic | |
| ctr_i | in | [15:0] [7:0] logic | 8 times 2 bytes |
| ctr_o | out | [15:0] [7:0] logic | 8 times 2 bytes |
| ctr_we_o | out | [7:0] logic |
This design unit is implemented in aes_prng_clearing.sv
This file depends on: uvm_pkg.sv, prim_lfsr.sv, prim_cipher_pkg.sv, aes_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 64 | At the moment we just support a width of 64. |
| RndCnstLfsrSeed | clearing_lfsr_seed_t | RndCnstClearingLfsrSeedDefault | |
| RndCnstLfsrPerm | clearing_lfsr_perm_t | RndCnstClearingLfsrPermDefault |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| data_req_i | in | logic | Connections to AES internals, PRNG consumers |
| data_ack_o | out | logic | |
| data_o | out | [Width-1:0] logic | |
| reseed_req_i | in | logic | |
| reseed_ack_o | out | logic | |
| entropy_req_o | out | logic | Connections to outer world, LFSR re-seed |
| entropy_ack_i | in | logic | |
| entropy_i | in | [Width-1:0] logic |
LFSR instance
This design unit is implemented in aes_sel_buf_chk.sv
This file depends on: uvm_pkg.sv, prim_buf.sv, aes_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Num | int | 2 | |
| Width | int | 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Used for assertions only. |
| rst_ni | in | logic | Used for assertions only. |
| sel_i | in | [Width-1:0] logic | |
| sel_o | out | [Width-1:0] logic | |
| err_o | out | logic |
This design unit is implemented in alert_handler_reg_top.sv
This file depends on: prim_subreg_ext.sv, alert_handler_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AW | int | 10 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_i | in | tl_h2d_t | Below Regster interface can be changed |
| tl_o | out | tl_d2h_t | |
| reg2hw | out | alert_handler_reg2hw_t | Write |
| hw2reg | in | alert_handler_hw2reg_t | Read |
| devmode_i | in | logic | If 1, explicit error return for unmapped register access |
Fclassa: 0:0
Fclassb: 1:1
Fclassc: 2:2
Fclassd: 3:3
Fclassa: 0:0
Fclassb: 1:1
Fclassc: 2:2
Fclassd: 3:3
Fclassa: 0:0
Fclassb: 1:1
Fclassc: 2:2
Fclassd: 3:3
Fen_a_0: 0:0
Fen_a_1: 1:1
Fen_a_2: 2:2
Fen_a_3: 3:3
Fen_a_4: 4:4
Fen_a_5: 5:5
Fen_a_6: 6:6
Fen_a_7: 7:7
Fen_a_8: 8:8
Fen_a_9: 9:9
Fen_a_10: 10:10
Fen_a_11: 11:11
Fen_a_12: 12:12
Fen_a_13: 13:13
Fen_a_14: 14:14
Fen_a_15: 15:15
Fen_a_16: 16:16
Fen_a_17: 17:17
Fen_a_18: 18:18
Fen_a_19: 19:19
Fen_a_20: 20:20
Fen_a_21: 21:21
Fen_a_22: 22:22
Fen_a_23: 23:23
Fen_a_24: 24:24
Fen_a_25: 25:25
Fen_a_26: 26:26
Fclass_a_0: 1:0
Fclass_a_1: 3:2
Fclass_a_2: 5:4
Fclass_a_3: 7:6
Fclass_a_4: 9:8
Fclass_a_5: 11:10
Fclass_a_6: 13:12
Fclass_a_7: 15:14
Fclass_a_8: 17:16
Fclass_a_9: 19:18
Fclass_a_10: 21:20
Fclass_a_11: 23:22
Fclass_a_12: 25:24
Fclass_a_13: 27:26
Fclass_a_14: 29:28
Fclass_a_15: 31:30
Fclass_a_16: 1:0
Fclass_a_17: 3:2
Fclass_a_18: 5:4
Fclass_a_19: 7:6
Fclass_a_20: 9:8
Fclass_a_21: 11:10
Fclass_a_22: 13:12
Fclass_a_23: 15:14
Fclass_a_24: 17:16
Fclass_a_25: 19:18
Fclass_a_26: 21:20
Fa_0: 0:0
Fa_1: 1:1
Fa_2: 2:2
Fa_3: 3:3
Fa_4: 4:4
Fa_5: 5:5
Fa_6: 6:6
Fa_7: 7:7
Fa_8: 8:8
Fa_9: 9:9
Fa_10: 10:10
Fa_11: 11:11
Fa_12: 12:12
Fa_13: 13:13
Fa_14: 14:14
Fa_15: 15:15
Fa_16: 16:16
Fa_17: 17:17
Fa_18: 18:18
Fa_19: 19:19
Fa_20: 20:20
Fa_21: 21:21
Fa_22: 22:22
Fa_23: 23:23
Fa_24: 24:24
Fa_25: 25:25
Fa_26: 26:26
Fen_la_0: 0:0
Fen_la_1: 1:1
Fen_la_2: 2:2
Fen_la_3: 3:3
Fclass_la_0: 1:0
Fclass_la_1: 3:2
Fclass_la_2: 5:4
Fclass_la_3: 7:6
Fla_0: 0:0
Fla_1: 1:1
Fla_2: 2:2
Fla_3: 3:3
Fen: 0:0
Flock: 1:1
Fen_e0: 2:2
Fen_e1: 3:3
Fen_e2: 4:4
Fen_e3: 5:5
Fmap_e0: 7:6
Fmap_e1: 9:8
Fmap_e2: 11:10
Fmap_e3: 13:12
Fen: 0:0
Flock: 1:1
Fen_e0: 2:2
Fen_e1: 3:3
Fen_e2: 4:4
Fen_e3: 5:5
Fmap_e0: 7:6
Fmap_e1: 9:8
Fmap_e2: 11:10
Fmap_e3: 13:12
Fen: 0:0
Flock: 1:1
Fen_e0: 2:2
Fen_e1: 3:3
Fen_e2: 4:4
Fen_e3: 5:5
Fmap_e0: 7:6
Fmap_e1: 9:8
Fmap_e2: 11:10
Fmap_e3: 13:12
Fen: 0:0
Flock: 1:1
Fen_e0: 2:2
Fen_e1: 3:3
Fen_e2: 4:4
Fen_e3: 5:5
Fmap_e0: 7:6
Fmap_e1: 9:8
Fmap_e2: 11:10
Fmap_e3: 13:12
This design unit is implemented in csrng_block_encrypt.sv
This file depends on: aes_cipher_core.sv, prim_fifo_sync.sv, aes_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| SBoxImpl | sbox_impl_e | aes_pkg::SBoxImplLut | |
| Cmd | int | 3 | |
| StateId | int | 4 | |
| BlkLen | int | 128 | |
| KeyLen | int | 256 | |
| BlkEncFifoDepth | int | 1 | |
| BlkEncFifoWidth | int | BlkLen+StateId+Cmd | |
| NumShares | int | 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| block_encrypt_bypass_i | in | logic | |
| block_encrypt_enable_i | in | logic | |
| block_encrypt_lc_hw_debug_not_on_i | in | logic | |
| block_encrypt_req_i | in | logic | |
| block_encrypt_rdy_o | out | logic | |
| block_encrypt_key_i | in | [KeyLen-1:0] logic | |
| block_encrypt_v_i | in | [BlkLen-1:0] logic | |
| block_encrypt_cmd_i | in | [Cmd-1:0] logic | |
| block_encrypt_id_i | in | [StateId-1:0] logic | |
| block_encrypt_ack_o | out | logic | |
| block_encrypt_rdy_i | in | logic | |
| block_encrypt_cmd_o | out | [Cmd-1:0] logic | |
| block_encrypt_id_o | out | [StateId-1:0] logic | |
| block_encrypt_v_o | out | [BlkLen-1:0] logic | |
| block_encrypt_aes_cipher_sm_err_o | out | logic | |
| block_encrypt_sfifo_blkenc_err_o | out | [2:0] logic |
Cipher core
This design unit is implemented in csrng_cmd_stage.sv
This file depends on: csrng_pkg.sv, prim_flop.sv, prim_fifo_sync.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| CmdFifoWidth | int | 32 | |
| CmdFifoDepth | int | 16 | |
| StateId | int | 4 | |
| GenBitsFifoWidth | int | 1+128 | |
| GenBitsFifoDepth | int | 1 | |
| StateWidth | int | 6 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| cs_enable_i | in | logic | command in |
| cmd_stage_vld_i | in | logic | |
| cmd_stage_shid_i | in | [StateId-1:0] logic | |
| cmd_stage_bus_i | in | [CmdFifoWidth-1:0] logic | |
| cmd_stage_rdy_o | out | logic | |
| cmd_arb_req_o | out | logic | command to arbiter |
| cmd_arb_sop_o | out | logic | |
| cmd_arb_mop_o | out | logic | |
| cmd_arb_eop_o | out | logic | |
| cmd_arb_gnt_i | in | logic | |
| cmd_arb_bus_o | out | [CmdFifoWidth-1:0] logic | |
| cmd_ack_i | in | logic | ack from core |
| cmd_ack_sts_i | in | logic | |
| cmd_stage_ack_o | out | logic | ack to app i/f |
| cmd_stage_ack_sts_o | out | logic | |
| genbits_vld_i | in | logic | genbits from core |
| genbits_bus_i | in | [127:0] logic | |
| genbits_fips_i | in | logic | |
| genbits_vld_o | out | logic | genbits to app i/f |
| genbits_rdy_i | in | logic | |
| genbits_bus_o | out | [127:0] logic | |
| genbits_fips_o | out | logic | |
| cmd_stage_sfifo_cmd_err_o | out | [2:0] logic | error indication |
| cmd_stage_sfifo_genbits_err_o | out | [2:0] logic | |
| cmd_stage_sm_err_o | out | logic |
This primitive is used to place a size-only constraint on the flops in order to prevent FSM state encoding optimizations.
This design unit is implemented in csrng_ctr_drbg_cmd.sv
This file depends on: csrng_pkg.sv, prim_fifo_sync.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Cmd | int | 3 | |
| StateId | int | 4 | |
| BlkLen | int | 128 | |
| KeyLen | int | 256 | |
| SeedLen | int | 384 | |
| CtrLen | int | 32 | |
| CmdreqFifoDepth | int | 1 | |
| CmdreqFifoWidth | int | KeyLen+BlkLen+CtrLen+1+2*SeedLen+StateId+Cmd | |
| RCStageFifoDepth | int | 1 | |
| RCStageFifoWidth | int | CtrLen+1+SeedLen+Cmd | |
| KeyVRCFifoDepth | int | 1 | |
| KeyVRCFifoWidth | int | KeyLen+BlkLen+CtrLen+1+SeedLen+StateId+Cmd |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| ctr_drbg_cmd_enable_i | in | logic | |
| ctr_drbg_cmd_req_i | in | logic | |
| ctr_drbg_cmd_rdy_o | out | logic | ready to process the req above |
| ctr_drbg_cmd_ccmd_i | in | [Cmd-1:0] logic | current command |
| ctr_drbg_cmd_inst_id_i | in | [StateId-1:0] logic | instantance id |
| ctr_drbg_cmd_entropy_i | in | [SeedLen-1:0] logic | es entropy |
| ctr_drbg_cmd_entropy_fips_i | in | logic | es entropy)fips |
| ctr_drbg_cmd_adata_i | in | [SeedLen-1:0] logic | additional data |
| ctr_drbg_cmd_key_i | in | [KeyLen-1:0] logic | |
| ctr_drbg_cmd_v_i | in | [BlkLen-1:0] logic | |
| ctr_drbg_cmd_rc_i | in | [CtrLen-1:0] logic | |
| ctr_drbg_cmd_fips_i | in | logic | |
| ctr_drbg_cmd_ack_o | out | logic | final ack when update process has been completed |
| ctr_drbg_cmd_sts_o | out | logic | final ack status |
| ctr_drbg_cmd_rdy_i | in | logic | ready to process the ack above |
| ctr_drbg_cmd_ccmd_o | out | [Cmd-1:0] logic | |
| ctr_drbg_cmd_inst_id_o | out | [StateId-1:0] logic | |
| ctr_drbg_cmd_fips_o | out | logic | |
| ctr_drbg_cmd_adata_o | out | [SeedLen-1:0] logic | |
| ctr_drbg_cmd_key_o | out | [KeyLen-1:0] logic | |
| ctr_drbg_cmd_v_o | out | [BlkLen-1:0] logic | |
| ctr_drbg_cmd_rc_o | out | [CtrLen-1:0] logic | |
| cmd_upd_req_o | out | logic | |
| upd_cmd_rdy_i | in | logic | |
| cmd_upd_ccmd_o | out | [Cmd-1:0] logic | |
| cmd_upd_inst_id_o | out | [StateId-1:0] logic | |
| cmd_upd_pdata_o | out | [SeedLen-1:0] logic | |
| cmd_upd_key_o | out | [KeyLen-1:0] logic | |
| cmd_upd_v_o | out | [BlkLen-1:0] logic | |
| upd_cmd_ack_i | in | logic | |
| cmd_upd_rdy_o | out | logic | |
| upd_cmd_ccmd_i | in | [Cmd-1:0] logic | |
| upd_cmd_inst_id_i | in | [StateId-1:0] logic | |
| upd_cmd_key_i | in | [KeyLen-1:0] logic | |
| upd_cmd_v_i | in | [BlkLen-1:0] logic | |
| ctr_drbg_cmd_sfifo_cmdreq_err_o | out | [2:0] logic | misc |
| ctr_drbg_cmd_sfifo_rcstage_err_o | out | [2:0] logic | |
| ctr_drbg_cmd_sfifo_keyvrc_err_o | out | [2:0] logic |
This design unit is implemented in csrng_ctr_drbg_gen.sv
This file depends on: csrng_pkg.sv, prim_flop.sv, prim_fifo_sync.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Cmd | int | 3 | |
| StateId | int | 4 | |
| BlkLen | int | 128 | |
| KeyLen | int | 256 | |
| SeedLen | int | 384 | |
| CtrLen | int | 32 | |
| GenreqFifoDepth | int | 1 | |
| GenreqFifoWidth | int | KeyLen+BlkLen+CtrLen+1+SeedLen+StateId+Cmd | |
| BlkEncAckFifoDepth | int | 1 | |
| BlkEncAckFifoWidth | int | BlkLen+StateId+Cmd | |
| AdstageFifoDepth | int | 1 | |
| AdstageFifoWidth | int | KeyLen+BlkLen+CtrLen+1+SeedLen | |
| RCStageFifoDepth | int | 1 | |
| RCStageFifoWidth | int | BlkLen+CtrLen+1 | |
| GenbitsFifoDepth | int | 1 | |
| GenbitsFifoWidth | int | 1+BlkLen+KeyLen+BlkLen+CtrLen+StateId+Cmd | |
| StateWidth | int | 5 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| ctr_drbg_gen_enable_i | in | logic | |
| ctr_drbg_gen_req_i | in | logic | |
| ctr_drbg_gen_rdy_o | out | logic | ready to process the req above |
| ctr_drbg_gen_ccmd_i | in | [Cmd-1:0] logic | current command |
| ctr_drbg_gen_inst_id_i | in | [StateId-1:0] logic | instantance id |
| ctr_drbg_gen_fips_i | in | logic | fips |
| ctr_drbg_gen_adata_i | in | [SeedLen-1:0] logic | additional data |
| ctr_drbg_gen_key_i | in | [KeyLen-1:0] logic | |
| ctr_drbg_gen_v_i | in | [BlkLen-1:0] logic | |
| ctr_drbg_gen_rc_i | in | [CtrLen-1:0] logic | |
| ctr_drbg_gen_ack_o | out | logic | final ack when update process has been completed |
| ctr_drbg_gen_sts_o | out | logic | final ack status |
| ctr_drbg_gen_rdy_i | in | logic | ready to process the ack above |
| ctr_drbg_gen_ccmd_o | out | [Cmd-1:0] logic | |
| ctr_drbg_gen_inst_id_o | out | [StateId-1:0] logic | |
| ctr_drbg_gen_key_o | out | [KeyLen-1:0] logic | |
| ctr_drbg_gen_v_o | out | [BlkLen-1:0] logic | |
| ctr_drbg_gen_rc_o | out | [CtrLen-1:0] logic | |
| ctr_drbg_gen_bits_o | out | [BlkLen-1:0] logic | |
| ctr_drbg_gen_fips_o | out | logic | |
| gen_upd_req_o | out | logic | update interface |
| upd_gen_rdy_i | in | logic | |
| gen_upd_ccmd_o | out | [Cmd-1:0] logic | |
| gen_upd_inst_id_o | out | [StateId-1:0] logic | |
| gen_upd_pdata_o | out | [SeedLen-1:0] logic | |
| gen_upd_key_o | out | [KeyLen-1:0] logic | |
| gen_upd_v_o | out | [BlkLen-1:0] logic | |
| upd_gen_ack_i | in | logic | |
| gen_upd_rdy_o | out | logic | |
| upd_gen_ccmd_i | in | [Cmd-1:0] logic | |
| upd_gen_inst_id_i | in | [StateId-1:0] logic | |
| upd_gen_key_i | in | [KeyLen-1:0] logic | |
| upd_gen_v_i | in | [BlkLen-1:0] logic | |
| block_encrypt_req_o | out | logic | block encrypt interface |
| block_encrypt_rdy_i | in | logic | |
| block_encrypt_ccmd_o | out | [Cmd-1:0] logic | |
| block_encrypt_inst_id_o | out | [StateId-1:0] logic | |
| block_encrypt_key_o | out | [KeyLen-1:0] logic | |
| block_encrypt_v_o | out | [BlkLen-1:0] logic | |
| block_encrypt_ack_i | in | logic | |
| block_encrypt_rdy_o | out | logic | |
| block_encrypt_ccmd_i | in | [Cmd-1:0] logic | |
| block_encrypt_inst_id_i | in | [StateId-1:0] logic | |
| block_encrypt_v_i | in | [BlkLen-1:0] logic | |
| ctr_drbg_gen_sfifo_gbencack_err_o | out | [2:0] logic | misc |
| ctr_drbg_gen_sfifo_grcstage_err_o | out | [2:0] logic | |
| ctr_drbg_gen_sfifo_ggenreq_err_o | out | [2:0] logic | |
| ctr_drbg_gen_sfifo_gadstage_err_o | out | [2:0] logic | |
| ctr_drbg_gen_sfifo_ggenbits_err_o | out | [2:0] logic | |
| ctr_drbg_gen_sm_err_o | out | logic |
This primitive is used to place a size-only constraint on the flops in order to prevent FSM state encoding optimizations.
This design unit is implemented in csrng_ctr_drbg_upd.sv
This file depends on: prim_flop.sv, prim_fifo_sync.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Cmd | int | 3 | |
| StateId | int | 4 | |
| BlkLen | int | 128 | |
| KeyLen | int | 256 | |
| SeedLen | int | 384 | |
| CtrLen | int | 32 | |
| UpdReqFifoDepth | int | 1 | |
| UpdReqFifoWidth | int | KeyLen+BlkLen+SeedLen+StateId+Cmd | |
| BlkEncReqFifoDepth | int | 1 | |
| BlkEncReqFifoWidth | int | KeyLen+BlkLen+StateId+Cmd | |
| BlkEncAckFifoDepth | int | 1 | |
| BlkEncAckFifoWidth | int | BlkLen+StateId+Cmd | |
| PDataFifoDepth | int | 1 | |
| PDataFifoWidth | int | SeedLen | |
| FinalFifoDepth | int | 1 | |
| FinalFifoWidth | int | KeyLen+BlkLen+StateId+Cmd | |
| BlkEncStateWidth | int | 5 | |
| OutBlkStateWidth | int | 6 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| ctr_drbg_upd_enable_i | in | logic | |
| ctr_drbg_upd_req_i | in | logic | |
| ctr_drbg_upd_rdy_o | out | logic | ready to process the req above |
| ctr_drbg_upd_ccmd_i | in | [Cmd-1:0] logic | |
| ctr_drbg_upd_inst_id_i | in | [StateId-1:0] logic | instantance id |
| ctr_drbg_upd_pdata_i | in | [SeedLen-1:0] logic | provided_data |
| ctr_drbg_upd_key_i | in | [KeyLen-1:0] logic | |
| ctr_drbg_upd_v_i | in | [BlkLen-1:0] logic | |
| ctr_drbg_upd_ccmd_o | out | [Cmd-1:0] logic | |
| ctr_drbg_upd_inst_id_o | out | [StateId-1:0] logic | |
| ctr_drbg_upd_key_o | out | [KeyLen-1:0] logic | |
| ctr_drbg_upd_v_o | out | [BlkLen-1:0] logic | |
| ctr_drbg_upd_ack_o | out | logic | final ack when update process has been completed |
| ctr_drbg_upd_rdy_i | in | logic | readu to process the ack above |
| block_encrypt_req_o | out | logic | |
| block_encrypt_rdy_i | in | logic | |
| block_encrypt_ccmd_o | out | [Cmd-1:0] logic | |
| block_encrypt_inst_id_o | out | [StateId-1:0] logic | |
| block_encrypt_key_o | out | [KeyLen-1:0] logic | |
| block_encrypt_v_o | out | [BlkLen-1:0] logic | |
| block_encrypt_ack_i | in | logic | |
| block_encrypt_rdy_o | out | logic | |
| block_encrypt_ccmd_i | in | [Cmd-1:0] logic | |
| block_encrypt_inst_id_i | in | [StateId-1:0] logic | |
| block_encrypt_v_i | in | [BlkLen-1:0] logic | |
| ctr_drbg_upd_sfifo_updreq_err_o | out | [2:0] logic | |
| ctr_drbg_upd_sfifo_bencreq_err_o | out | [2:0] logic | |
| ctr_drbg_upd_sfifo_bencack_err_o | out | [2:0] logic | |
| ctr_drbg_upd_sfifo_pdata_err_o | out | [2:0] logic | |
| ctr_drbg_upd_sfifo_final_err_o | out | [2:0] logic | |
| ctr_drbg_updbe_sm_err_o | out | logic | |
| ctr_drbg_updob_sm_err_o | out | logic |
This primitive is used to place a size-only constraint on the flops in order to prevent FSM state encoding optimizations.
This primitive is used to place a size-only constraint on the flops in order to prevent FSM state encoding optimizations.
This design unit is implemented in csrng_main_sm.sv
This file depends on: csrng_pkg.sv, prim_flop.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| StateWidth | int | 8 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| acmd_avail_i | in | logic | |
| acmd_accept_o | out | logic | |
| acmd_i | in | [2:0] logic | |
| acmd_eop_i | in | logic | |
| ctr_drbg_cmd_req_rdy_i | in | logic | |
| flag0_i | in | logic | |
| cmd_entropy_req_o | out | logic | |
| cmd_entropy_avail_i | in | logic | |
| instant_req_o | out | logic | |
| reseed_req_o | out | logic | |
| generate_req_o | out | logic | |
| update_req_o | out | logic | |
| uninstant_req_o | out | logic | |
| main_sm_err_o | out | logic |
This primitive is used to place a size-only constraint on the flops in order to prevent FSM state encoding optimizations.
This design unit is implemented in csrng_state_db.sv
This file depends on: csrng_pkg.sv, uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NApps | int | 4 | |
| StateId | int | 4 | |
| BlkLen | int | 128 | |
| KeyLen | int | 256 | |
| CtrLen | int | 32 | |
| Cmd | int | 3 | |
| InternalStateWidth | int | 2+KeyLen+BlkLen+CtrLen | |
| RegInternalStateWidth | int | 30+InternalStateWidth | |
| RegW | int | 32 | |
| MaxNApps | int | 16 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| state_db_enable_i | in | logic | |
| state_db_rd_req_i | in | logic | |
| state_db_rd_inst_id_i | in | [StateId-1:0] logic | |
| state_db_rd_key_o | out | [KeyLen-1:0] logic | |
| state_db_rd_v_o | out | [BlkLen-1:0] logic | |
| state_db_rd_res_ctr_o | out | [CtrLen-1:0] logic | |
| state_db_rd_inst_st_o | out | logic | |
| state_db_rd_fips_o | out | logic | |
| state_db_wr_req_i | in | logic | write interface |
| state_db_wr_req_rdy_o | out | logic | |
| state_db_wr_inst_id_i | in | [StateId-1:0] logic | |
| state_db_wr_fips_i | in | logic | |
| state_db_wr_ccmd_i | in | [Cmd-1:0] logic | |
| state_db_wr_key_i | in | [KeyLen-1:0] logic | |
| state_db_wr_v_i | in | [BlkLen-1:0] logic | |
| state_db_wr_res_ctr_i | in | [CtrLen-1:0] logic | |
| state_db_wr_sts_i | in | logic | |
| state_db_lc_en_i | in | logic | status interface |
| state_db_reg_rd_sel_i | in | logic | |
| state_db_reg_rd_id_i | in | [StateId-1:0] logic | |
| state_db_reg_rd_id_pulse_i | in | logic | |
| state_db_reg_rd_val_o | out | [31:0] logic | |
| state_db_sts_ack_o | out | logic | |
| state_db_sts_sts_o | out | logic | |
| state_db_sts_id_o | out | [StateId-1:0] logic |
This design unit is implemented in debug_rom.sv
Auto-generated code
| Name | Type | Default Value | Description |
|---|---|---|---|
| RomSize | int | 19 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| req_i | in | logic | |
| addr_i | in | [63:0] logic | |
| rdata_o | out | [63:0] logic |
This design unit is implemented in debug_rom_one_scratch.sv
Auto-generated code
| Name | Type | Default Value | Description |
|---|---|---|---|
| RomSize | int | 13 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| req_i | in | logic | |
| addr_i | in | [63:0] logic | |
| rdata_o | out | [63:0] logic |
This design unit is implemented in dmi_cdc.sv
This file depends on: prim_fifo_async.sv, dm_pkg.sv
Copyright 2018 ETH Zurich and University of Bologna.
Copyright and related rights are licensed under the Solderpad Hardware
License, Version 0.51 (the “License”); you may not use this file except in
compliance with the License. You may obtain a copy of the License at
http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
or agreed to in writing, software, hardware and materials distributed under
this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
CONDITIONS OF ANY KIND, either express or implied. See the License for the
specific language governing permissions and limitations under the License.
File: axi_riscv_debug_module.sv
Author: Andreas Traber atraber@iis.ee.ethz.ch
Author: Florian Zaruba zarubaf@iis.ee.ethz.ch
Description: Clock domain crossings for JTAG to DMI very heavily based
| Name | Direction | Type | Description |
|---|---|---|---|
| tck_i | in | logic | JTAG side (master side) |
| trst_ni | in | logic | |
| jtag_dmi_req_i | in | dmi_req_t | |
| jtag_dmi_ready_o | out | logic | |
| jtag_dmi_valid_i | in | logic | |
| jtag_dmi_resp_o | out | dmi_resp_t | |
| jtag_dmi_valid_o | out | logic | |
| jtag_dmi_ready_i | in | logic | |
| clk_i | in | logic | core side (slave side) |
| rst_ni | in | logic | |
| core_dmi_req_o | out | dmi_req_t | |
| core_dmi_valid_o | out | logic | |
| core_dmi_ready_i | in | logic | |
| core_dmi_resp_i | in | dmi_resp_t | |
| core_dmi_ready_o | out | logic | |
| core_dmi_valid_i | in | logic |
This design unit is implemented in dmi_jtag_tap.sv
This file depends on: prim_clock_inv.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| IrLength | int | 5 | |
| IdcodeValue | [31:0] logic | 32'h00000001 | JTAG IDCODE Value |
| Name | Direction | Type | Description |
|---|---|---|---|
| tck_i | in | logic | JTAG test clock pad |
| tms_i | in | logic | JTAG test mode select pad |
| trst_ni | in | logic | JTAG test reset pad |
| td_i | in | logic | JTAG test data input pad |
| td_o | out | logic | JTAG test data output pad |
| tdo_oe_o | out | logic | Data out output enable |
| testmode_i | in | logic | |
| test_logic_reset_o | out | logic | |
| shift_dr_o | out | logic | |
| update_dr_o | out | logic | |
| capture_dr_o | out | logic | |
| dmi_access_o | out | logic | we want to access DMI register |
| dtmcs_select_o | out | logic | JTAG is interested in writing the DTM CSR register |
| dmi_reset_o | out | logic | clear error state |
| dmi_error_i | in | [1:0] logic | |
| dmi_tdi_o | out | logic | test data to submodule |
| dmi_tdo_i | in | logic | test data in from submodule |
This design unit is implemented in edn_ack_sm.sv
This file depends on: prim_flop.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| StateWidth | int | 6 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | logic | |
| ack_o | out | logic | |
| fifo_not_empty_i | in | logic | |
| fifo_pop_o | out | logic | |
| ack_sm_err_o | out | logic |
This primitive is used to place a size-only constraint on the flops in order to prevent FSM state encoding optimizations.
This design unit is implemented in edn_main_sm.sv
This file depends on: prim_flop.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| StateWidth | int | 6 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| auto_req_mode_i | in | logic | |
| seq_auto_req_mode_o | out | logic | |
| auto_req_mode_end_o | out | logic | |
| csrng_cmd_ack_i | in | logic | |
| capt_gencmd_fifo_cnt_o | out | logic | |
| send_gencmd_o | out | logic | |
| max_reqs_cnt_zero_i | in | logic | |
| capt_rescmd_fifo_cnt_o | out | logic | |
| send_rescmd_o | out | logic | |
| cmd_sent_i | in | logic | |
| main_sm_err_o | out | logic |
This design unit is implemented in entropy_src_ack_sm.sv
This file depends on: prim_flop.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| StateWidth | int | 6 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | logic | |
| ack_o | out | logic | |
| fifo_not_empty_i | in | logic | |
| fifo_pop_o | out | logic | |
| ack_sm_err_o | out | logic |
This design unit is implemented in entropy_src_adaptp_ht.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RegWidth | int | 16 | |
| RngBusWidth | int | 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| entropy_bit_i | in | [RngBusWidth-1:0] logic | |
| entropy_bit_vld_i | in | logic | |
| clear_i | in | logic | |
| active_i | in | logic | |
| thresh_hi_i | in | [RegWidth-1:0] logic | |
| thresh_lo_i | in | [RegWidth-1:0] logic | |
| window_wrap_pulse_i | in | logic | |
| test_cnt_o | out | [RegWidth-1:0] logic | |
| test_fail_hi_pulse_o | out | logic | |
| test_fail_lo_pulse_o | out | logic |
This design unit is implemented in entropy_src_bucket_ht.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RegWidth | int | 16 | |
| RngBusWidth | int | 4 | |
| NUM_BINS | int | 2**RngBusWidth |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| entropy_bit_i | in | [RngBusWidth-1:0] logic | |
| entropy_bit_vld_i | in | logic | |
| clear_i | in | logic | |
| active_i | in | logic | |
| thresh_i | in | [RegWidth-1:0] logic | |
| window_wrap_pulse_i | in | logic | |
| test_cnt_o | out | [RegWidth-1:0] logic | |
| test_fail_pulse_o | out | logic |
This design unit is implemented in entropy_src_cntr_reg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RegWidth | int | 16 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clear_i | in | logic | |
| active_i | in | logic | |
| event_i | in | logic | |
| value_o | out | [RegWidth-1:0] logic |
This design unit is implemented in entropy_src_main_sm.sv
This file depends on: prim_flop.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| StateWidth | int | 8 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| enable_i | in | logic | |
| ht_done_pulse_i | in | logic | |
| ht_fail_pulse_i | in | logic | |
| postht_not_empty_i | in | logic | |
| rst_alert_cntr_o | out | logic | |
| bypass_mode_i | in | logic | |
| rst_bypass_mode_o | out | logic | |
| main_stage_rdy_i | in | logic | |
| bypass_stage_rdy_i | in | logic | |
| main_stage_pop_o | out | logic | |
| bypass_stage_pop_o | out | logic | |
| main_sm_err_o | out | logic |
This primitive is used to place a size-only constraint on the flops in order to prevent FSM state encoding optimizations.
This design unit is implemented in entropy_src_markov_ht.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RegWidth | int | 16 | |
| RngBusWidth | int | 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| entropy_bit_i | in | [RngBusWidth-1:0] logic | |
| entropy_bit_vld_i | in | logic | |
| clear_i | in | logic | |
| active_i | in | logic | |
| thresh_hi_i | in | [RegWidth-1:0] logic | |
| thresh_lo_i | in | [RegWidth-1:0] logic | |
| window_wrap_pulse_i | in | logic | |
| test_cnt_hi_o | out | [RegWidth-1:0] logic | |
| test_cnt_lo_o | out | [RegWidth-1:0] logic | |
| test_fail_hi_pulse_o | out | logic | |
| test_fail_lo_pulse_o | out | logic |
This design unit is implemented in entropy_src_repcnt_ht.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RegWidth | int | 16 | |
| RngBusWidth | int | 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| entropy_bit_i | in | [RngBusWidth-1:0] logic | |
| entropy_bit_vld_i | in | logic | |
| clear_i | in | logic | |
| active_i | in | logic | |
| thresh_i | in | [RegWidth-1:0] logic | |
| test_cnt_o | out | [RegWidth-1:0] logic | |
| test_fail_pulse_o | out | logic |
This design unit is implemented in entropy_src_watermark_reg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RegWidth | int | 16 | |
| HighWatermark | bit | 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clear_i | in | logic | |
| active_i | in | logic | |
| event_i | in | logic | |
| value_i | in | [RegWidth-1:0] logic | |
| value_o | out | [RegWidth-1:0] logic |
This design unit is implemented in flash_phy_erase.sv
This file depends on: flash_phy_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| pg_erase_req_i | in | logic | interface with controller |
| bk_erase_req_i | in | logic | |
| ack_o | out | logic | |
| pg_erase_req_o | out | logic | interface with flash |
| bk_erase_req_o | out | logic | |
| ack_i | in | logic | |
| done_i | in | logic |
This design unit is implemented in flash_phy_prog.sv
This file depends on: uvm_pkg.sv, prim_secded_hamming_72_64_enc.sv, flash_phy_pkg.sv
flash_phy_prog
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | logic | |
| scramble_i | in | logic | |
| ecc_i | in | logic | |
| sel_i | in | [WordSelW-1:0] logic | |
| data_i | in | [BusWidth-1:0] logic | |
| last_i | in | logic | |
| ack_i | in | logic | ack means request has been accepted by flash |
| done_i | in | logic | done means requested transaction has completed |
| calc_ack_i | in | logic | |
| scramble_ack_i | in | logic | |
| mask_i | in | [DataWidth-1:0] logic | |
| scrambled_data_i | in | [DataWidth-1:0] logic | |
| calc_req_o | out | logic | |
| scramble_req_o | out | logic | |
| req_o | out | logic | |
| last_o | out | logic | last beat of an incoming transaction |
| ack_o | out | logic | |
| block_data_o | out | [DataWidth-1:0] logic | block data does not contain ecc / metadata portion |
| data_o | out | [FullDataWidth-1:0] logic |
This design unit is implemented in flash_phy_rd.sv
This file depends on: prim_secded_hamming_72_64_dec.sv, uvm_pkg.sv, flash_phy_pkg.sv, flash_ctrl_pkg.sv, flash_phy_rd_buffers.sv, prim_fifo_sync.sv, prim_arbiter_tree.sv
flash_phy_core
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| buf_en_i | in | logic | configuration interface from flash controller |
| req_i | in | logic | interface with arbitration unit |
| descramble_i | in | logic | |
| ecc_i | in | logic | |
| prog_i | in | logic | |
| pg_erase_i | in | logic | |
| bk_erase_i | in | logic | |
| addr_i | in | [BusBankAddrW-1:0] logic | |
| part_i | in | flash_part_e | |
| info_sel_i | in | [InfoTypesWidth-1:0] logic | |
| rdy_o | out | logic | |
| data_valid_o | out | logic | |
| data_err_o | out | logic | |
| data_o | out | [BusWidth-1:0] logic | |
| idle_o | out | logic | the entire read pipeline is idle |
| calc_req_o | out | logic | interface with scramble unit |
| descramble_req_o | out | logic | |
| calc_addr_o | out | [BankAddrW-1:0] logic | |
| scrambled_data_o | out | [DataWidth-1:0] logic | |
| calc_ack_i | in | logic | |
| descramble_ack_i | in | logic | |
| mask_i | in | [DataWidth-1:0] logic | |
| descrambled_data_i | in | [DataWidth-1:0] logic | |
| req_o | out | logic | interface to actual flash primitive |
| ack_i | in | logic | request has been accepted |
| done_i | in | logic | actual data return |
| data_i | in | [FullDataWidth-1:0] logic | |
| ecc_single_err_o | out | logic | error status reporting |
| ecc_multi_err_o | out | logic | |
| ecc_addr_o | out | [BusBankAddrW-1:0] logic |
response order FIFO
storage for mask calculations
This design unit is implemented in flash_phy_scramble.sv
This file depends on: prim_gf_mult.sv, flash_phy_pkg.sv, prim_prince.sv
flash_phy_scramble
| Name | Type | Default Value | Description |
|---|---|---|---|
| AddrPadWidth | int | DataWidth - BankAddrW | |
| UnusedWidth | int | KeySize - AddrPadWidth |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| calc_req_i | in | logic | calculate galois multiplier mask |
| op_req_i | in | logic | request primitive operation |
| op_type_i | in | cipher_ops_e | sramble or de-scramble |
| addr_i | in | [BankAddrW-1:0] logic | |
| plain_data_i | in | [DataWidth-1:0] logic | |
| scrambled_data_i | in | [DataWidth-1:0] logic | |
| addr_key_i | in | [KeySize-1:0] logic | |
| data_key_i | in | [KeySize-1:0] logic | |
| calc_ack_o | out | logic | |
| op_ack_o | out | logic | |
| mask_o | out | [DataWidth-1:0] logic | |
| plain_data_o | out | [DataWidth-1:0] logic | |
| scrambled_data_o | out | [DataWidth-1:0] logic |
This design unit is implemented in i2c_fsm.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | clock |
| rst_ni | in | logic | active low reset |
| scl_i | in | logic | serial clock input from i2c bus |
| scl_o | out | logic | serial clock output to i2c bus |
| sda_i | in | logic | serial data input from i2c bus |
| sda_o | out | logic | serial data output to i2c bus |
| host_enable_i | in | logic | enable host functionality |
| target_enable_i | in | logic | enable target functionality |
| fmt_fifo_rvalid_i | in | logic | indicates there is valid data in fmt_fifo |
| fmt_fifo_wvalid_i | in | logic | indicates data is being put into fmt_fifo |
| fmt_fifo_depth_i | in | [5:0] logic | fmt_fifo_depth |
| fmt_fifo_rready_o | out | logic | populates fmt_fifo |
| fmt_byte_i | in | [7:0] logic | byte in fmt_fifo to be sent to target |
| fmt_flag_start_before_i | in | logic | issue start before sending byte |
| fmt_flag_stop_after_i | in | logic | issue stop after sending byte |
| fmt_flag_read_bytes_i | in | logic | indicates byte is an number of reads |
| fmt_flag_read_continue_i | in | logic | host to send Ack to final byte read |
| fmt_flag_nak_ok_i | in | logic | no Ack is expected |
| rx_fifo_wvalid_o | out | logic | high if there is valid data in rx_fifo |
| rx_fifo_wdata_o | out | [7:0] logic | byte in rx_fifo read from target |
| tx_fifo_rvalid_i | in | logic | indicates there is valid data in tx_fifo |
| tx_fifo_wvalid_i | in | logic | indicates data is being put into tx_fifo |
| tx_fifo_depth_i | in | [5:0] logic | tx_fifo_depth |
| tx_fifo_rready_o | out | logic | populates tx_fifo |
| tx_fifo_rdata_i | in | [7:0] logic | byte in tx_fifo to be sent to host |
| acq_fifo_wready_i | in | logic | low if acq_fifo is full |
| acq_fifo_wvalid_o | out | logic | high if there is valid data in acq_fifo |
| acq_fifo_wdata_o | out | [9:0] logic | byte and signal in acq_fifo read from target |
| host_idle_o | out | logic | indicates the host is idle |
| target_idle_o | out | logic | indicates the target is idle |
| thigh_i | in | [15:0] logic | high period of the SCL in clock units |
| tlow_i | in | [15:0] logic | low period of the SCL in clock units |
| t_r_i | in | [15:0] logic | rise time of both SDA and SCL in clock units |
| t_f_i | in | [15:0] logic | fall time of both SDA and SCL in clock units |
| thd_sta_i | in | [15:0] logic | hold time for (repeated) START in clock units |
| tsu_sta_i | in | [15:0] logic | setup time for repeated START in clock units |
| tsu_sto_i | in | [15:0] logic | setup time for STOP in clock units |
| tsu_dat_i | in | [15:0] logic | data setup time in clock units |
| thd_dat_i | in | [15:0] logic | data hold time in clock units |
| t_buf_i | in | [15:0] logic | bus free time between STOP and START in clock units |
| stretch_timeout_i | in | [30:0] logic | max time target may stretch the clock |
| timeout_enable_i | in | logic | assert if target stretches clock past max |
| stretch_en_addr_i | in | logic | enable target stretching clock after address matching |
| stretch_en_tx_i | in | logic | enable target stretching clock after transmit transaction |
| stretch_en_acq_i | in | logic | enable target stretching clock after acquire transaction |
| stretch_stop_i | in | logic | stop stretching clock and resume normal operation |
| host_timeout_i | in | [31:0] logic | max time target waits for host to pull clock down |
| target_address0_i | in | [6:0] logic | |
| target_mask0_i | in | [6:0] logic | |
| target_address1_i | in | [6:0] logic | |
| target_mask1_i | in | [6:0] logic | |
| event_nak_o | out | logic | target didn't Ack when expected |
| event_scl_interference_o | out | logic | other device forcing SCL low |
| event_sda_interference_o | out | logic | other device forcing SDA low |
| event_stretch_timeout_o | out | logic | target stretches clock past max time |
| event_sda_unstable_o | out | logic | SDA is not constant during SCL pulse |
| event_trans_complete_o | out | logic | Transaction is complete |
| event_tx_empty_o | out | logic | tx_fifo is empty but data is needed |
| event_tx_nonempty_o | out | logic | tx_fifo is nonempty after stop |
| event_ack_stop_o | out | logic | target received stop after ack |
| event_host_timeout_o | out | logic | host ceased sending SCL pulses during ongoing transactn |
This design unit is implemented in ibex_cs_registers.sv
This file depends on: uvm_pkg.sv, ibex_pkg.sv, ibex_csr.sv, ibex_counter.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| DbgTriggerEn | bit | 0 | |
| DbgHwBreakNum | int | 1 | |
| DataIndTiming | bit | 1'b0 | |
| DummyInstructions | bit | 1'b0 | |
| ShadowCSR | bit | 1'b0 | |
| ICache | bit | 1'b0 | |
| MHPMCounterNum | int | 10 | |
| MHPMCounterWidth | int | 40 | |
| PMPEnable | bit | 0 | |
| PMPGranularity | int | 0 | |
| PMPNumRegions | int | 4 | |
| RV32E | bit | 0 | |
| RV32M | rv32m_e | ibex_pkg::RV32MFast | |
| RV32MEnabled | int | (RV32M == RV32MNone) ? 0 : 1 | |
| MISA_VALUE | [31:0] logic | (0 << 0) | (1 << 2) | (0 << 3) | (32'(RV32E) << 4) | (0 << 5) | (32'(!RV32E) << 8) | (RV32MEnabled << 12) | (0 << 13) | (0 << 18) | (1 << 20) | (0 << 23) | (32'(CSR_MISA_MXL) << 30) | M-XLEN |
| MSTATUS_RST_VAL | status_t | '{mie: 1'b0, mpie: 1'b1, mpp: PRIV_LVL_U, mprv: 1'b0, tw: 1'b0} | MSTATUS |
| DCSR_RESET_VAL | dcsr_t | '{ xdebugver: XDEBUGVER_STD, cause: DBG_CAUSE_NONE, prv: PRIV_LVL_M, default: '0 } | DCSR |
| MSTACK_RESET_VAL | status_stk_t | '{ mpie: 1'b1, mpp: PRIV_LVL_U } | MSTACK |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock and Reset |
| rst_ni | in | logic | |
| hart_id_i | in | [31:0] logic | Hart ID |
| priv_mode_id_o | out | priv_lvl_e | Privilege mode |
| priv_mode_if_o | out | priv_lvl_e | |
| priv_mode_lsu_o | out | priv_lvl_e | |
| csr_mstatus_tw_o | out | logic | |
| csr_mtvec_o | out | [31:0] logic | mtvec |
| csr_mtvec_init_i | in | logic | |
| boot_addr_i | in | [31:0] logic | |
| csr_access_i | in | logic | Interface to registers (SRAM like) |
| csr_addr_i | in | csr_num_e | |
| csr_wdata_i | in | [31:0] logic | |
| csr_op_i | in | csr_op_e | |
| csr_op_en_i | in | logic | |
| csr_rdata_o | out | [31:0] logic | |
| irq_software_i | in | logic | interrupts |
| irq_timer_i | in | logic | |
| irq_external_i | in | logic | |
| irq_fast_i | in | [14:0] logic | |
| nmi_mode_i | in | logic | |
| irq_pending_o | out | logic | interrupt request pending |
| irqs_o | out | irqs_t | interrupt requests qualified with mie |
| csr_mstatus_mie_o | out | logic | |
| csr_mepc_o | out | [31:0] logic | |
| csr_pmp_cfg_o | out | pmp_cfg_t [PMPNumRegions] | PMP |
| csr_pmp_addr_o | out | [33:0] logic [PMPNumRegions] | |
| debug_mode_i | in | logic | debug |
| debug_cause_i | in | dbg_cause_e | |
| debug_csr_save_i | in | logic | |
| csr_depc_o | out | [31:0] logic | |
| debug_single_step_o | out | logic | |
| debug_ebreakm_o | out | logic | |
| debug_ebreaku_o | out | logic | |
| trigger_match_o | out | logic | |
| pc_if_i | in | [31:0] logic | |
| pc_id_i | in | [31:0] logic | |
| pc_wb_i | in | [31:0] logic | |
| data_ind_timing_o | out | logic | CPU control bits |
| dummy_instr_en_o | out | logic | |
| dummy_instr_mask_o | out | [2:0] logic | |
| dummy_instr_seed_en_o | out | logic | |
| dummy_instr_seed_o | out | [31:0] logic | |
| icache_enable_o | out | logic | |
| csr_shadow_err_o | out | logic | |
| csr_save_if_i | in | logic | Exception save/restore |
| csr_save_id_i | in | logic | |
| csr_save_wb_i | in | logic | |
| csr_restore_mret_i | in | logic | |
| csr_restore_dret_i | in | logic | |
| csr_save_cause_i | in | logic | |
| csr_mcause_i | in | exc_cause_e | |
| csr_mtval_i | in | [31:0] logic | |
| illegal_csr_insn_o | out | logic | access to non-existent CSR, with wrong priviledge level, or missing write permissions |
| instr_ret_i | in | logic | instr retired in ID/EX stage |
| instr_ret_compressed_i | in | logic | compressed instr retired |
| iside_wait_i | in | logic | core waiting for the iside |
| jump_i | in | logic | jump instr seen (j, jr, jal, jalr) |
| branch_i | in | logic | branch instr seen (bf, bnf) |
| branch_taken_i | in | logic | branch was taken |
| mem_load_i | in | logic | load from memory in this cycle |
| mem_store_i | in | logic | store to memory in this cycle |
| dside_wait_i | in | logic | core waiting for the dside |
| mul_wait_i | in | logic | core waiting for multiply |
| div_wait_i | in | logic | core waiting for divide |
MEPC
MSCRATCH
MCAUSE
MTVAL
MTVEC
DEPC
DSCRATCH0
DSCRATCH1
MSTACK_EPC
MSTACK_CAUSE
mcycle
minstret
This design unit is implemented in ibex_ex_block.sv
This file depends on: ibex_alu.sv, ibex_multdiv_fast.sv, ibex_pkg.sv, ibex_multdiv_slow.sv
Execution stage
Execution block: Hosts ALU and MUL/DIV unit
| Name | Type | Default Value | Description |
|---|---|---|---|
| RV32M | rv32m_e | ibex_pkg::RV32MFast | |
| RV32B | rv32b_e | ibex_pkg::RV32BNone | |
| BranchTargetALU | bit | 0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| alu_operator_i | in | alu_op_e | ALU |
| alu_operand_a_i | in | [31:0] logic | |
| alu_operand_b_i | in | [31:0] logic | |
| alu_instr_first_cycle_i | in | logic | |
| bt_a_operand_i | in | [31:0] logic | Branch Target ALU All of these signals are unusued when BranchTargetALU == 0 |
| bt_b_operand_i | in | [31:0] logic | |
| multdiv_operator_i | in | md_op_e | Multiplier/Divider |
| mult_en_i | in | logic | dynamic enable signal, for FSM control |
| div_en_i | in | logic | dynamic enable signal, for FSM control |
| mult_sel_i | in | logic | static decoder output, for data muxes |
| div_sel_i | in | logic | static decoder output, for data muxes |
| multdiv_signed_mode_i | in | [1:0] logic | |
| multdiv_operand_a_i | in | [31:0] logic | |
| multdiv_operand_b_i | in | [31:0] logic | |
| multdiv_ready_id_i | in | logic | |
| data_ind_timing_i | in | logic | |
| imd_val_we_o | out | [1:0] logic | intermediate val reg |
| imd_val_d_o | out | [33:0] logic [2] | |
| imd_val_q_i | in | [33:0] logic [2] | |
| alu_adder_result_ex_o | out | [31:0] logic | to LSU |
| result_ex_o | out | [31:0] logic | |
| branch_target_o | out | [31:0] logic | to IF |
| branch_decision_o | out | logic | to ID |
| ex_valid_o | out | logic | EX has valid output |
This design unit is implemented in ibex_id_stage.sv
This file depends on: uvm_pkg.sv, ibex_controller.sv, ibex_pkg.sv, ibex_decoder.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RV32E | bit | 0 | |
| RV32M | rv32m_e | ibex_pkg::RV32MFast | |
| RV32B | rv32b_e | ibex_pkg::RV32BNone | |
| DataIndTiming | bit | 1'b0 | |
| BranchTargetALU | bit | 0 | |
| SpecBranch | bit | 0 | |
| WritebackStage | bit | 0 | |
| BranchPredictor | bit | 0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| ctrl_busy_o | out | logic | |
| illegal_insn_o | out | logic | |
| instr_valid_i | in | logic | Interface to IF stage |
| instr_rdata_i | in | [31:0] logic | from IF-ID pipeline registers |
| instr_rdata_alu_i | in | [31:0] logic | from IF-ID pipeline registers |
| instr_rdata_c_i | in | [15:0] logic | from IF-ID pipeline registers |
| instr_is_compressed_i | in | logic | |
| instr_bp_taken_i | in | logic | |
| instr_req_o | out | logic | |
| instr_first_cycle_id_o | out | logic | |
| instr_valid_clear_o | out | logic | kill instr in IF-ID reg |
| id_in_ready_o | out | logic | ID stage is ready for next instr |
| icache_inval_o | out | logic | |
| branch_decision_i | in | logic | Jumps and branches |
| pc_set_o | out | logic | IF and ID stage signals |
| pc_set_spec_o | out | logic | |
| pc_mux_o | out | pc_sel_e | |
| nt_branch_mispredict_o | out | logic | |
| exc_pc_mux_o | out | exc_pc_sel_e | |
| exc_cause_o | out | exc_cause_e | |
| illegal_c_insn_i | in | logic | |
| instr_fetch_err_i | in | logic | |
| instr_fetch_err_plus2_i | in | logic | |
| pc_id_i | in | [31:0] logic | |
| ex_valid_i | in | logic | EX stage has valid output |
| lsu_resp_valid_i | in | logic | LSU has valid output, or is done |
| alu_operator_ex_o | out | alu_op_e | ALU |
| alu_operand_a_ex_o | out | [31:0] logic | |
| alu_operand_b_ex_o | out | [31:0] logic | |
| imd_val_we_ex_i | in | [1:0] logic | Multicycle Operation Stage Register |
| imd_val_d_ex_i | in | [33:0] logic [2] | |
| imd_val_q_ex_o | out | [33:0] logic [2] | |
| bt_a_operand_o | out | [31:0] logic | Branch target ALU |
| bt_b_operand_o | out | [31:0] logic | |
| mult_en_ex_o | out | logic | MUL, DIV |
| div_en_ex_o | out | logic | |
| mult_sel_ex_o | out | logic | |
| div_sel_ex_o | out | logic | |
| multdiv_operator_ex_o | out | md_op_e | |
| multdiv_signed_mode_ex_o | out | [1:0] logic | |
| multdiv_operand_a_ex_o | out | [31:0] logic | |
| multdiv_operand_b_ex_o | out | [31:0] logic | |
| multdiv_ready_id_o | out | logic | |
| csr_access_o | out | logic | CSR |
| csr_op_o | out | csr_op_e | |
| csr_op_en_o | out | logic | |
| csr_save_if_o | out | logic | |
| csr_save_id_o | out | logic | |
| csr_save_wb_o | out | logic | |
| csr_restore_mret_id_o | out | logic | |
| csr_restore_dret_id_o | out | logic | |
| csr_save_cause_o | out | logic | |
| csr_mtval_o | out | [31:0] logic | |
| priv_mode_i | in | priv_lvl_e | |
| csr_mstatus_tw_i | in | logic | |
| illegal_csr_insn_i | in | logic | |
| data_ind_timing_i | in | logic | |
| lsu_req_o | out | logic | Interface to load store unit |
| lsu_we_o | out | logic | |
| lsu_type_o | out | [1:0] logic | |
| lsu_sign_ext_o | out | logic | |
| lsu_wdata_o | out | [31:0] logic | |
| lsu_req_done_i | in | logic | Data req to LSU is complete and instruction can move to writeback (only relevant where writeback stage is present) |
| lsu_addr_incr_req_i | in | logic | |
| lsu_addr_last_i | in | [31:0] logic | |
| csr_mstatus_mie_i | in | logic | Interrupt signals |
| irq_pending_i | in | logic | |
| irqs_i | in | irqs_t | |
| irq_nm_i | in | logic | |
| nmi_mode_o | out | logic | |
| lsu_load_err_i | in | logic | |
| lsu_store_err_i | in | logic | |
| debug_mode_o | out | logic | Debug Signal |
| debug_cause_o | out | dbg_cause_e | |
| debug_csr_save_o | out | logic | |
| debug_req_i | in | logic | |
| debug_single_step_i | in | logic | |
| debug_ebreakm_i | in | logic | |
| debug_ebreaku_i | in | logic | |
| trigger_match_i | in | logic | |
| result_ex_i | in | [31:0] logic | Write back signal |
| csr_rdata_i | in | [31:0] logic | |
| rf_raddr_a_o | out | [4:0] logic | Register file read |
| rf_rdata_a_i | in | [31:0] logic | |
| rf_raddr_b_o | out | [4:0] logic | |
| rf_rdata_b_i | in | [31:0] logic | |
| rf_ren_a_o | out | logic | |
| rf_ren_b_o | out | logic | |
| rf_waddr_id_o | out | [4:0] logic | Register file write (via writeback) |
| rf_wdata_id_o | out | [31:0] logic | |
| rf_we_id_o | out | logic | |
| rf_rd_a_wb_match_o | out | logic | |
| rf_rd_b_wb_match_o | out | logic | |
| rf_waddr_wb_i | in | [4:0] logic | Register write information from writeback (for resolving data hazards) |
| rf_wdata_fwd_wb_i | in | [31:0] logic | |
| rf_write_wb_i | in | logic | |
| en_wb_o | out | logic | |
| instr_type_wb_o | out | wb_instr_type_e | |
| ready_wb_i | in | logic | |
| outstanding_load_wb_i | in | logic | |
| outstanding_store_wb_i | in | logic | |
| perf_jump_o | out | logic | executing a jump instr |
| perf_branch_o | out | logic | executing a branch instr |
| perf_tbranch_o | out | logic | executing a taken branch instr |
| perf_dside_wait_o | out | logic | instruction in ID/EX is awaiting memory access to finish before proceeding |
| perf_mul_wait_o | out | logic | |
| perf_div_wait_o | out | logic | |
| instr_id_done_o | out | logic | |
| instr_id_done_compressed_o | out | logic |
This design unit is implemented in ibex_if_stage.sv
This file depends on: ibex_dummy_instr.sv, ibex_branch_predict.sv, uvm_pkg.sv, ibex_pkg.sv, ibex_prefetch_buffer.sv, ibex_icache.sv, ibex_compressed_decoder.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| DmHaltAddr | int | 32'h1A110800 | |
| DmExceptionAddr | int | 32'h1A110808 | |
| DummyInstructions | bit | 1'b0 | |
| ICache | bit | 1'b0 | |
| ICacheECC | bit | 1'b0 | |
| PCIncrCheck | bit | 1'b0 | |
| BranchPredictor | bit | 1'b0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| boot_addr_i | in | [31:0] logic | also used for mtvec |
| req_i | in | logic | instruction request control |
| instr_req_o | out | logic | instruction cache interface |
| instr_addr_o | out | [31:0] logic | |
| instr_gnt_i | in | logic | |
| instr_rvalid_i | in | logic | |
| instr_rdata_i | in | [31:0] logic | |
| instr_err_i | in | logic | |
| instr_pmp_err_i | in | logic | |
| instr_valid_id_o | out | logic | instr in IF-ID is valid |
| instr_new_id_o | out | logic | instr in IF-ID is new |
| instr_rdata_id_o | out | [31:0] logic | instr for ID stage |
| instr_rdata_alu_id_o | out | [31:0] logic | replicated instr for ID stage to reduce fan-out |
| instr_rdata_c_id_o | out | [15:0] logic | compressed instr for ID stage (mtval), meaningful only if instr_is_compressed_id_o = 1'b1 |
| instr_is_compressed_id_o | out | logic | compressed decoder thinks this is a compressed instr |
| instr_bp_taken_o | out | logic | instruction was predicted to be a taken branch |
| instr_fetch_err_o | out | logic | bus error on fetch |
| instr_fetch_err_plus2_o | out | logic | bus error misaligned |
| illegal_c_insn_id_o | out | logic | compressed decoder thinks this is an invalid instr |
| dummy_instr_id_o | out | logic | Instruction is a dummy |
| pc_if_o | out | [31:0] logic | |
| pc_id_o | out | [31:0] logic | |
| instr_valid_clear_i | in | logic | clear instr valid bit in IF-ID |
| pc_set_i | in | logic | set the PC to a new value |
| pc_set_spec_i | in | logic | |
| pc_mux_i | in | pc_sel_e | selector for PC multiplexer |
| nt_branch_mispredict_i | in | logic | Not-taken branch in ID/EX was mispredicted (predicted taken) |
| exc_pc_mux_i | in | exc_pc_sel_e | selects ISR address |
| exc_cause | in | exc_cause_e | selects ISR address for vectorized interrupt lines |
| dummy_instr_en_i | in | logic | |
| dummy_instr_mask_i | in | [2:0] logic | |
| dummy_instr_seed_en_i | in | logic | |
| dummy_instr_seed_i | in | [31:0] logic | |
| icache_enable_i | in | logic | |
| icache_inval_i | in | logic | |
| branch_target_ex_i | in | [31:0] logic | branch/jump target address |
| csr_mepc_i | in | [31:0] logic | PC to restore after handling the interrupt/exception |
| csr_depc_i | in | [31:0] logic | PC to restore after handling the debug request |
| csr_mtvec_i | in | [31:0] logic | base PC to jump to on exception |
| csr_mtvec_init_o | out | logic | tell CS regfile to init mtvec |
| id_in_ready_i | in | logic | ID stage is ready for new instr |
| pc_mismatch_alert_o | out | logic | misc signals |
| if_busy_o | out | logic | IF stage is busy fetching instr |
This design unit is implemented in ibex_load_store_unit.sv
This file depends on: uvm_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| data_req_o | out | logic | data interface |
| data_gnt_i | in | logic | |
| data_rvalid_i | in | logic | |
| data_err_i | in | logic | |
| data_pmp_err_i | in | logic | |
| data_addr_o | out | [31:0] logic | |
| data_we_o | out | logic | |
| data_be_o | out | [3:0] logic | |
| data_wdata_o | out | [31:0] logic | |
| data_rdata_i | in | [31:0] logic | |
| lsu_we_i | in | logic | write enable -> from ID/EX |
| lsu_type_i | in | [1:0] logic | data type: word, half word, byte -> from ID/EX |
| lsu_wdata_i | in | [31:0] logic | data to write to memory -> from ID/EX |
| lsu_sign_ext_i | in | logic | sign extension -> from ID/EX |
| lsu_rdata_o | out | [31:0] logic | requested data -> to ID/EX |
| lsu_rdata_valid_o | out | logic | |
| lsu_req_i | in | logic | data request -> from ID/EX |
| adder_result_ex_i | in | [31:0] logic | address computed in ALU -> from ID/EX |
| addr_incr_req_o | out | logic | request address increment for misaligned accesses -> to ID/EX |
| addr_last_o | out | [31:0] logic | address of last transaction -> to controller -> mtval -> AGU for misaligned accesses |
| lsu_req_done_o | out | logic | Signals that data request is complete (only need to await final data response) -> to ID/EX |
| lsu_resp_valid_o | out | logic | LSU has response from transaction -> to ID/EX |
| load_err_o | out | logic | exception signals |
| store_err_o | out | logic | |
| busy_o | out | logic | |
| perf_load_o | out | logic | |
| perf_store_o | out | logic |
This design unit is implemented in ibex_pmp.sv
This file depends on: ibex_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| PMPGranularity | int | 0 | Granularity of NAPOT access, 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc. |
| PMPNumChan | int | 2 | Number of access channels (e.g. i-side + d-side) |
| PMPNumRegions | int | 4 | Number of implemented regions |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock and Reset |
| rst_ni | in | logic | |
| csr_pmp_cfg_i | in | pmp_cfg_t [PMPNumRegions] | Interface to CSRs |
| csr_pmp_addr_i | in | [33:0] logic [PMPNumRegions] | |
| priv_mode_i | in | priv_lvl_e [PMPNumChan] | |
| pmp_req_addr_i | in | [33:0] logic [PMPNumChan] | Access checking channels |
| pmp_req_type_i | in | pmp_req_e [PMPNumChan] | |
| pmp_req_err_o | out | logic [PMPNumChan] |
This design unit is implemented in ibex_register_file_ff.sv
RISC-V register file
Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0.
This register file is based on flip flops. Use this register file when
targeting FPGA synthesis or Verilator simulation.
| Name | Type | Default Value | Description |
|---|---|---|---|
| RV32E | bit | 0 | |
| DataWidth | int | 32 | |
| DummyInstructions | bit | 0 | |
| ADDR_WIDTH | int | RV32E ? 4 : 5 | |
| NUM_WORDS | int | 2**ADDR_WIDTH |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock and Reset |
| rst_ni | in | logic | |
| test_en_i | in | logic | |
| dummy_instr_id_i | in | logic | |
| raddr_a_i | in | [4:0] logic | Read port R1 |
| rdata_a_o | out | [DataWidth-1:0] logic | |
| raddr_b_i | in | [4:0] logic | Read port R2 |
| rdata_b_o | out | [DataWidth-1:0] logic | |
| waddr_a_i | in | [4:0] logic | Write port W1 |
| wdata_a_i | in | [DataWidth-1:0] logic | |
| we_a_i | in | logic |
This design unit is implemented in ibex_register_file_fpga.sv
RISC-V register file
Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0.
This register file is designed to make FPGA synthesis tools infer RAM primitives. For Xilinx
FPGA architectures, it will produce RAM32M primitives. Other vendors have not yet been tested.
| Name | Type | Default Value | Description |
|---|---|---|---|
| RV32E | bit | 0 | |
| DataWidth | int | 32 | |
| DummyInstructions | bit | 0 | |
| ADDR_WIDTH | int | RV32E ? 4 : 5 | |
| NUM_WORDS | int | 2**ADDR_WIDTH |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock and Reset |
| rst_ni | in | logic | |
| test_en_i | in | logic | |
| dummy_instr_id_i | in | logic | |
| raddr_a_i | in | [4:0] logic | Read port R1 |
| rdata_a_o | out | [DataWidth-1:0] logic | |
| raddr_b_i | in | [4:0] logic | Read port R2 |
| rdata_b_o | out | [DataWidth-1:0] logic | |
| waddr_a_i | in | [4:0] logic | Write port W1 |
| wdata_a_i | in | [DataWidth-1:0] logic | |
| we_a_i | in | logic |
This design unit is implemented in ibex_register_file_latch.sv
This file depends on: prim_clock_gating.sv
RISC-V register file
Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0.
This register file is based on latches and is thus smaller than the flip-flop
based RF. It requires a target technology-specific clock gating cell. Use this
register file when targeting ASIC synthesis or event-based simulators.
| Name | Type | Default Value | Description |
|---|---|---|---|
| RV32E | bit | 0 | |
| DataWidth | int | 32 | |
| DummyInstructions | bit | 0 | |
| ADDR_WIDTH | int | RV32E ? 4 : 5 | |
| NUM_WORDS | int | 2**ADDR_WIDTH |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock and Reset |
| rst_ni | in | logic | |
| test_en_i | in | logic | |
| dummy_instr_id_i | in | logic | |
| raddr_a_i | in | [4:0] logic | Read port R1 |
| rdata_a_o | out | [DataWidth-1:0] logic | |
| raddr_b_i | in | [4:0] logic | Read port R2 |
| rdata_b_o | out | [DataWidth-1:0] logic | |
| waddr_a_i | in | [4:0] logic | Write port W1 |
| wdata_a_i | in | [DataWidth-1:0] logic | |
| we_a_i | in | logic |
WRITE //
Global clock gating
This design unit is implemented in ibex_tracer_pkg.sv
This file depends on: ibex_pkg.sv
This design unit is implemented in ibex_wb_stage.sv
This file depends on: uvm_pkg.sv, ibex_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| WritebackStage | bit | 1'b0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| en_wb_i | in | logic | |
| instr_type_wb_i | in | wb_instr_type_e | |
| pc_id_i | in | [31:0] logic | |
| ready_wb_o | out | logic | |
| rf_write_wb_o | out | logic | |
| outstanding_load_wb_o | out | logic | |
| outstanding_store_wb_o | out | logic | |
| pc_wb_o | out | [31:0] logic | |
| rf_waddr_id_i | in | [4:0] logic | |
| rf_wdata_id_i | in | [31:0] logic | |
| rf_we_id_i | in | logic | |
| rf_wdata_lsu_i | in | [31:0] logic | |
| rf_we_lsu_i | in | logic | |
| rf_wdata_fwd_wb_o | out | [31:0] logic | |
| rf_waddr_wb_o | out | [4:0] logic | |
| rf_wdata_wb_o | out | [31:0] logic | |
| rf_we_wb_o | out | logic | |
| lsu_resp_valid_i | in | logic | |
| instr_done_wb_o | out | logic |
This design unit is implemented in IOBUF.v
| Name | Type | Default Value | Description |
|---|---|---|---|
| CAPACITANCE | unknown | "DONT_CARE" | |
| DRIVE | integer | 12 | |
| IBUF_DELAY_VALUE | unknown | "0" | |
| IBUF_LOW_PWR | unknown | "TRUE" | |
| IFD_DELAY_VALUE | unknown | "AUTO" | |
| IOSTANDARD | unknown | "DEFAULT" | |
| SLEW | unknown | "SLOW" |
| Name | Direction | Type | Description |
|---|---|---|---|
| O | out | logic | |
| IO | inout | logic | |
| I | in | logic | |
| T | in | logic |
This design unit is implemented in keccak_round.sv
This file depends on: keccak_2share.sv, uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 1600 | b= {25, 50, 100, 200, 400, 800, 1600} |
| W | int | Width/25 | Derived |
| L | int | $clog2(W) | |
| MaxRound | int | 12 + 2*L | Keccak-f only |
| RndW | int | $clog2(MaxRound+1) | Representing up to MaxRound-1 |
| DInWidth | int | 64 | currently only 64bit supported |
| DInEntry | int | Width / DInWidth | |
| DInAddr | int | $clog2(DInEntry) | |
| EnMasking | bit | 0 | Enable secure hardening |
| Share | int | EnMasking ? 2 : 1 | |
| ReuseShare | int | 0 | Re-use adjacent share for entropy |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| valid_i | in | logic | Message Feed |
| addr_i | in | [DInAddr-1:0] logic | |
| data_i | in | [DInWidth-1:0] logic [Share] | |
| ready_o | out | logic | |
| run_i | in | logic | Pulse signal to initiates Keccak full round |
| rand_valid_i | in | logic | |
| rand_data_i | in | [Width-1:0] logic | |
| rand_consumed_o | out | logic | |
| complete_o | out | logic | Indicates full round is done |
| state_o | out | [Width-1:0] logic [Share] | State out. This can be used as Digest |
| clear_i | in | logic | Clear internal state to '0 |
Datapath //
This design unit is implemented in keymgr_sideload_key.sv
This file depends on: keymgr_pkg.sv
keymgr_sideload_key
| Name | Type | Default Value | Description |
|---|---|---|---|
| EntropyCopies | int | KeyWidth / 32 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| en_i | in | logic | |
| set_en_i | in | logic | |
| set_i | in | logic | |
| clr_i | in | logic | |
| entropy_i | in | [RandWidth-1:0] [Shares-1:0] logic | |
| key_i | in | [KeyWidth-1:0] [Shares-1:0] logic | |
| key_o | out | hw_key_req_t |
This design unit is implemented in lc_ctrl_signal_decode.sv
This file depends on: prim_lc_sender.sv, uvm_pkg.sv, lc_ctrl_state_pkg.sv, lc_ctrl_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| RndCnstLcKeymgrDivInvalid | lc_keymgr_div_t | LcKeymgrDivWidth'(0) | Random netlist constants SCRAP, RAW, TEST_LOCKED*, INVALID |
| RndCnstLcKeymgrDivTestDevRma | lc_keymgr_div_t | LcKeymgrDivWidth'(1) | TEST_UNLOCKED*, DEV, RMA |
| RndCnstLcKeymgrDivProduction | lc_keymgr_div_t | LcKeymgrDivWidth'(2) | PROD, PROD_END |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| lc_state_valid_i | in | logic | Life cycle state vector. |
| lc_state_i | in | lc_state_e | |
| lc_id_state_i | in | lc_id_state_e | |
| fsm_state_i | in | fsm_state_e | |
| esc_wipe_secrets_i | in | logic | Escalation enable from escalation receiver. |
| lc_dft_en_o | out | lc_tx_t | Life cycle broadcast outputs. |
| lc_nvm_debug_en_o | out | lc_tx_t | |
| lc_hw_debug_en_o | out | lc_tx_t | |
| lc_cpu_en_o | out | lc_tx_t | |
| lc_creator_seed_sw_rw_en_o | out | lc_tx_t | |
| lc_owner_seed_sw_rw_en_o | out | lc_tx_t | |
| lc_iso_part_sw_rd_en_o | out | lc_tx_t | |
| lc_iso_part_sw_wr_en_o | out | lc_tx_t | |
| lc_seed_hw_rd_en_o | out | lc_tx_t | |
| lc_keymgr_en_o | out | lc_tx_t | |
| lc_escalate_en_o | out | lc_tx_t | |
| lc_keymgr_div_o | out | lc_keymgr_div_t | State group diversification value for keymgr |
This design unit is implemented in lc_ctrl_state_decode.sv
This file depends on: lc_ctrl_state_pkg.sv, lc_ctrl_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| lc_state_valid_i | in | logic | Life cycle state vector. |
| lc_state_i | in | lc_state_e | |
| lc_id_state_i | in | lc_id_state_e | |
| lc_cnt_i | in | lc_cnt_e | |
| fsm_state_i | in | fsm_state_e | Main FSM state. |
| dec_lc_state_o | out | dec_lc_state_e | Decoded state vector. |
| dec_lc_id_state_o | out | dec_lc_id_state_e | |
| dec_lc_cnt_o | out | dec_lc_cnt_t | |
| state_invalid_error_o | out | logic |
This design unit is implemented in lc_ctrl_state_transition.sv
This file depends on: lc_ctrl_state_pkg.sv, lc_ctrl_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| lc_state_i | in | lc_state_e | Life cycle state vector. |
| lc_cnt_i | in | lc_cnt_e | |
| fsm_state_i | in | fsm_state_e | Main FSM state. |
| dec_lc_state_i | in | dec_lc_state_e | Decoded lc state input |
| trans_target_i | in | dec_lc_state_e | Transition target. |
| next_lc_state_o | out | lc_state_e | Updated state vector. |
| next_lc_cnt_o | out | lc_cnt_e | |
| trans_cnt_oflw_error_o | out | logic | If the transition counter is maxed out |
| trans_invalid_error_o | out | logic |
This design unit is implemented in otbn_alu_base.sv
This file depends on: otbn_pkg.sv
OTBN execute block for the base instruction subset
This ALU supports the execution of all of OTBN's base instruction subset.
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Block is combinatorial; clk/rst are for assertions only. |
| rst_ni | in | logic | |
| operation_i | in | alu_base_operation_t | |
| comparison_i | in | alu_base_comparison_t | |
| operation_result_o | out | [31:0] logic | |
| comparison_result_o | out | logic |
This design unit is implemented in otbn_alu_bignum.sv
This file depends on: uvm_pkg.sv, otbn_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| operation_i | in | alu_bignum_operation_t | |
| operation_result_o | out | [WLEN-1:0] logic | |
| ispr_addr_i | in | ispr_e | |
| ispr_base_wdata_i | in | [31:0] logic | |
| ispr_base_wr_en_i | in | [BaseWordsPerWLEN-1:0] logic | |
| ispr_bignum_wdata_i | in | [WLEN-1:0] logic | |
| ispr_bignum_wr_en_i | in | logic | |
| ispr_rdata_o | out | [WLEN-1:0] logic | |
| ispr_acc_i | in | [WLEN-1:0] logic | |
| ispr_acc_wr_data_o | out | [WLEN-1:0] logic | |
| ispr_acc_wr_en_o | out | logic | |
| mac_operation_flags_i | in | flags_t | |
| mac_operation_flags_en_i | in | flags_t | |
| rnd_i | in | [WLEN-1:0] logic |
This design unit is implemented in otbn_controller.sv
This file depends on: uvm_pkg.sv, otbn_loop_controller.sv, prim_util_pkg.sv, otbn_pkg.sv
OTBN Controller
| Name | Type | Default Value | Description |
|---|---|---|---|
| ImemSizeByte | int | 4096 | Size of the instruction memory, in bytes |
| DmemSizeByte | int | 4096 | Size of the data memory, in bytes |
| ImemAddrWidth | int | prim_util_pkg::vbits(ImemSizeByte) | |
| DmemAddrWidth | int | prim_util_pkg::vbits(DmemSizeByte) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| start_i | in | logic | start the processing at start_addr_i |
| done_o | out | logic | processing done, signaled by ECALL or error occurring |
| err_bits_o | out | err_bits_t | valid when done_o is asserted |
| start_addr_i | in | [ImemAddrWidth-1:0] logic | |
| insn_fetch_req_valid_o | out | logic | Next instruction selection (to instruction fetch) |
| insn_fetch_req_addr_o | out | [ImemAddrWidth-1:0] logic | |
| insn_fetch_err_i | in | logic | Error from fetch requested last cycle |
| insn_valid_i | in | logic | Fetched/decoded instruction |
| insn_illegal_i | in | logic | |
| insn_addr_i | in | [ImemAddrWidth-1:0] logic | |
| insn_dec_base_i | in | insn_dec_base_t | Decoded instruction data, matching the "Decoding" section of the specification. |
| insn_dec_bignum_i | in | insn_dec_bignum_t | |
| insn_dec_shared_i | in | insn_dec_shared_t | |
| rf_base_wr_addr_o | out | [4:0] logic | Base register file |
| rf_base_wr_en_o | out | logic | |
| rf_base_wr_commit_o | out | logic | |
| rf_base_wr_data_o | out | [31:0] logic | |
| rf_base_rd_addr_a_o | out | [4:0] logic | |
| rf_base_rd_en_a_o | out | logic | |
| rf_base_rd_data_a_i | in | [31:0] logic | |
| rf_base_rd_addr_b_o | out | [4:0] logic | |
| rf_base_rd_en_b_o | out | logic | |
| rf_base_rd_data_b_i | in | [31:0] logic | |
| rf_base_rd_commit_o | out | logic | |
| rf_base_call_stack_err_i | in | logic | |
| rf_bignum_wr_addr_o | out | [4:0] logic | Bignum register file (WDRs) |
| rf_bignum_wr_en_o | out | [1:0] logic | |
| rf_bignum_wr_data_o | out | [WLEN-1:0] logic | |
| rf_bignum_rd_addr_a_o | out | [4:0] logic | |
| rf_bignum_rd_data_a_i | in | [WLEN-1:0] logic | |
| rf_bignum_rd_addr_b_o | out | [4:0] logic | |
| rf_bignum_rd_data_b_i | in | [WLEN-1:0] logic | |
| alu_base_operation_o | out | alu_base_operation_t | Base ALU |
| alu_base_comparison_o | out | alu_base_comparison_t | |
| alu_base_operation_result_i | in | [31:0] logic | |
| alu_base_comparison_result_i | in | logic | |
| alu_bignum_operation_o | out | alu_bignum_operation_t | Bignum ALU |
| alu_bignum_operation_result_i | in | [WLEN-1:0] logic | |
| mac_bignum_operation_o | out | mac_bignum_operation_t | Bignum MAC |
| mac_bignum_operation_result_i | in | [WLEN-1:0] logic | |
| mac_bignum_en_o | out | logic | |
| lsu_load_req_o | out | logic | LSU |
| lsu_store_req_o | out | logic | |
| lsu_req_subset_o | out | insn_subset_e | |
| lsu_addr_o | out | [DmemAddrWidth-1:0] logic | |
| lsu_base_wdata_o | out | [31:0] logic | |
| lsu_bignum_wdata_o | out | [WLEN-1:0] logic | |
| lsu_base_rdata_i | in | [31:0] logic | |
| lsu_bignum_rdata_i | in | [WLEN-1:0] logic | |
| lsu_rdata_err_i | in | logic | |
| ispr_addr_o | out | ispr_e | Internal Special-Purpose Registers (ISPRs) |
| ispr_base_wdata_o | out | [31:0] logic | |
| ispr_base_wr_en_o | out | [BaseWordsPerWLEN-1:0] logic | |
| ispr_bignum_wdata_o | out | [WLEN-1:0] logic | |
| ispr_bignum_wr_en_o | out | logic | |
| ispr_rdata_i | in | [WLEN-1:0] logic |
This design unit is implemented in otbn_decoder.sv
This file depends on: uvm_pkg.sv, otbn_pkg.sv
OTBN instruction Decoder
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | For assertions only. |
| rst_ni | in | logic | |
| insn_fetch_resp_data_i | in | [31:0] logic | instruction data to be decoded |
| insn_fetch_resp_valid_i | in | logic | |
| insn_valid_o | out | logic | Decoded instruction |
| insn_illegal_o | out | logic | |
| insn_dec_base_o | out | insn_dec_base_t | |
| insn_dec_bignum_o | out | insn_dec_bignum_t | |
| insn_dec_shared_o | out | insn_dec_shared_t |
This design unit is implemented in otbn_instruction_fetch.sv
This file depends on: prim_util_pkg.sv, otbn_pkg.sv
OTBN Instruction Fetch Unit
Fetch an instruction from the instruction memory.
| Name | Type | Default Value | Description |
|---|---|---|---|
| ImemSizeByte | int | 4096 | |
| ImemAddrWidth | int | prim_util_pkg::vbits(ImemSizeByte) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| imem_req_o | out | logic | Instruction memory (IMEM) interface. Read-only. |
| imem_addr_o | out | [ImemAddrWidth-1:0] logic | |
| imem_rdata_i | in | [31:0] logic | |
| imem_rvalid_i | in | logic | |
| imem_rerror_i | in | logic | |
| insn_fetch_req_valid_i | in | logic | Next instruction selection (to instruction fetch) |
| insn_fetch_req_addr_i | in | [ImemAddrWidth-1:0] logic | |
| insn_fetch_resp_valid_o | out | logic | Decoded instruction |
| insn_fetch_resp_addr_o | out | [ImemAddrWidth-1:0] logic | |
| insn_fetch_resp_data_o | out | [31:0] logic | |
| insn_fetch_err_o | out | logic | ECC error seen in instruction fetch |
This design unit is implemented in otbn_lsu.sv
This file depends on: uvm_pkg.sv, prim_util_pkg.sv, otbn_pkg.sv
OTBN Load-Store Unit
Read and write data from/to the data memory (DMEM). Used by the base and the BN instruction
subset; loads and stores are hence either 32b or WLEN bit wide.
The data memory interface makes the following assumptions:
All requests are answered in the next cycle; the LSU must have exclusive access to the memory.
The write mask supports aligned 32b write accesses.
| Name | Type | Default Value | Description |
|---|---|---|---|
| DmemSizeByte | int | 4096 | |
| DmemAddrWidth | int | prim_util_pkg::vbits(DmemSizeByte) | |
| BaseWordsPerWLen | int | WLEN / 32 | |
| BaseWordAddrW | int | prim_util_pkg::vbits(WLEN/8) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| dmem_req_o | out | logic | Data memory (DMEM) interface |
| dmem_write_o | out | logic | |
| dmem_addr_o | out | [DmemAddrWidth-1:0] logic | |
| dmem_wdata_o | out | [WLEN-1:0] logic | |
| dmem_wmask_o | out | [WLEN-1:0] logic | |
| dmem_rdata_i | in | [WLEN-1:0] logic | |
| dmem_rvalid_i | in | logic | |
| dmem_rerror_i | in | logic | |
| lsu_load_req_i | in | logic | |
| lsu_store_req_i | in | logic | |
| lsu_req_subset_i | in | insn_subset_e | |
| lsu_addr_i | in | [DmemAddrWidth-1:0] logic | |
| lsu_base_wdata_i | in | [31:0] logic | |
| lsu_bignum_wdata_i | in | [WLEN-1:0] logic | |
| lsu_base_rdata_o | out | [31:0] logic | |
| lsu_bignum_rdata_o | out | [WLEN-1:0] logic | |
| lsu_rdata_err_o | out | logic |
This design unit is implemented in otbn_mac_bignum.sv
This file depends on: uvm_pkg.sv, otbn_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| QWLEN | int | WLEN / 4 | The MAC operates on quarter-words, QWLEN gives the number of bits in a quarter-word. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| operation_i | in | mac_bignum_operation_t | |
| mac_en_i | in | logic | |
| operation_result_o | out | [WLEN-1:0] logic | |
| operation_flags_o | out | flags_t | |
| operation_flags_en_o | out | flags_t | |
| ispr_acc_o | out | [WLEN-1:0] logic | |
| ispr_acc_wr_data_i | in | [WLEN-1:0] logic | |
| ispr_acc_wr_en_i | in | logic |
This design unit is implemented in otbn_rf_base.sv
This file depends on: otbn_rf_base_fpga.sv, otbn_rf_base_ff.sv, otbn_stack.sv, otbn_pkg.sv
32b General Purpose Register File (GPRs)
This wraps two implementations, one for FPGA (otbn_rf_base_fpga)
implementation the other for ASIC (otbn_rf_base_ff).
Both reads and writes use a 2 signal protocol: An _en signal indicates intent to do
a read or write operation, a _commit signals the operation should proceed. A _commit without _en
is permissible and means no operation is performed.
This is used to prevent combinational loops in the error handling logic in the controller.
Features:
2 read ports
1 write port
special purpose stack on a single register (localparam CallStackRegIndex)
for use as a call stack
| Name | Type | Default Value | Description |
|---|---|---|---|
| RegFile | regfile_e | RegFileFF | Register file implementation selection, see otbn_pkg.sv. |
| CallStackRegIndex | int | 1 | |
| CallStackDepth | int | 8 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wr_addr_i | in | [4:0] logic | |
| wr_en_i | in | logic | |
| wr_data_i | in | [31:0] logic | |
| wr_commit_i | in | logic | |
| rd_addr_a_i | in | [4:0] logic | |
| rd_en_a_i | in | logic | |
| rd_data_a_o | out | [31:0] logic | |
| rd_addr_b_i | in | [4:0] logic | |
| rd_en_b_i | in | logic | |
| rd_data_b_o | out | [31:0] logic | |
| rd_commit_i | in | logic | |
| call_stack_err_o | out | logic |
This design unit is implemented in otbn_rf_bignum_ff.sv
This file depends on: otbn_pkg.sv
WLEN (256b) Wide Register File (WDRs)
Features:
2 read ports
1 write port
Half (WLEN) word write enables
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wr_addr_i | in | [WdrAw-1:0] logic | |
| wr_en_i | in | [1:0] logic | |
| wr_data_i | in | [WLEN-1:0] logic | |
| rd_addr_a_i | in | [WdrAw-1:0] logic | |
| rd_data_a_o | out | [WLEN-1:0] logic | |
| rd_addr_b_i | in | [WdrAw-1:0] logic | |
| rd_data_b_o | out | [WLEN-1:0] logic |
This design unit is implemented in otbn_rf_bignum_fpga.sv
This file depends on: otbn_pkg.sv
WLEN (256b) Wide Register File (WDRs)
Features:
2 read ports
1 write port
Half (WLEN) word write enables
This register file is designed to make FPGA synthesis tools infer RAM primitives. For Xilinx
FPGA architectures, it will produce RAM32M primitives. Other vendors have not yet been tested.
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wr_addr_i | in | [WdrAw-1:0] logic | |
| wr_en_i | in | [1:0] logic | |
| wr_data_i | in | [WLEN-1:0] logic | |
| rd_addr_a_i | in | [WdrAw-1:0] logic | |
| rd_data_a_o | out | [WLEN-1:0] logic | |
| rd_addr_b_i | in | [WdrAw-1:0] logic | |
| rd_data_b_o | out | [WLEN-1:0] logic |
This design unit is implemented in otp_ctrl_ecc_reg.sv
This file depends on: prim_secded_72_64_dec.sv, uvm_pkg.sv, prim_secded_72_64_enc.sv, prim_util_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 64 | bit |
| Depth | int | 128 | |
| Aw | int | prim_util_pkg::vbits(Depth) | derived parameter |
| EccWidth | int | 8 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wren_i | in | logic | |
| addr_i | in | [Aw-1:0] logic | |
| wdata_i | in | [Width-1:0] logic | |
| data_o | out | [Width-1:0] [Depth-1:0] logic | Concurrent output of the register state. |
| ecc_err_o | out | logic | Concurrent ECC check error is flagged via this signal. |
Only one encoder is needed.
This design unit is implemented in pattgen_chan.sv
This file depends on: pattgen_ctrl_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| ctrl_i | in | pattgen_chan_ctrl_t | |
| pda_o | out | logic | |
| pcl_o | out | logic | |
| event_done_o | out | logic |
This design unit is implemented in pattgen_ctrl_pkg.sv
This design unit is implemented in pinmux_jtag_buf.sv
This file depends on: jtag_pkg.sv, prim_buf.sv, prim_clock_buf.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| req_i | in | jtag_req_t | |
| req_o | out | jtag_req_t | |
| rsp_i | in | jtag_rsp_t | |
| rsp_o | out | jtag_rsp_t |
This design unit is implemented in prim_arbiter_ppc.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| N | int | 8 | |
| DW | int | 32 | |
| EnDataPort | bit | 1 | Configurations EnDataPort: {0, 1}, if 0, input data will be ignored |
| EnReqStabA | bit | 1 | Non-functional parameter to switch on the request stability assertion |
| IdxW | int | $clog2(N) | Derived parameters |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | [N-1:0] logic | |
| data_i | in | [DW-1:0] logic [N] | |
| gnt_o | out | [N-1:0] logic | |
| idx_o | out | [IdxW-1:0] logic | |
| valid_o | out | logic | |
| data_o | out | [DW-1:0] logic | |
| ready_i | in | logic |
This design unit is implemented in prim_buf.sv
This file depends on: prim_xilinx_buf.sv, prim_generic_buf.sv, prim_pkg.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| Impl | impl_e | prim_pkg::ImplGeneric |
| Name | Direction | Type | Description |
|---|---|---|---|
| in_i | in | logic | |
| out_o | out | logic |
This design unit is implemented in prim_cipher_pkg.sv
This design unit is implemented in prim_diff_decode.sv
This file depends on: prim_flop_2sync.sv, uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AsyncOn | bit | 1'b0 | enables additional synchronization logic |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| diff_pi | in | logic | input diff pair |
| diff_ni | in | logic | |
| level_o | out | logic | logical level and detected edges |
| rise_o | out | logic | |
| fall_o | out | logic | |
| event_o | out | logic | either rise or fall |
| sigint_o | out | logic | signal integrity issue detected |
This design unit is implemented in prim_filter.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Cycles | int | 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| enable_i | in | logic | |
| filter_i | in | logic | |
| filter_o | out | logic |
This design unit is implemented in prim_generic_clock_buf.sv
prim_generic_clock_buf
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| clk_o | out | logic |
This design unit is implemented in prim_generic_clock_gating.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NoFpgaGate | bit | 1'b0 | this parameter has no function in generic |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| en_i | in | logic | |
| test_en_i | in | logic | |
| clk_o | out | logic |
This design unit is implemented in prim_generic_clock_inv.sv
This file depends on: prim_clock_mux2.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| HasScanMode | bit | 1'b1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| scanmode_i | in | logic | |
| clk_no | out | logic | Inverted |
This design unit is implemented in prim_generic_clock_mux2.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NoFpgaBufG | bit | 1'b0 | this parameter serves no function in the generic model |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk0_i | in | logic | |
| clk1_i | in | logic | |
| sel_i | in | logic | |
| clk_o | out | logic |
This design unit is implemented in prim_generic_flash.sv
This file depends on: tlul_adapter_sram.sv, flash_phy_pkg.sv, flash_ctrl_pkg.sv, tlul_pkg.sv, lc_ctrl_pkg.sv, prim_generic_flash_bank.sv, prim_ram_1p.sv
prim_generic_flash
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumBanks | int | 2 | number of banks |
| InfosPerBank | int | 1 | info pages per bank |
| InfoTypes | int | 1 | different info types |
| InfoTypesWidth | int | 1 | different info types |
| PagesPerBank | int | 256 | data pages per bank |
| WordsPerPage | int | 256 | words per page |
| DataWidth | int | 32 | bits per word |
| MetaDataWidth | int | 12 | metadata such as ECC |
| TestModeWidth | int | 4 | |
| CfgRegs | int | 21 | |
| CfgAddrWidth | int | $clog2(CfgRegs) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| flash_req_i | in | [NumBanks-1:0] flash_phy_prim_flash_req_t | |
| flash_rsp_o | out | [NumBanks-1:0] flash_phy_prim_flash_rsp_t | |
| prog_type_avail_o | out | [flash_phy_pkg::ProgTypes-1:0] logic | |
| init_busy_o | out | logic | |
| tck_i | in | logic | |
| tdi_i | in | logic | |
| tms_i | in | logic | |
| tdo_o | out | logic | |
| bist_enable_i | in | lc_tx_t | |
| scanmode_i | in | lc_tx_t | |
| scan_en_i | in | logic | |
| scan_rst_ni | in | logic | |
| flash_power_ready_h_i | in | logic | |
| flash_power_down_h_i | in | logic | |
| flash_test_mode_a_i | in | [TestModeWidth-1:0] logic | |
| flash_test_voltage_h_i | in | logic | |
| flash_err_o | out | logic | |
| flash_alert_po | out | logic | |
| flash_alert_no | out | logic | |
| flash_alert_ack_i | in | logic | |
| flash_alert_trig_i | in | logic | |
| tl_i | in | tl_h2d_t | |
| tl_o | out | tl_d2h_t | |
| devmode_i | in | logic |
This design unit is implemented in prim_generic_flop.sv
prim_generic_flop
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 1 | |
| WidthSubOne | int | Width-1 | |
| ResetValue | [WidthSubOne:0] logic | 0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| d_i | in | [Width-1:0] logic | |
| q_o | out | [Width-1:0] logic |
This design unit is implemented in prim_generic_otp.sv
This file depends on: tlul_adapter_sram.sv, prim_flop.sv, uvm_pkg.sv, prim_ram_1p_adv.sv, prim_util_pkg.sv, prim_otp_pkg.sv, tlul_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 16 | Native OTP word size. This determines the size_i granule. |
| Depth | int | 1024 | |
| SizeWidth | int | 2 | This determines the maximum number of native words that can be transferred accross the interface in one cycle. |
| PwrSeqWidth | int | 2 | Width of the power sequencing signal. |
| TlDepth | int | 16 | Number of Test TL-UL words |
| AddrWidth | int | prim_util_pkg::vbits(Depth) | Derived parameters |
| IfWidth | int | 2**SizeWidth*Width | |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| TlAddrWidth | int | prim_util_pkg::vbits(TlDepth) | Put down a register that can be used to test the TL interface. TODO: this emulation may need to be adjusted, once closed source wrapper is implemented. |
| StateWidth | int | 10 | Encoding generated with ./sparse-fsm-encode.py -d 5 -m 8 -n 10 Hamming distance histogram: 0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (53.57%) 6: ||||||||||||| (35.71%) 7: | (3.57%) 8: || (7.14%) 9: -- 10: -- Minimum Hamming distance: 5 Maximum Hamming distance: 8 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| pwr_seq_o | out | [PwrSeqWidth-1:0] logic | Macro-specific power sequencing signals to/from AST |
| pwr_seq_h_i | in | [PwrSeqWidth-1:0] logic | |
| test_tl_i | in | tl_h2d_t | Test interface |
| test_tl_o | out | tl_d2h_t | |
| ready_o | out | logic | Ready valid handshake for read/write command |
| valid_i | in | logic | |
| size_i | in | [SizeWidth-1:0] logic | #(Native words)-1, e.g. size == 0 for 1 native word. |
| cmd_i | in | cmd_e | 00: read command, 01: write command, 11: init command |
| addr_i | in | [AddrWidth-1:0] logic | |
| wdata_i | in | [IfWidth-1:0] logic | |
| valid_o | out | logic | Response channel |
| rdata_o | out | [IfWidth-1:0] logic | |
| err_o | out | err_e |
This design unit is implemented in prim_generic_rom.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 32 | |
| Depth | int | 2048 | 8kB default |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| Aw | int | $clog2(Depth) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| req_i | in | logic | |
| addr_i | in | [Aw-1:0] logic | |
| rdata_o | out | [Width-1:0] logic |
This design unit is implemented in prim_present.sv
This file depends on: uvm_pkg.sv, prim_cipher_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| DataWidth | int | 64 | {32, 64} |
| KeyWidth | int | 128 | {64, 80, 128} |
| NumRounds | int | 31 | Number of rounds to perform in total (>0) |
| NumPhysRounds | int | NumRounds | Number of physically instantiated PRESENT rounds. This can be used to construct e.g. an iterative full-round implementation that only has one physical round instance by setting NumRounds = 31 and NumPhysRounds = 1. Note that NumPhysRounds needs to divide NumRounds. |
| Decrypt | bit | 0 | 0: encrypt, 1: decrypt |
| LastRoundIdx | int | (Decrypt != 0 || NumRounds == 31) ? 0 : NumRounds+1 | This only needs to be applied after the last round. Note that for a full-round implementation the output index will be 0 for enc/dec for the last round (either due to wraparound or subtraction). |
| Name | Direction | Type | Description |
|---|---|---|---|
| data_i | in | [DataWidth-1:0] logic | |
| key_i | in | [KeyWidth-1:0] logic | |
| idx_i | in | [4:0] logic | Starting round index for keyschedule 1 ... 31. Set this to 5'd1 for a fully unrolled encryption, and 5'd31 for a fully unrolled decryption. |
| data_o | out | [DataWidth-1:0] logic | |
| key_o | out | [KeyWidth-1:0] logic | |
| idx_o | out | [4:0] logic | Next round index for keyschedule (Enc: idx_i + NumPhysRounds, Dec: idx_i - NumPhysRounds) Can be ignored for a fully unrolled implementation. |
This design unit is implemented in prim_ram_1p.sv
This file depends on: prim_generic_ram_1p.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 32 | bit |
| Depth | int | 128 | |
| DataBitsPerMask | int | 1 | Number of data bits per bit of write mask |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| Aw | int | $clog2(Depth) | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| req_i | in | logic | |
| write_i | in | logic | |
| addr_i | in | [Aw-1:0] logic | |
| wdata_i | in | [Width-1:0] logic | |
| wmask_i | in | [Width-1:0] logic | |
| rdata_o | out | [Width-1:0] logic | Read data. Data is returned one cycle after req_i is high. |
This design unit is implemented in prim_ram_2p.sv
This file depends on: prim_generic_ram_2p.sv
This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 32 | bit |
| Depth | int | 128 | |
| DataBitsPerMask | int | 1 | Number of data bits per bit of write mask |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| Aw | int | $clog2(Depth) | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_a_i | in | logic | |
| clk_b_i | in | logic | |
| a_req_i | in | logic | |
| a_write_i | in | logic | |
| a_addr_i | in | [Aw-1:0] logic | |
| a_wdata_i | in | [Width-1:0] logic | |
| a_wmask_i | in | [Width-1:0] logic | |
| a_rdata_o | out | [Width-1:0] logic | |
| b_req_i | in | logic | |
| b_write_i | in | logic | |
| b_addr_i | in | [Aw-1:0] logic | |
| b_wdata_i | in | [Width-1:0] logic | |
| b_wmask_i | in | [Width-1:0] logic | |
| b_rdata_o | out | [Width-1:0] logic |
This design unit is implemented in prim_secded_22_16_dec.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [21:0] logic | |
| d_o | out | [15:0] logic | |
| syndrome_o | out | [5:0] logic | |
| err_o | out | [1:0] logic |
This design unit is implemented in prim_secded_22_16_enc.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [15:0] logic | |
| out | out | [21:0] logic |
This design unit is implemented in prim_secded_39_32_dec.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [38:0] logic | |
| d_o | out | [31:0] logic | |
| syndrome_o | out | [6:0] logic | |
| err_o | out | [1:0] logic |
This design unit is implemented in prim_secded_39_32_enc.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [31:0] logic | |
| out | out | [38:0] logic |
This design unit is implemented in prim_secded_64_57_enc.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [56:0] logic | |
| out | out | [63:0] logic |
This design unit is implemented in prim_secded_hamming_22_16_dec.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [21:0] logic | |
| d_o | out | [15:0] logic | |
| syndrome_o | out | [5:0] logic | |
| err_o | out | [1:0] logic |
This design unit is implemented in prim_secded_hamming_22_16_enc.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [15:0] logic | |
| out | out | [21:0] logic |
This design unit is implemented in prim_secded_hamming_39_32_dec.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [38:0] logic | |
| d_o | out | [31:0] logic | |
| syndrome_o | out | [6:0] logic | |
| err_o | out | [1:0] logic |
This design unit is implemented in prim_secded_hamming_39_32_enc.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [31:0] logic | |
| out | out | [38:0] logic |
This design unit is implemented in prim_slicer.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| InW | int | 64 | |
| OutW | int | 8 | |
| IndexW | int | 4 | |
| UnrollW | int | OutW*(2**IndexW) |
| Name | Direction | Type | Description |
|---|---|---|---|
| sel_i | in | [IndexW-1:0] logic | |
| data_i | in | [InW-1:0] logic | |
| data_o | out | [OutW-1:0] logic |
This design unit is implemented in prim_subreg_arb.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| DW | int | 32 | |
| SWACCESS | unknown | "RW" | {RW, RO, WO, W1C, W1S, W0C, RC} |
| Name | Direction | Type | Description |
|---|---|---|---|
| we | in | logic | From SW: valid for RW, WO, W1C, W1S, W0C, RC. In case of RC, top connects read pulse to we. |
| wd | in | [DW-1:0] logic | |
| de | in | logic | From HW: valid for HRW, HWO. |
| d | in | [DW-1:0] logic | |
| q | in | [DW-1:0] logic | From register: actual reg value. |
| wr_en | out | logic | To register: actual write enable and write data. |
| wr_data | out | [DW-1:0] logic |
This design unit is implemented in prim_subreg_ext.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| DW | int | 32 |
| Name | Direction | Type | Description |
|---|---|---|---|
| re | in | logic | |
| we | in | logic | |
| wd | in | [DW-1:0] logic | |
| d | in | [DW-1:0] logic | |
| qe | out | logic | output to HW and Reg Read |
| qre | out | logic | |
| q | out | [DW-1:0] logic | |
| qs | out | [DW-1:0] logic |
This design unit is implemented in prim_subreg_shadow.sv
This file depends on: prim_subreg_arb.sv, prim_subreg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| DW | int | 32 | |
| SWACCESS | unknown | "RW" | {RW, RO, WO, W1C, W1S, W0C, RC} |
| RESVAL | [DW-1:0] logic | '0 | reset value |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| re | in | logic | From SW: valid for RW, WO, W1C, W1S, W0C, RC. SW reads clear phase unless SWACCESS is RO. |
| we | in | logic | In case of RC, top connects read pulse to we. |
| wd | in | [DW-1:0] logic | |
| de | in | logic | From HW: valid for HRW, HWO. |
| d | in | [DW-1:0] logic | |
| qe | out | logic | Output to HW and Reg Read |
| q | out | [DW-1:0] logic | |
| qs | out | [DW-1:0] logic | |
| err_update | out | logic | Error conditions |
| err_storage | out | logic |
This design unit is implemented in prim_sync_reqack.sv
This file depends on: prim_flop_2sync.sv, uvm_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_src_i | in | logic | REQ side, SRC domain |
| rst_src_ni | in | logic | REQ side, SRC domain |
| clk_dst_i | in | logic | ACK side, DST domain |
| rst_dst_ni | in | logic | ACK side, DST domain |
| src_req_i | in | logic | REQ side, SRC domain |
| src_ack_o | out | logic | REQ side, SRC domain |
| dst_req_o | out | logic | ACK side, DST domain |
| dst_ack_i | in | logic | ACK side, DST domain |
Move REQ over to DST domain.
Move ACK over to SRC domain.
This design unit is implemented in prim_xilinx_clock_buf.sv
This file depends on: BUFG.v
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| clk_o | out | logic |
This design unit is implemented in prim_xilinx_clock_gating.sv
This file depends on: BUFGCE.v
| Name | Type | Default Value | Description |
|---|---|---|---|
| NoFpgaGate | bit | 1'b0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| en_i | in | logic | |
| test_en_i | in | logic | |
| clk_o | out | logic |
This design unit is implemented in prim_xilinx_clock_mux2.sv
This file depends on: uvm_pkg.sv, BUFGMUX.v
| Name | Type | Default Value | Description |
|---|---|---|---|
| NoFpgaBufG | bit | 1'b0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk0_i | in | logic | |
| clk1_i | in | logic | |
| sel_i | in | logic | |
| clk_o | out | logic |
This design unit is implemented in prim_xilinx_flop.sv
prim_xilinx_flop
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 1 | |
| WidthSubOne | int | Width-1 | |
| ResetValue | [WidthSubOne:0] logic | 0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| d_i | in | [Width-1:0] logic | |
| q_o | out | [Width-1:0] logic | Prevent Vivado from optimizing this signal away. |
This design unit is implemented in sha2_pad.sv
This file depends on: hmac_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wipe_secret | in | logic | |
| wipe_v | in | sha_word_t | |
| fifo_rvalid | in | logic | To actual FIFO |
| fifo_rdata | in | sha_fifo_t | |
| fifo_rready | out | logic | |
| shaf_rvalid | out | logic | from SHA2 compress engine |
| shaf_rdata | out | sha_word_t | |
| shaf_rready | in | logic | |
| sha_en | in | logic | |
| hash_start | in | logic | |
| hash_process | in | logic | |
| hash_done | in | logic | |
| message_length | in | [63:0] logic | of bytes in bits (8 bits granularity) |
| msg_feed_complete | out | logic | Indicates, all message is feeded |
This design unit is implemented in sha3pad.sv
This file depends on: prim_slicer.sv, uvm_pkg.sv, sha3_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| EnMasking | bit | 0 | |
| Share | int | (EnMasking) ? 2 : 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| msg_valid_i | in | logic | Message interface (FIFO) |
| msg_data_i | in | [MsgWidth-1:0] logic [Share] | |
| msg_strb_i | in | [MsgStrbW-1:0] logic | one strobe for shares |
| msg_ready_o | out | logic | |
| ns_data_i | in | [NSRegisterSize*8-1:0] logic | See sha3_pkg for details |
| keccak_valid_o | out | logic | output to keccak_round: message path |
| keccak_addr_o | out | [KeccakMsgAddrW-1:0] logic | |
| keccak_data_o | out | [MsgWidth-1:0] logic [Share] | |
| keccak_ready_i | in | logic | |
| keccak_run_o | out | logic | keccak_round control and status
|
| keccak_complete_i | in | logic | |
| mode_i | in | sha3_mode_e | configurations |
| strength_i | in | keccak_strength_e | strength_i is used in bytepad operation. bytepad() is used in cSHAKE only. SHA3, SHAKE doesn't have encode_N,S |
| start_i | in | logic | control signal start_i is a pulse signal triggers the padding logic (and the rest of SHA) to accept the incoming messages. This signal is used in the pad module, to initiate the prefix transmitting to keccak_round |
| process_i | in | logic | process_i is a pulse signal triggers the pad logic to stop receiving the
message from MSG_FIFO and pad the trailing bits specified in the SHA3
standard. Look at |
| done_i | in | logic | done_i is a pulse signal to make the pad logic to clear internal variables and to move back to the Idle state for next hashing process. done_i may not needed if sw controls the keccak_round directly. |
| absorbed_o | out | logic | Indication of the Keccak Sponge Absorbing is complete, it is time for SW to
control the Keccak-round if it needs more digest, or complete by asserting
|
This design unit is implemented in tlul_err_resp.sv
This file depends on: top_pkg.sv, tlul_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tl_h_i | in | tl_h2d_t | |
| tl_h_o | out | tl_d2h_t |
This design unit is implemented in tlul_gen_payload_chk.sv
This file depends on: prim_secded_64_57_enc.sv, uvm_pkg.sv, tlul_pkg.sv
tlul_payload_chk
| Name | Direction | Type | Description |
|---|---|---|---|
| tl_i | in | tl_d2h_t | TL-UL interface |
| tl_o | out | tl_d2h_t |
This design unit is implemented in tlul_payload_chk.sv
This file depends on: uvm_pkg.sv, prim_secded_64_57_dec.sv, tlul_pkg.sv
tlul_payload_chk
| Name | Direction | Type | Description |
|---|---|---|---|
| tl_i | in | tl_h2d_t | TL-UL interface |
| err_o | out | logic | error output |
This design unit is implemented in uart_rx.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| rx_enable | in | logic | |
| tick_baud_x16 | in | logic | |
| parity_enable | in | logic | |
| parity_odd | in | logic | |
| tick_baud | out | logic | |
| rx_valid | out | logic | |
| rx_data | out | [7:0] logic | |
| idle | out | logic | |
| frame_err | out | logic | |
| rx_parity_err | out | logic | |
| rx | in | logic |
This design unit is implemented in uart_tx.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| tx_enable | in | logic | |
| tick_baud_x16 | in | logic | |
| parity_enable | in | logic | |
| wr | in | logic | |
| wr_parity | in | logic | |
| wr_data | in | [7:0] logic | |
| idle | out | logic | |
| tx | out | logic |
This design unit is implemented in usb_fs_nb_pe.sv
This file depends on: usb_fs_tx_mux.sv, usb_fs_nb_in_pe.sv, usb_fs_nb_out_pe.sv, usb_consts_pkg.sv, usb_fs_tx.sv, usb_fs_rx.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumOutEps | int | 2 | |
| NumInEps | int | 2 | |
| MaxPktSizeByte | int | 32 | |
| PktW | int | $clog2(MaxPktSizeByte) | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_48mhz_i | in | logic | |
| rst_ni | in | logic | Async. reset, active low |
| link_reset_i | in | logic | USB reset, sync to 48 MHz, active high |
| dev_addr_i | in | [6:0] logic | |
| cfg_eop_single_bit_i | in | logic | 1: detect a single SE0 bit as EOP |
| cfg_rx_differential_i | in | logic | 1: use differential rx data on usb_d_i |
| tx_osc_test_mode_i | in | logic | Oscillator test mode (constantly output JK) |
| data_toggle_clear_i | in | [NumOutEps-1:0] logic | Clear the data toggles for an EP |
| out_ep_current_o | out | [3:0] logic | Other signals address to this ep |
| out_ep_data_put_o | out | logic | put the data (put addr advances after) |
| out_ep_put_addr_o | out | [PktW - 1:0] logic | Offset to put data (0..pktlen) |
| out_ep_data_o | out | [7:0] logic | |
| out_ep_newpkt_o | out | logic | New OUT pkt start (with in_ep_current_o update) |
| out_ep_acked_o | out | logic | good termination, device has acked |
| out_ep_rollback_o | out | logic | bad termination, discard data |
| out_ep_setup_o | out | [NumOutEps-1:0] logic | |
| out_ep_full_i | in | [NumOutEps-1:0] logic | Cannot accept data |
| out_ep_stall_i | in | [NumOutEps-1:0] logic | Stalled |
| out_ep_iso_i | in | [NumOutEps-1:0] logic | Configure endpoint in isochronous mode |
| in_ep_current_o | out | [3:0] logic | Other signals addressed to this ep |
| in_ep_rollback_o | out | logic | Bad termination, rollback transaction |
| in_ep_xfr_end_o | out | logic | good termination, transaction complete |
| in_ep_get_addr_o | out | [PktW - 1:0] logic | Offset requested (0..pktlen) |
| in_ep_data_get_o | out | logic | Accept data (get_addr advances too) |
| in_ep_newpkt_o | out | logic | New IN pkt start (with in_ep_current_o update) |
| in_ep_stall_i | in | [NumInEps-1:0] logic | Endpoint in a stall state |
| in_ep_has_data_i | in | [NumInEps-1:0] logic | Endpoint has data to supply |
| in_ep_data_i | in | [7:0] logic | Data for current get_addr |
| in_ep_data_done_i | in | [NumInEps-1:0] logic | Set when out of data |
| in_ep_iso_i | in | [NumInEps-1:0] logic | Configure endpoint in isochronous mode |
| sof_valid_o | out | logic | sof interface |
| frame_index_o | out | [10:0] logic | |
| rx_jjj_det_o | out | logic | RX line status |
| rx_crc_err_o | out | logic | RX errors |
| rx_pid_err_o | out | logic | |
| rx_bitstuff_err_o | out | logic | |
| usb_d_i | in | logic | USB RX Interface (synchronous) // |
| usb_dp_i | in | logic | |
| usb_dn_i | in | logic | |
| usb_d_o | out | logic | USB TX Interface (synchronous) // |
| usb_se0_o | out | logic | |
| usb_oe_o | out | logic |
This design unit is implemented in usbdev_linkstate.sv
This file depends on: prim_filter.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| SUSPEND_TIMEOUT | [11:0] logic | 12'd3000 | 3ms by spec |
| RESET_TIMEOUT | [2:0] logic | 3'd3 | 3us. Can be 2.5us - 10ms by spec |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_48mhz_i | in | logic | |
| rst_ni | in | logic | |
| us_tick_i | in | logic | |
| usb_sense_i | in | logic | |
| usb_dp_i | in | logic | |
| usb_dn_i | in | logic | |
| usb_oe_i | in | logic | |
| rx_jjj_det_i | in | logic | |
| sof_valid_i | in | logic | |
| link_disconnect_o | out | logic | level |
| link_connect_o | out | logic | level |
| link_reset_o | out | logic | level |
| link_active_o | out | logic | level |
| link_suspend_o | out | logic | level |
| link_resume_o | out | logic | pulse |
| host_lost_o | out | logic | level |
| link_state_o | out | [2:0] logic |
four ticks is a bit time Could completely filter out 2-cycle EOP SE0 here but does not seem needed
This design unit is implemented in aes_cipher_control.sv
This file depends on: prim_flop.sv, uvm_pkg.sv, aes_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Masking | bit | 0 | |
| SBoxImpl | sbox_impl_e | SBoxImplLut | |
| StateWidth | int | 6 | Types
$ ./sparse-fsm-encode.py -d 3 -m 7 -n 6 Hamming distance histogram: 0: -- 1: -- 2: -- 3: |||||||||||||||||||| (57.14%) 4: ||||||||||||||| (42.86%) 5: -- 6: -- Minimum Hamming distance: 3 Maximum Hamming distance: 4 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| in_valid_i | in | logic | Input handshake signals |
| in_ready_o | out | logic | |
| out_valid_o | out | logic | Output handshake signals |
| out_ready_i | in | logic | |
| cfg_valid_i | in | logic | Control and sync signals |
| op_i | in | ciph_op_e | |
| key_len_i | in | key_len_e | |
| crypt_i | in | logic | |
| crypt_o | out | logic | |
| dec_key_gen_i | in | logic | |
| dec_key_gen_o | out | logic | |
| key_clear_i | in | logic | |
| key_clear_o | out | logic | |
| data_out_clear_i | in | logic | |
| data_out_clear_o | out | logic | |
| mux_sel_err_i | in | logic | |
| alert_o | out | logic | |
| prng_update_o | out | logic | Control signals for masking PRNG |
| prng_reseed_req_o | out | logic | |
| prng_reseed_ack_i | in | logic | |
| state_sel_o | out | state_sel_e | Control and sync signals for cipher data path |
| state_we_o | out | logic | |
| sub_bytes_en_o | out | logic | |
| sub_bytes_out_req_i | in | logic | |
| sub_bytes_out_ack_o | out | logic | |
| add_rk_sel_o | out | add_rk_sel_e | |
| key_expand_op_o | out | ciph_op_e | Control and sync signals for key expand data path |
| key_full_sel_o | out | key_full_sel_e | |
| key_full_we_o | out | logic | |
| key_dec_sel_o | out | key_dec_sel_e | |
| key_dec_we_o | out | logic | |
| key_expand_en_o | out | logic | |
| key_expand_out_req_i | in | logic | |
| key_expand_out_ack_o | out | logic | |
| key_expand_clear_o | out | logic | |
| key_expand_round_o | out | [3:0] logic | |
| key_words_sel_o | out | key_words_sel_e | |
| round_key_sel_o | out | round_key_sel_e |
The following primitives are used to place size-only constraints on the flops in order to prevent optimizations on the protected round counter.
This design unit is implemented in aes_key_expand.sv
This file depends on: uvm_pkg.sv, aes_sbox.sv, aes_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| AES192Enable | bit | 1 | |
| Masking | bit | 0 | |
| SBoxImpl | sbox_impl_e | SBoxImplLut | |
| NumShares | int | Masking ? 2 : 1 | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| cfg_valid_i | in | logic | |
| op_i | in | ciph_op_e | |
| en_i | in | logic | |
| out_req_o | out | logic | |
| out_ack_i | in | logic | |
| clear_i | in | logic | |
| round_i | in | [3:0] logic | |
| key_len_i | in | key_len_e | |
| key_i | in | [31:0] [7:0] logic [NumShares] | |
| key_o | out | [31:0] [7:0] logic [NumShares] | |
| prd_i | in | [WidthPRDKey-1:0] logic |
This design unit is implemented in aes_mix_columns.sv
This file depends on: aes_pkg.sv, aes_mix_single_column.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| op_i | in | ciph_op_e | |
| data_i | in | [7:0] [3:0] [3:0] logic | |
| data_o | out | [7:0] [3:0] [3:0] logic |
This design unit is implemented in aes_prng_masking.sv
This file depends on: uvm_pkg.sv, prim_lfsr.sv, prim_cipher_pkg.sv, aes_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | WidthPRDMasking | Must be divisble by ChunkSize and 8. |
| ChunkSize | int | ChunkSizePRDMasking | width of the LFSR primitives |
| NumChunks | int | Width/ChunkSize | derived parameter |
| SecAllowForcingMasks | bit | 0 | Allow forcing masks to 0 using force_zero_masks_i. Useful for SCA only. |
| RndCnstLfsrSeed | masking_lfsr_seed_t | RndCnstMaskingLfsrSeedDefault | |
| RndCnstChunkLfsrPerm | mskg_chunk_lfsr_perm_t | RndCnstMskgChunkLfsrPermDefault | |
| NumBytes | int | Width/8 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| force_zero_masks_i | in | logic | |
| data_update_i | in | logic | Connections to AES internals, PRNG consumers |
| data_o | out | [Width-1:0] logic | |
| reseed_req_i | in | logic | |
| reseed_ack_o | out | logic | |
| entropy_req_o | out | logic | Connections to outer world, LFSR reseeding |
| entropy_ack_i | in | logic | |
| entropy_i | in | [Width-1:0] logic |
This design unit is implemented in aes_reg_status.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| we_i | in | [Width-1:0] logic | |
| use_i | in | logic | |
| clear_i | in | logic | |
| arm_i | in | logic | |
| new_o | out | logic | |
| clean_o | out | logic |
This design unit is implemented in aes_shift_rows.sv
This file depends on: aes_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| op_i | in | ciph_op_e | |
| data_i | in | [7:0] [3:0] [3:0] logic | |
| data_o | out | [7:0] [3:0] [3:0] logic |
This design unit is implemented in aes_sub_bytes.sv
This file depends on: aes_sbox.sv, aes_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| SBoxImpl | sbox_impl_e | SBoxImplLut |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| en_i | in | logic | |
| out_req_o | out | logic | |
| out_ack_i | in | logic | |
| op_i | in | ciph_op_e | |
| data_i | in | [7:0] [3:0] [3:0] logic | |
| mask_i | in | [7:0] [3:0] [3:0] logic | |
| prd_i | in | [WidthPRDSBox-1:0] [3:0] [3:0] logic | |
| data_o | out | [7:0] [3:0] [3:0] logic | |
| mask_o | out | [7:0] [3:0] [3:0] logic |
This design unit is implemented in BUFG.v
| Name | Direction | Type | Description |
|---|---|---|---|
| O | out | logic | |
| I | in | logic |
This design unit is implemented in BUFGCE.v
| Name | Direction | Type | Description |
|---|---|---|---|
| O | out | logic | |
| CE | in | logic | |
| I | in | logic |
This design unit is implemented in BUFGMUX.v
| Name | Type | Default Value | Description |
|---|---|---|---|
| CLK_SEL_TYPE | unknown | "SYNC" |
| Name | Direction | Type | Description |
|---|---|---|---|
| O | out | logic | |
| I0 | in | logic | |
| I1 | in | logic | |
| S | in | logic |
This design unit is implemented in flash_phy_rd_buffers.sv
This file depends on: flash_phy_pkg.sv, flash_ctrl_pkg.sv
flash_phy_rd_buffers
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| en_i | in | logic | |
| alloc_i | in | logic | |
| update_i | in | logic | |
| wipe_i | in | logic | |
| addr_i | in | [BankAddrW-1:0] logic | |
| part_i | in | logic | |
| info_sel_i | in | [InfoTypesWidth-1:0] logic | |
| data_i | in | [DataWidth-1:0] logic | |
| out_o | out | rd_buf_t |
This design unit is implemented in ibex_alu.sv
This file depends on: ibex_pkg.sv
Arithmetic logic unit
| Name | Type | Default Value | Description |
|---|---|---|---|
| RV32B | rv32b_e | ibex_pkg::RV32BNone |
| Name | Direction | Type | Description |
|---|---|---|---|
| operator_i | in | alu_op_e | |
| operand_a_i | in | [31:0] logic | |
| operand_b_i | in | [31:0] logic | |
| instr_first_cycle_i | in | logic | |
| multdiv_operand_a_i | in | [32:0] logic | |
| multdiv_operand_b_i | in | [32:0] logic | |
| multdiv_sel_i | in | logic | |
| imd_val_q_i | in | [31:0] logic [2] | |
| imd_val_d_o | out | [31:0] logic [2] | |
| imd_val_we_o | out | [1:0] logic | |
| adder_result_o | out | [31:0] logic | |
| adder_result_ext_o | out | [33:0] logic | |
| result_o | out | [31:0] logic | |
| comparison_result_o | out | logic | |
| is_equal_result_o | out | logic |
This design unit is implemented in ibex_branch_predict.sv
This file depends on: uvm_pkg.sv, ibex_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| fetch_rdata_i | in | [31:0] logic | Instruction from fetch stage |
| fetch_pc_i | in | [31:0] logic | |
| fetch_valid_i | in | logic | |
| predict_branch_taken_o | out | logic | Prediction for supplied instruction |
| predict_branch_pc_o | out | [31:0] logic |
This design unit is implemented in ibex_compressed_decoder.sv
This file depends on: uvm_pkg.sv, ibex_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| valid_i | in | logic | |
| instr_i | in | [31:0] logic | |
| instr_o | out | [31:0] logic | |
| is_compressed_o | out | logic | |
| illegal_instr_o | out | logic |
This design unit is implemented in ibex_controller.sv
This file depends on: uvm_pkg.sv, ibex_pkg.sv, ibex_id_stage.sv, ibex_core.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| WritebackStage | bit | 0 | |
| BranchPredictor | bit | 0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| ctrl_busy_o | out | logic | core is busy processing instrs |
| illegal_insn_i | in | logic | decoder has an invalid instr |
| ecall_insn_i | in | logic | decoder has ECALL instr |
| mret_insn_i | in | logic | decoder has MRET instr |
| dret_insn_i | in | logic | decoder has DRET instr |
| wfi_insn_i | in | logic | decoder has WFI instr |
| ebrk_insn_i | in | logic | decoder has EBREAK instr |
| csr_pipe_flush_i | in | logic | do CSR-related pipeline flush |
| instr_valid_i | in | logic | instr is valid |
| instr_i | in | [31:0] logic | uncompressed instr data for mtval |
| instr_compressed_i | in | [15:0] logic | instr compressed data for mtval |
| instr_is_compressed_i | in | logic | instr is compressed |
| instr_bp_taken_i | in | logic | instr was predicted taken branch |
| instr_fetch_err_i | in | logic | instr has error |
| instr_fetch_err_plus2_i | in | logic | instr error is x32 |
| pc_id_i | in | [31:0] logic | instr address |
| instr_valid_clear_o | out | logic | kill instr in IF-ID reg |
| id_in_ready_o | out | logic | ID stage is ready for new instr |
| controller_run_o | out | logic | Controller is in standard instruction run mode |
| instr_req_o | out | logic | start fetching instructions |
| pc_set_o | out | logic | jump to address set by pc_mux |
| pc_set_spec_o | out | logic | speculative branch |
| pc_mux_o | out | pc_sel_e | IF stage fetch address selector (boot, normal, exception...) |
| nt_branch_mispredict_o | out | logic | Not-taken branch in ID/EX was mispredicted (predicted taken) |
| exc_pc_mux_o | out | exc_pc_sel_e | IF stage selector for exception PC |
| exc_cause_o | out | exc_cause_e | for IF stage, CSRs |
| lsu_addr_last_i | in | [31:0] logic | for mtval |
| load_err_i | in | logic | |
| store_err_i | in | logic | |
| wb_exception_o | out | logic | Instruction in WB taking an exception |
| branch_set_i | in | logic | branch set signal (branch definitely taken) |
| branch_set_spec_i | in | logic | speculative branch signal (branch may be taken) |
| branch_not_set_i | in | logic | branch is definitely not taken |
| jump_set_i | in | logic | jump taken set signal |
| csr_mstatus_mie_i | in | logic | M-mode interrupt enable bit |
| irq_pending_i | in | logic | interrupt request pending |
| irqs_i | in | irqs_t | interrupt requests qualified with mie CSR |
| irq_nm_i | in | logic | non-maskeable interrupt |
| nmi_mode_o | out | logic | core executing NMI handler |
| debug_req_i | in | logic | debug signals |
| debug_cause_o | out | dbg_cause_e | |
| debug_csr_save_o | out | logic | |
| debug_mode_o | out | logic | |
| debug_single_step_i | in | logic | |
| debug_ebreakm_i | in | logic | |
| debug_ebreaku_i | in | logic | |
| trigger_match_i | in | logic | |
| csr_save_if_o | out | logic | |
| csr_save_id_o | out | logic | |
| csr_save_wb_o | out | logic | |
| csr_restore_mret_id_o | out | logic | |
| csr_restore_dret_id_o | out | logic | |
| csr_save_cause_o | out | logic | |
| csr_mtval_o | out | [31:0] logic | |
| priv_mode_i | in | priv_lvl_e | |
| csr_mstatus_tw_i | in | logic | |
| stall_id_i | in | logic | stall & flush signals |
| stall_wb_i | in | logic | |
| flush_id_o | out | logic | |
| ready_wb_i | in | logic | |
| perf_jump_o | out | logic | we are executing a jump instruction (j, jr, jal, jalr) |
| perf_tbranch_o | out | logic | we are executing a taken branch instruction |
This design unit is implemented in ibex_counter.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| CounterWidth | int | 32 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| counter_inc_i | in | logic | |
| counterh_we_i | in | logic | |
| counter_we_i | in | logic | |
| counter_val_i | in | [31:0] logic | |
| counter_val_o | out | [63:0] logic |
This design unit is implemented in ibex_csr.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 32 | |
| ShadowCopy | bit | 1'b0 | |
| ResetValue | [Width-1:0] bit | '0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wr_data_i | in | [Width-1:0] logic | |
| wr_en_i | in | logic | |
| rd_data_o | out | [Width-1:0] logic | |
| rd_error_o | out | logic |
This design unit is implemented in ibex_decoder.sv
This file depends on: uvm_pkg.sv, ibex_pkg.sv
controller
| Name | Type | Default Value | Description |
|---|---|---|---|
| RV32E | bit | 0 | |
| RV32M | rv32m_e | ibex_pkg::RV32MFast | |
| RV32B | rv32b_e | ibex_pkg::RV32BNone | |
| BranchTargetALU | bit | 0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| illegal_insn_o | out | logic | illegal instr encountered |
| ebrk_insn_o | out | logic | trap instr encountered |
| mret_insn_o | out | logic | return from exception instr encountered |
| dret_insn_o | out | logic | return from debug instr encountered |
| ecall_insn_o | out | logic | syscall instr encountered |
| wfi_insn_o | out | logic | wait for interrupt instr encountered |
| jump_set_o | out | logic | jump taken set signal |
| branch_taken_i | in | logic | registered branch decision |
| icache_inval_o | out | logic | |
| instr_first_cycle_i | in | logic | instruction read is in its first cycle |
| instr_rdata_i | in | [31:0] logic | instruction read from memory/cache |
| instr_rdata_alu_i | in | [31:0] logic | instruction read from memory/cache replicated to ease fan-out) |
| illegal_c_insn_i | in | logic | compressed instruction decode failed |
| imm_a_mux_sel_o | out | imm_a_sel_e | immediate selection for operand a |
| imm_b_mux_sel_o | out | imm_b_sel_e | immediate selection for operand b |
| bt_a_mux_sel_o | out | op_a_sel_e | branch target selection operand a |
| bt_b_mux_sel_o | out | imm_b_sel_e | branch target selection operand b |
| imm_i_type_o | out | [31:0] logic | |
| imm_s_type_o | out | [31:0] logic | |
| imm_b_type_o | out | [31:0] logic | |
| imm_u_type_o | out | [31:0] logic | |
| imm_j_type_o | out | [31:0] logic | |
| zimm_rs1_type_o | out | [31:0] logic | |
| rf_wdata_sel_o | out | rf_wd_sel_e | RF write data selection |
| rf_we_o | out | logic | write enable for regfile |
| rf_raddr_a_o | out | [4:0] logic | |
| rf_raddr_b_o | out | [4:0] logic | |
| rf_waddr_o | out | [4:0] logic | |
| rf_ren_a_o | out | logic | Instruction reads from RF addr A |
| rf_ren_b_o | out | logic | Instruction reads from RF addr B |
| alu_operator_o | out | alu_op_e | ALU operation selection |
| alu_op_a_mux_sel_o | out | op_a_sel_e | operand a selection: reg value, PC, immediate or zero |
| alu_op_b_mux_sel_o | out | op_b_sel_e | operand b selection: reg value or immediate |
| alu_multicycle_o | out | logic | ternary bitmanip instruction |
| mult_en_o | out | logic | perform integer multiplication |
| div_en_o | out | logic | perform integer division or remainder |
| mult_sel_o | out | logic | as above but static, for data muxes |
| div_sel_o | out | logic | as above but static, for data muxes |
| multdiv_operator_o | out | md_op_e | |
| multdiv_signed_mode_o | out | [1:0] logic | |
| csr_access_o | out | logic | access to CSR |
| csr_op_o | out | csr_op_e | operation to perform on CSR |
| data_req_o | out | logic | start transaction to data memory |
| data_we_o | out | logic | write enable |
| data_type_o | out | [1:0] logic | size of transaction: byte, half word or word |
| data_sign_extension_o | out | logic | sign extension for data read from memory |
| jump_in_dec_o | out | logic | jump is being calculated in ALU |
| branch_in_dec_o | out | logic |
This design unit is implemented in ibex_dummy_instr.sv
This file depends on: prim_lfsr.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| TIMEOUT_CNT_W | int | 5 | |
| OP_W | int | 5 | |
| LFSR_OUT_W | int | $bits(lfsr_data_t) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock and reset |
| rst_ni | in | logic | |
| dummy_instr_en_i | in | logic | Interface to CSRs |
| dummy_instr_mask_i | in | [2:0] logic | |
| dummy_instr_seed_en_i | in | logic | |
| dummy_instr_seed_i | in | [31:0] logic | |
| fetch_valid_i | in | logic | Interface to IF stage |
| id_in_ready_i | in | logic | |
| insert_dummy_instr_o | out | logic | |
| dummy_instr_data_o | out | [31:0] logic |
This design unit is implemented in ibex_icache.sv
This file depends on: prim_secded_28_22_enc.sv, prim_secded_72_64_dec.sv, uvm_pkg.sv, prim_secded_28_22_dec.sv, prim_secded_72_64_enc.sv, prim_ram_1p.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| BusWidth | int | 32 | Cache arrangement parameters |
| CacheSizeBytes | int | 4*1024 | |
| ICacheECC | bit | 1'b0 | |
| LineSize | int | 64 | |
| NumWays | int | 2 | |
| SpecRequest | bit | 1'b0 | Always make speculative bus requests in parallel with lookups |
| BranchCache | bit | 1'b0 | Only cache branch targets |
| ADDR_W | int | 32 | Local constants |
| NUM_FB | int | 4 | Number of fill buffers (must be >= 2) |
| FB_THRESHOLD | int | NUM_FB - 2 | Request throttling threshold |
| LINE_SIZE_ECC | int | ICacheECC ? (LineSize + 8) : LineSize | Derived parameters |
| LINE_SIZE_BYTES | int | LineSize/8 | |
| LINE_W | int | $clog2(LINE_SIZE_BYTES) | |
| BUS_BYTES | int | BusWidth/8 | |
| BUS_W | int | $clog2(BUS_BYTES) | |
| LINE_BEATS | int | LINE_SIZE_BYTES / BUS_BYTES | |
| LINE_BEATS_W | int | $clog2(LINE_BEATS) | |
| NUM_LINES | int | CacheSizeBytes / NumWays / LINE_SIZE_BYTES | |
| INDEX_W | int | $clog2(NUM_LINES) | |
| INDEX_HI | int | INDEX_W + LINE_W - 1 | |
| TAG_SIZE | int | ADDR_W - INDEX_W - LINE_W + 1 | 1 valid bit |
| TAG_SIZE_ECC | int | ICacheECC ? (TAG_SIZE + 6) : TAG_SIZE | |
| OUTPUT_BEATS | int | (BUS_BYTES / 2) | number of halfwords |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | Clock and reset |
| rst_ni | in | logic | |
| req_i | in | logic | Signal that the core would like instructions |
| branch_i | in | logic | Set the cache's address counter |
| branch_spec_i | in | logic | |
| addr_i | in | [31:0] logic | |
| ready_i | in | logic | IF stage interface: Pass fetched instructions to the core |
| valid_o | out | logic | |
| rdata_o | out | [31:0] logic | |
| addr_o | out | [31:0] logic | |
| err_o | out | logic | |
| err_plus2_o | out | logic | |
| instr_req_o | out | logic | Instruction memory / interconnect interface: Fetch instruction data from memory |
| instr_gnt_i | in | logic | |
| instr_addr_o | out | [31:0] logic | |
| instr_rdata_i | in | [BusWidth-1:0] logic | |
| instr_err_i | in | logic | |
| instr_pmp_err_i | in | logic | |
| instr_rvalid_i | in | logic | |
| icache_enable_i | in | logic | Cache status |
| icache_inval_i | in | logic | |
| busy_o | out | logic |
This design unit is implemented in ibex_multdiv_fast.sv
This file depends on: uvm_pkg.sv, ibex_pkg.sv
ibex_mult
| Name | Type | Default Value | Description |
|---|---|---|---|
| RV32M | rv32m_e | ibex_pkg::RV32MFast |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| mult_en_i | in | logic | dynamic enable signal, for FSM control |
| div_en_i | in | logic | dynamic enable signal, for FSM control |
| mult_sel_i | in | logic | static decoder output, for data muxes |
| div_sel_i | in | logic | static decoder output, for data muxes |
| operator_i | in | md_op_e | |
| signed_mode_i | in | [1:0] logic | |
| op_a_i | in | [31:0] logic | |
| op_b_i | in | [31:0] logic | |
| alu_adder_ext_i | in | [33:0] logic | |
| alu_adder_i | in | [31:0] logic | |
| equal_to_zero_i | in | logic | |
| data_ind_timing_i | in | logic | |
| alu_operand_a_o | out | [32:0] logic | |
| alu_operand_b_o | out | [32:0] logic | |
| imd_val_q_i | in | [33:0] logic [2] | |
| imd_val_d_o | out | [33:0] logic [2] | |
| imd_val_we_o | out | [1:0] logic | |
| multdiv_ready_id_i | in | logic | |
| multdiv_result_o | out | [31:0] logic | |
| valid_o | out | logic |
This design unit is implemented in ibex_multdiv_slow.sv
This file depends on: uvm_pkg.sv, ibex_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| mult_en_i | in | logic | dynamic enable signal, for FSM control |
| div_en_i | in | logic | dynamic enable signal, for FSM control |
| mult_sel_i | in | logic | static decoder output, for data muxes |
| div_sel_i | in | logic | static decoder output, for data muxes |
| operator_i | in | md_op_e | |
| signed_mode_i | in | [1:0] logic | |
| op_a_i | in | [31:0] logic | |
| op_b_i | in | [31:0] logic | |
| alu_adder_ext_i | in | [33:0] logic | |
| alu_adder_i | in | [31:0] logic | |
| equal_to_zero_i | in | logic | |
| data_ind_timing_i | in | logic | |
| alu_operand_a_o | out | [32:0] logic | |
| alu_operand_b_o | out | [32:0] logic | |
| imd_val_q_i | in | [33:0] logic [2] | |
| imd_val_d_o | out | [33:0] logic [2] | |
| imd_val_we_o | out | [1:0] logic | |
| multdiv_ready_id_i | in | logic | |
| multdiv_result_o | out | [31:0] logic | |
| valid_o | out | logic |
This design unit is implemented in ibex_prefetch_buffer.sv
This file depends on: ibex_fetch_fifo.sv
Prefetcher Buffer for 32 bit memory interface
Prefetch Buffer that caches instructions. This cuts overly long critical
paths to the instruction cache.
| Name | Type | Default Value | Description |
|---|---|---|---|
| BranchPredictor | bit | 1'b0 | |
| NUM_REQS | int | 2 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | logic | |
| branch_i | in | logic | |
| branch_spec_i | in | logic | |
| predicted_branch_i | in | logic | |
| branch_mispredict_i | in | logic | |
| addr_i | in | [31:0] logic | |
| ready_i | in | logic | |
| valid_o | out | logic | |
| rdata_o | out | [31:0] logic | |
| addr_o | out | [31:0] logic | |
| err_o | out | logic | |
| err_plus2_o | out | logic | |
| instr_req_o | out | logic | goes to instruction memory / instruction cache |
| instr_gnt_i | in | logic | |
| instr_addr_o | out | [31:0] logic | |
| instr_rdata_i | in | [31:0] logic | |
| instr_err_i | in | logic | |
| instr_pmp_err_i | in | logic | |
| instr_rvalid_i | in | logic | |
| busy_o | out | logic | Prefetch Buffer Status |
This design unit is implemented in otbn_loop_controller.sv
This file depends on: uvm_pkg.sv, otbn_stack.sv, otbn_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| ImemAddrWidth | int | 12 | |
| LoopStackDepth | int | 7 | The loop controller has a current loop and then a stack of outer loops, this sets the size of the stack so maximum loop nesting depth is LoopStackDepth + 1. |
| LoopEndAddrWidth | int | ImemAddrWidth < 14 ? 14 : ImemAddrWidth | ISA has a fixed 12 bits for loop_bodysize. When IMEM size is less than 16 kB (ImemAddrWidth < 14) some of these bits are ignored as a loop body cannot be greater than the IMEM size. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| insn_valid_i | in | logic | |
| insn_addr_i | in | [ImemAddrWidth-1:0] logic | |
| next_insn_addr_i | in | [ImemAddrWidth-1:0] logic | |
| loop_start_req_i | in | logic | |
| loop_start_commit_i | in | logic | |
| loop_bodysize_i | in | [11:0] logic | |
| loop_iterations_i | in | [31:0] logic | |
| loop_jump_o | out | logic | |
| loop_jump_addr_o | out | [ImemAddrWidth-1:0] logic | |
| loop_err_o | out | logic | |
| branch_taken_i | in | logic | |
| otbn_stall_i | in | logic |
This design unit is implemented in otbn_rf_base_ff.sv
This file depends on: otbn_pkg.sv
32b General Purpose Register File (GPRs)
Features:
2 read ports
1 write port
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wr_addr_i | in | [4:0] logic | |
| wr_en_i | in | logic | |
| wr_data_i | in | [31:0] logic | |
| rd_addr_a_i | in | [4:0] logic | |
| rd_data_a_o | out | [31:0] logic | |
| rd_addr_b_i | in | [4:0] logic | |
| rd_data_b_o | out | [31:0] logic |
This design unit is implemented in otbn_rf_base_fpga.sv
This file depends on: otbn_pkg.sv
32b General Purpose Register File (GPRs)
Features:
2 read ports
1 write port
Register 0 is fixed to 0.
This register file is designed to make FPGA synthesis tools infer RAM primitives. For Xilinx
FPGA architectures, it will produce RAM32M primitives. Other vendors have not yet been tested.
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| wr_addr_i | in | [4:0] logic | |
| wr_en_i | in | logic | |
| wr_data_i | in | [31:0] logic | |
| rd_addr_a_i | in | [4:0] logic | |
| rd_data_a_o | out | [31:0] logic | |
| rd_addr_b_i | in | [4:0] logic | |
| rd_data_b_o | out | [31:0] logic |
This design unit is implemented in otbn_stack.sv
This file depends on: prim_util_pkg.sv, otbn_pkg.sv
Simple stack parameterised on width and depth
When a push and pop occur in the same cycle the pop is ordered before the push (so top_data_o
reflects what was on top of the stack, which is retrieved by the pop, the push then immediately
replaces this with a new piece of data). Internal checking is performed for full & empty
conditions so a push on full/pop on empty is allowable, though meaningless. For a push on full
the data will be dropped, for a pop no empty there is no valid data to pop. The exception is
a combined push & pop on full, here the top is popped off and replaced with what is pushed, no
data is dropped.
| Name | Type | Default Value | Description |
|---|---|---|---|
| StackWidth | int | 32 | |
| StackDepth | int | 4 | |
| StackDepthW | int | prim_util_pkg::vbits(StackDepth) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| full_o | out | logic | Stack is full |
| push_i | in | logic | Push the data |
| push_data_i | in | [StackWidth-1:0] logic | Data to push |
| pop_i | in | logic | Pop top of the stack |
| top_data_o | out | [StackWidth-1:0] logic | Data on top of the stack |
| top_valid_o | out | logic | Stack is non empty ( |
This design unit is implemented in prim_generic_buf.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in_i | in | logic | |
| out_o | out | logic |
This design unit is implemented in prim_generic_flash_bank.sv
This file depends on: flash_ctrl_pkg.sv, prim_fifo_sync.sv, prim_ram_1p.sv
prim_generic_flash
| Name | Type | Default Value | Description |
|---|---|---|---|
| InfosPerBank | int | 1 | info pages per bank |
| InfoTypes | int | 1 | different info types |
| InfoTypesWidth | int | 1 | different info types |
| PagesPerBank | int | 256 | data pages per bank |
| WordsPerPage | int | 256 | words per page |
| DataWidth | int | 32 | bits per word |
| MetaDataWidth | int | 12 | this is a temporary parameter to work around ECC issues |
| PageW | int | $clog2(PagesPerBank) | Derived parameters |
| WordW | int | $clog2(WordsPerPage) | |
| AddrW | int | PageW + WordW | |
| ReadCycles | int | 1 | Emulated flash macro values |
| ProgCycles | int | 50 | |
| PgEraseCycles | int | 200 | |
| BkEraseCycles | int | 2000 | |
| InitCycles | int | 100 | |
| WordsPerBank | int | PagesPerBank * WordsPerPage | Locally derived values |
| WordsPerInfoBank | int | InfosPerBank * WordsPerPage | |
| InfoAddrW | int | $clog2(WordsPerInfoBank) | |
| MemWidth | int | DataWidth - MetaDataWidth |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| rd_i | in | logic | |
| prog_i | in | logic | |
| prog_last_i | in | logic | |
| prog_type_i | in | flash_prog_e | the generic model does not make use of program types |
| pg_erase_i | in | logic | |
| bk_erase_i | in | logic | |
| erase_suspend_req_i | in | logic | |
| he_i | in | logic | |
| addr_i | in | [AddrW-1:0] logic | |
| part_i | in | flash_part_e | |
| info_sel_i | in | [InfoTypesWidth-1:0] logic | |
| prog_data_i | in | [DataWidth-1:0] logic | |
| ack_o | out | logic | |
| done_o | out | logic | |
| rd_data_o | out | [DataWidth-1:0] logic | |
| init_i | in | logic | |
| init_busy_o | out | logic | |
| flash_power_ready_h_i | in | logic | |
| flash_power_down_h_i | in | logic |
This design unit is implemented in prim_generic_ram_1p.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 32 | bit |
| Depth | int | 128 | |
| DataBitsPerMask | int | 1 | Number of data bits per bit of write mask |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| Aw | int | $clog2(Depth) | derived parameter |
| MaskWidth | int | Width / DataBitsPerMask | Width of internal write mask. Note wmask_i input into the module is always assumed to be the full bit mask |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| req_i | in | logic | |
| write_i | in | logic | |
| addr_i | in | [Aw-1:0] logic | |
| wdata_i | in | [Width-1:0] logic | |
| wmask_i | in | [Width-1:0] logic | |
| rdata_o | out | [Width-1:0] logic | Read data. Data is returned one cycle after req_i is high. |
This design unit is implemented in prim_generic_ram_2p.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 32 | bit |
| Depth | int | 128 | |
| DataBitsPerMask | int | 1 | Number of data bits per bit of write mask |
| MemInitFile | unknown | "" | VMEM file to initialize the memory with |
| Aw | int | $clog2(Depth) | derived parameter |
| MaskWidth | int | Width / DataBitsPerMask | Width of internal write mask. Note *_wmask_i input into the module is always assumed to be the full bit mask. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_a_i | in | logic | |
| clk_b_i | in | logic | |
| a_req_i | in | logic | |
| a_write_i | in | logic | |
| a_addr_i | in | [Aw-1:0] logic | |
| a_wdata_i | in | [Width-1:0] logic | |
| a_wmask_i | in | [Width-1:0] logic | |
| a_rdata_o | out | [Width-1:0] logic | |
| b_req_i | in | logic | |
| b_write_i | in | logic | |
| b_addr_i | in | [Aw-1:0] logic | |
| b_wdata_i | in | [Width-1:0] logic | |
| b_wmask_i | in | [Width-1:0] logic | |
| b_rdata_o | out | [Width-1:0] logic |
This design unit is implemented in prim_gf_mult.sv
This file depends on: uvm_pkg.sv
prim_gf_mult
| Name | Type | Default Value | Description |
|---|---|---|---|
| Width | int | 32 | |
| StagesPerCycle | int | Width | |
| IPoly | [Width-1:0] logic | 1'b1 << 15 | 1'b1 << 9 | 1'b1 << 7 | 1'b1 << 4 | 1'b1 << 3 | 1'b1 << 0 | The field-generating, irreducible polynomial of degree Width. Can for example be a Conway polynomial, see http://www.math.rwth-aachen.de/~Frank.Luebeck/data/ConwayPol/CP2.html For Width = 33, the Conway polynomial hast bits 32, 15, 9, 7, 4, 3, 0 set to one. |
| Loops | int | Width / StagesPerCycle | |
| CntWidth | int | (Loops == 1) ? 1 : $clog2(Loops) |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| req_i | in | logic | |
| operand_a_i | in | [Width-1:0] logic | |
| operand_b_i | in | [Width-1:0] logic | |
| ack_o | out | logic | |
| prod_o | out | [Width-1:0] logic |
This design unit is implemented in prim_secded_64_57_dec.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [63:0] logic | |
| d_o | out | [56:0] logic | |
| syndrome_o | out | [6:0] logic | |
| err_o | out | [1:0] logic |
This design unit is implemented in prim_secded_72_64_dec.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [71:0] logic | |
| d_o | out | [63:0] logic | |
| syndrome_o | out | [7:0] logic | |
| err_o | out | [1:0] logic |
This design unit is implemented in prim_secded_72_64_enc.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [63:0] logic | |
| out | out | [71:0] logic |
This design unit is implemented in prim_secded_hamming_72_64_dec.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [71:0] logic | |
| d_o | out | [63:0] logic | |
| syndrome_o | out | [7:0] logic | |
| err_o | out | [1:0] logic |
This design unit is implemented in prim_secded_hamming_72_64_enc.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [63:0] logic | |
| out | out | [71:0] logic |
This design unit is implemented in prim_xilinx_buf.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in_i | in | logic | |
| out_o | out | logic |
This design unit is implemented in usb_consts_pkg.sv
This design unit is implemented in usb_fs_nb_in_pe.sv
This file depends on: usb_consts_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumInEps | [4:0] logic | 12 | |
| MaxInPktSizeByte | int | 32 | |
| InEpW | int | $clog2(NumInEps) | derived parameter |
| PktW | int | $clog2(MaxInPktSizeByte) | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_48mhz_i | in | logic | |
| rst_ni | in | logic | |
| link_reset_i | in | logic | |
| dev_addr_i | in | [6:0] logic | |
| in_ep_current_o | out | [3:0] logic | Other signals addressed to this ep |
| in_ep_rollback_o | out | logic | Bad termination, rollback transaction |
| in_ep_xfr_end_o | out | logic | good termination, transaction complete |
| in_ep_get_addr_o | out | [PktW - 1:0] logic | Offset requested (0..pktlen) |
| in_ep_data_get_o | out | logic | Accept data (get_addr advances too) |
| in_ep_newpkt_o | out | logic | New IN packet starting (updates in_ep_current_o) |
| in_ep_stall_i | in | [NumInEps-1:0] logic | Endpoint in a stall state |
| in_ep_has_data_i | in | [NumInEps-1:0] logic | Endpoint has data to supply |
| in_ep_data_i | in | [7:0] logic | Data for current get_addr |
| in_ep_data_done_i | in | [NumInEps-1:0] logic | Set when out of data |
| in_ep_iso_i | in | [NumInEps-1:0] logic | Configure endpoint in isochronous mode |
| data_toggle_clear_i | in | [NumInEps-1:0] logic | Clear the data toggles for an EP |
| rx_pkt_start_i | in | logic | Strobed on reception of packet. |
| rx_pkt_end_i | in | logic | |
| rx_pkt_valid_i | in | logic | |
| rx_pid_i | in | [3:0] logic | Most recent packet received. |
| rx_addr_i | in | [6:0] logic | |
| rx_endp_i | in | [3:0] logic | |
| tx_pkt_start_o | out | logic | Strobe to send new packet. |
| tx_pkt_end_i | in | logic | |
| tx_pid_o | out | [3:0] logic | Packet type to send |
| tx_data_avail_o | out | logic | Data payload to send if any |
| tx_data_get_i | in | logic | |
| tx_data_o | out | [7:0] logic |
This design unit is implemented in usb_fs_nb_out_pe.sv
This file depends on: usb_consts_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NumOutEps | [4:0] logic | 2 | |
| MaxOutPktSizeByte | int | 32 | |
| OutEpW | int | $clog2(NumOutEps) | derived parameter |
| PktW | int | $clog2(MaxOutPktSizeByte) | derived parameter |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_48mhz_i | in | logic | |
| rst_ni | in | logic | |
| link_reset_i | in | logic | |
| dev_addr_i | in | [6:0] logic | |
| out_ep_current_o | out | [3:0] logic | Other signals address to this ep, stable for several cycles |
| out_ep_data_put_o | out | logic | put the data (put addr advances after) |
| out_ep_put_addr_o | out | [PktW - 1:0] logic | Offset to put data (0..pktlen) |
| out_ep_data_o | out | [7:0] logic | |
| out_ep_newpkt_o | out | logic | new packed, current was set |
| out_ep_acked_o | out | logic | good termination, device has acked |
| out_ep_rollback_o | out | logic | bad termination, discard data |
| out_ep_setup_o | out | [NumOutEps-1:0] logic | |
| out_ep_full_i | in | [NumOutEps-1:0] logic | Cannot accept data |
| out_ep_stall_i | in | [NumOutEps-1:0] logic | Stalled |
| out_ep_iso_i | in | [NumOutEps-1:0] logic | Configure endpoint in isochronous mode |
| data_toggle_clear_i | in | [NumOutEps-1:0] logic | Clear the data toggles for an EP |
| rx_pkt_start_i | in | logic | Strobed on reception of packet. |
| rx_pkt_end_i | in | logic | |
| rx_pkt_valid_i | in | logic | |
| rx_pid_i | in | [3:0] logic | Most recent packet received. |
| rx_addr_i | in | [6:0] logic | |
| rx_endp_i | in | [3:0] logic | |
| rx_data_put_i | in | logic | rx_data is pushed into endpoint controller. |
| rx_data_i | in | [7:0] logic | |
| tx_pkt_start_o | out | logic | Strobe to send new packet. |
| tx_pkt_end_i | in | logic | |
| tx_pid_o | out | [3:0] logic |
This design unit is implemented in usb_fs_rx.sv
usb_fs_rx
| Name | Type | Default Value | Description |
|---|---|---|---|
| DT | [2:0] logic | 3'b100 | transition state |
| DJ | [2:0] logic | 3'b010 | J - idle line state |
| DK | [2:0] logic | 3'b001 | K - inverse of J |
| SE0 | [2:0] logic | 3'b000 | single-ended 0 - end of packet or detached |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | A 48MHz clock is required to recover the clock from the incoming data. |
| rst_ni | in | logic | |
| link_reset_i | in | logic | |
| cfg_eop_single_bit_i | in | logic | configuration |
| cfg_rx_differential_i | in | logic | |
| usb_d_i | in | logic | USB data+ and data- lines (synchronous) |
| usb_dp_i | in | logic | |
| usb_dn_i | in | logic | |
| tx_en_i | in | logic | Transmit enable disables the receier |
| bit_strobe_o | out | logic | pulse on every bit transition. |
| pkt_start_o | out | logic | Pulse on beginning of new packet. |
| pkt_end_o | out | logic | Pulse on end of current packet. |
| pid_o | out | [3:0] logic | Most recent packet decoded. |
| addr_o | out | [6:0] logic | |
| endp_o | out | [3:0] logic | |
| frame_num_o | out | [10:0] logic | |
| rx_data_put_o | out | logic | Pulse on valid data on rx_data. |
| rx_data_o | out | [7:0] logic | |
| valid_packet_o | out | logic | Most recent packet passes PID and CRC checks |
| rx_jjj_det_o | out | logic | line status for the status detection (actual rx bits after clock recovery) |
| crc_error_o | out | logic | Error detection |
| pid_error_o | out | logic | |
| bitstuff_error_o | out | logic |
This design unit is implemented in usb_fs_tx.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | A 48MHz clock is required to receive USB data at 12MHz it's simpler to juse use 48MHz everywhere |
| rst_ni | in | logic | asyc reset |
| link_reset_i | in | logic | USB reset, sync to 48 MHz, active high |
| tx_osc_test_mode_i | in | logic | Oscillator test mode (constantly output JK) |
| bit_strobe_i | in | logic | bit strobe from rx to align with senders clock |
| usb_oe_o | out | logic | output enable to take ownership of bus and data out |
| usb_d_o | out | logic | |
| usb_se0_o | out | logic | |
| pkt_start_i | in | logic | pulse to initiate new packet transmission |
| pkt_end_o | out | logic | |
| pid_i | in | [3:0] logic | pid_i to send |
| tx_data_avail_i | in | logic | tx logic pulls data until there is nothing available |
| tx_data_get_o | out | logic | |
| tx_data_i | in | [7:0] logic |
This design unit is implemented in usb_fs_tx_mux.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in_tx_pkt_start_i | in | logic | interface to IN Protocol Engine |
| in_tx_pid_i | in | [3:0] logic | |
| out_tx_pkt_start_i | in | logic | interface to OUT Protocol Engine |
| out_tx_pid_i | in | [3:0] logic | |
| tx_pkt_start_o | out | logic | interface to tx module |
| tx_pid_o | out | [3:0] logic |
This design unit is implemented in aes_mix_single_column.sv
This file depends on: aes_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| op_i | in | ciph_op_e | |
| data_i | in | [7:0] [3:0] logic | |
| data_o | out | [7:0] [3:0] logic |
This design unit is implemented in aes_sbox.sv
This file depends on: aes_sbox_dom.sv, uvm_pkg.sv, aes_sbox_lut.sv, aes_sbox_canright_masked.sv, aes_sbox_canright.sv, aes_pkg.sv, aes_sbox_canright_masked_noreuse.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| SBoxImpl | sbox_impl_e | SBoxImplLut | |
| SBoxMasked | bit | (SBoxImpl == SBoxImplCanrightMasked || SBoxImpl == SBoxImplCanrightMaskedNoreuse || SBoxImpl == SBoxImplDom) ? 1'b1 : 1'b0 | |
| SBoxSingleCycle | bit | (SBoxImpl == SBoxImplDom) ? 1'b0 : 1'b1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| en_i | in | logic | |
| out_req_o | out | logic | |
| out_ack_i | in | logic | |
| op_i | in | ciph_op_e | |
| data_i | in | [7:0] logic | |
| mask_i | in | [7:0] logic | |
| prd_i | in | [WidthPRDSBox-1:0] logic | |
| data_o | out | [7:0] logic | |
| mask_o | out | [7:0] logic |
This design unit is implemented in ibex_fetch_fifo.sv
This file depends on: uvm_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| NUM_REQS | int | 2 | |
| DEPTH | int | NUM_REQS+1 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| clear_i | in | logic | clears the contents of the FIFO |
| busy_o | out | [NUM_REQS-1:0] logic | |
| in_valid_i | in | logic | input port |
| in_addr_i | in | [31:0] logic | |
| in_rdata_i | in | [31:0] logic | |
| in_err_i | in | logic | |
| out_valid_o | out | logic | output port |
| out_ready_i | in | logic | |
| out_addr_o | out | [31:0] logic | |
| out_addr_next_o | out | [31:0] logic | |
| out_rdata_o | out | [31:0] logic | |
| out_err_o | out | logic | |
| out_err_plus2_o | out | logic |
This design unit is implemented in prim_secded_28_22_dec.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [27:0] logic | |
| d_o | out | [21:0] logic | |
| syndrome_o | out | [5:0] logic | |
| err_o | out | [1:0] logic |
This design unit is implemented in prim_secded_28_22_enc.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| in | in | [21:0] logic | |
| out | out | [27:0] logic |
This design unit is implemented in aes_sbox_dom.sv
This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv
DOM-dep GF(2^N) multiplier, first-order masked. Computes (a_q ^ b_q) = (a_x ^ b_x) * (a_y ^ b_y), i.e. q = x * y using first-order domain-oriented masking. The sharings of x and y are NOT required to be independent from each other. This is the optimized version consuming 2 instead of 3 times N bits of randomness for blinding and resharing. See Formula 12 in 1.
| Name | Type | Default Value | Description |
|---|---|---|---|
| NPower | int | 4 | |
| Pipeline | bit | 1'b0 | |
| PreDomIndep | bit | 1'b0 | 1'b0: Not followed by an un-pipelined DOM-indep multiplier, this enables additional area optimizations 1'b1: Directly followed by an un-pipelined DOM-indep multiplier, this is the version discussed in 1. |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| we_i | in | logic | |
| a_x | in | [NPower-1:0] logic | Share a of x |
| a_y | in | [NPower-1:0] logic | Share a of y |
| b_x | in | [NPower-1:0] logic | Share b of x |
| b_y | in | [NPower-1:0] logic | Share b of y |
| z_0 | in | [NPower-1:0] logic | Randomness for blinding |
| z_1 | in | [NPower-1:0] logic | Randomness for resharing |
| a_q | out | [NPower-1:0] logic | Share a of q |
| b_q | out | [NPower-1:0] logic | Share b of q |
This design unit is implemented in aes_sbox_dom.sv
This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv
DOM-dep GF(2^N) multiplier, first-order masked. Computes (a_q ^ b_q) = (a_x ^ b_x) * (a_y ^ b_y), i.e. q = x * y using first-order domain-oriented masking. The sharings of x and y are NOT required to be independent from each other. This is the un-optimized version consuming 3 times N bits of randomness for blinding and resharing. It is not used in the design but we keep it for reference. See Fig. 4 and Formulas 8 - 11 in 1.
| Name | Type | Default Value | Description |
|---|---|---|---|
| NPower | int | 4 | |
| Pipeline | bit | 1'b0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| we_i | in | logic | |
| a_x | in | [NPower-1:0] logic | Share a of x |
| a_y | in | [NPower-1:0] logic | Share a of y |
| b_x | in | [NPower-1:0] logic | Share b of x |
| b_y | in | [NPower-1:0] logic | Share b of y |
| a_z | in | [NPower-1:0] logic | Randomness for blinding |
| b_z | in | [NPower-1:0] logic | Randomness for blinding |
| z_0 | in | [NPower-1:0] logic | Randomness for resharing |
| a_q | out | [NPower-1:0] logic | Share a of q |
| b_q | out | [NPower-1:0] logic | Share b of q |
This design unit is implemented in aes_sbox_dom.sv
This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv
DOM-indep GF(2^N) multiplier, first-order masked. Computes (a_q ^ b_q) = (a_x ^ b_x) * (a_y ^ b_y), i.e. q = x * y using first-order domain-oriented masking. The sharings of x and y are required to be uniformly random and independent from each other. See Fig. 2 in 1.
| Name | Type | Default Value | Description |
|---|---|---|---|
| NPower | int | 4 | |
| Pipeline | bit | 1'b0 |
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| we_i | in | logic | |
| a_x | in | [NPower-1:0] logic | Share a of x |
| a_y | in | [NPower-1:0] logic | Share a of y |
| b_x | in | [NPower-1:0] logic | Share b of x |
| b_y | in | [NPower-1:0] logic | Share b of y |
| z_0 | in | [NPower-1:0] logic | Randomness for resharing |
| a_q | out | [NPower-1:0] logic | Share a of q |
| b_q | out | [NPower-1:0] logic | Share b of q |
This design unit is implemented in aes_sbox_dom.sv
This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv
Inverse in GF(2^4) using first-order domain-oriented masking and normal basis z^4, z. See Fig. 6 in 2 (grey block, Stages 2 and 3) and Formulas 6, 13, 14, 15, 16, 17 in 2.
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| we_i | in | [1:0] logic | |
| a_gamma | in | [3:0] logic | |
| b_gamma | in | [3:0] logic | |
| prd_2 | in | [3:0] logic | |
| prd_3 | in | [7:0] logic | |
| a_gamma_inv | out | [3:0] logic | |
| b_gamma_inv | out | [3:0] logic |
This design unit is implemented in aes_sbox_dom.sv
This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv
Inverse in GF(2^8) using first-order domain-oriented masking and normal basis y^16, y. See Fig. 6 in 1 and Formulas 3, 12, 18 and 19 in 2.
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| we_i | in | [3:0] logic | |
| a_y | in | [7:0] logic | input data masked by b_y |
| b_y | in | [7:0] logic | input mask |
| prd | in | prd_t | pseudo-random data, e.g. for intermediate masks |
| a_y_inv | out | [7:0] logic | output data masked by b_y_inv |
| b_y_inv | out | [7:0] logic | output mask |
a_gamma is masked by b_gamma, a_gamma_inv is masked by b_gamma_inv.
This design unit is implemented in aes_sbox_canright_masked.sv
This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv
Masked inverse in GF(2^4), using normal basis z^4, z (see Formulas 6, 13, 14, 15, 21, 22, 23, 24 in the paper)
| Name | Direction | Type | Description |
|---|---|---|---|
| b | in | [3:0] logic | |
| q | in | [3:0] logic | |
| r | in | [1:0] logic | |
| m1 | in | [3:0] logic | |
| b_inv | out | [3:0] logic |
This design unit is implemented in aes_sbox_canright_masked_noreuse.sv
This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv
Masked inverse in GF(2^4), using normal basis z^4, z (see Formulas 6, 13, 14, 15, 16, 17 in the paper)
| Name | Direction | Type | Description |
|---|---|---|---|
| b | in | [3:0] logic | |
| q | in | [3:0] logic | |
| r | in | [1:0] logic | |
| t | in | [3:0] logic | |
| b_inv | out | [3:0] logic |
This design unit is implemented in aes_sbox_canright_masked.sv
This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv
Masked inverse in GF(2^8), using normal basis y^16, y (see Formulas 3, 12, 25, 26 and 27 in the paper)
| Name | Direction | Type | Description |
|---|---|---|---|
| a | in | [7:0] logic | |
| m | in | [7:0] logic | |
| n | in | [7:0] logic | |
| a_inv | out | [7:0] logic |
b is masked by q, b_inv is masked by m1.
This design unit is implemented in aes_sbox_canright_masked_noreuse.sv
This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv
Masked inverse in GF(2^8), using normal basis y^16, y (see Formulas 3, 12, 18 and 19 in the paper)
| Name | Direction | Type | Description |
|---|---|---|---|
| a | in | [7:0] logic | input data masked by m |
| m | in | [7:0] logic | input mask |
| n | in | [7:0] logic | output mask |
| prd | in | [9:0] logic | pseudo-random data, e.g. for intermediate masks |
| a_inv | out | [7:0] logic | output data masked by n |
b is masked by q, b_inv is masked by t.
This design unit is implemented in aes_sbox_canright.sv
This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| op_i | in | ciph_op_e | |
| data_i | in | [7:0] logic | |
| data_o | out | [7:0] logic |
This design unit is implemented in aes_sbox_canright_masked.sv
This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| op_i | in | ciph_op_e | |
| data_i | in | [7:0] logic | masked, the actual input data is data_i ^ mask_i |
| mask_i | in | [7:0] logic | input mask, independent from actual input data |
| prd_i | in | [7:0] logic | pseudo-random data for remasking, independent of input mask |
| data_o | out | [7:0] logic | masked, the actual output data is data_o ^ mask_o |
| mask_o | out | [7:0] logic | output mask |
Do the inversion in normal basis X.
This design unit is implemented in aes_sbox_canright_masked_noreuse.sv
This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| op_i | in | ciph_op_e | |
| data_i | in | [7:0] logic | masked, the actual input data is data_i ^ mask_i |
| mask_i | in | [7:0] logic | input mask, independent from actual input data |
| prd_i | in | [17:0] logic | pseudo-random data, for remasking and for intermediate masks, must be independent of input mask |
| data_o | out | [7:0] logic | masked, the actual output data is data_o ^ mask_o |
| mask_o | out | [7:0] logic | output mask |
Do the inversion in normal basis X.
This design unit is implemented in aes_sbox_dom.sv
This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv
| Name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | logic | |
| rst_ni | in | logic | |
| en_i | in | logic | |
| out_req_o | out | logic | |
| out_ack_i | in | logic | |
| op_i | in | ciph_op_e | |
| data_i | in | [7:0] logic | masked, the actual input data is data_i ^ mask_i |
| mask_i | in | [7:0] logic | input mask |
| prd_i | in | [7:0] logic | pseudo-random data for remasking, in total we need 28 bits of PRD per evaluation, but at most 8 bits per cycle |
| data_o | out | [7:0] logic | masked, the actual output data is data_o ^ mask_o |
| mask_o | out | [7:0] logic | output mask |
Do the inversion in normal basis X.
This design unit is implemented in aes_sbox_lut.sv
This file depends on: aes_pkg.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
| SBOX_FWD | [7:0] logic [256] | '{ 8'h63, 8'h7C, 8'h77, 8'h7B, 8'hF2, 8'h6B, 8'h6F, 8'hC5, 8'h30, 8'h01, 8'h67, 8'h2B, 8'hFE, 8'hD7, 8'hAB, 8'h76, 8'hCA, 8'h82, 8'hC9, 8'h7D, 8'hFA, 8'h59, 8'h47, 8'hF0, 8'hAD, 8'hD4, 8'hA2, 8'hAF, 8'h9C, 8'hA4, 8'h72, 8'hC0, 8'hB7, 8'hFD, 8'h93, 8'h26, 8'h36, 8'h3F, 8'hF7, 8'hCC, 8'h34, 8'hA5, 8'hE5, 8'hF1, 8'h71, 8'hD8, 8'h31, 8'h15, 8'h04, 8'hC7, 8'h23, 8'hC3, 8'h18, 8'h96, 8'h05, 8'h9A, 8'h07, 8'h12, 8'h80, 8'hE2, 8'hEB, 8'h27, 8'hB2, 8'h75, 8'h09, 8'h83, 8'h2C, 8'h1A, 8'h1B, 8'h6E, 8'h5A, 8'hA0, 8'h52, 8'h3B, 8'hD6, 8'hB3, 8'h29, 8'hE3, 8'h2F, 8'h84, 8'h53, 8'hD1, 8'h00, 8'hED, 8'h20, 8'hFC, 8'hB1, 8'h5B, 8'h6A, 8'hCB, 8'hBE, 8'h39, 8'h4A, 8'h4C, 8'h58, 8'hCF, 8'hD0, 8'hEF, 8'hAA, 8'hFB, 8'h43, 8'h4D, 8'h33, 8'h85, 8'h45, 8'hF9, 8'h02, 8'h7F, 8'h50, 8'h3C, 8'h9F, 8'hA8, 8'h51, 8'hA3, 8'h40, 8'h8F, 8'h92, 8'h9D, 8'h38, 8'hF5, 8'hBC, 8'hB6, 8'hDA, 8'h21, 8'h10, 8'hFF, 8'hF3, 8'hD2, 8'hCD, 8'h0C, 8'h13, 8'hEC, 8'h5F, 8'h97, 8'h44, 8'h17, 8'hC4, 8'hA7, 8'h7E, 8'h3D, 8'h64, 8'h5D, 8'h19, 8'h73, 8'h60, 8'h81, 8'h4F, 8'hDC, 8'h22, 8'h2A, 8'h90, 8'h88, 8'h46, 8'hEE, 8'hB8, 8'h14, 8'hDE, 8'h5E, 8'h0B, 8'hDB, 8'hE0, 8'h32, 8'h3A, 8'h0A, 8'h49, 8'h06, 8'h24, 8'h5C, 8'hC2, 8'hD3, 8'hAC, 8'h62, 8'h91, 8'h95, 8'hE4, 8'h79, 8'hE7, 8'hC8, 8'h37, 8'h6D, 8'h8D, 8'hD5, 8'h4E, 8'hA9, 8'h6C, 8'h56, 8'hF4, 8'hEA, 8'h65, 8'h7A, 8'hAE, 8'h08, 8'hBA, 8'h78, 8'h25, 8'h2E, 8'h1C, 8'hA6, 8'hB4, 8'hC6, 8'hE8, 8'hDD, 8'h74, 8'h1F, 8'h4B, 8'hBD, 8'h8B, 8'h8A, 8'h70, 8'h3E, 8'hB5, 8'h66, 8'h48, 8'h03, 8'hF6, 8'h0E, 8'h61, 8'h35, 8'h57, 8'hB9, 8'h86, 8'hC1, 8'h1D, 8'h9E, 8'hE1, 8'hF8, 8'h98, 8'h11, 8'h69, 8'hD9, 8'h8E, 8'h94, 8'h9B, 8'h1E, 8'h87, 8'hE9, 8'hCE, 8'h55, 8'h28, 8'hDF, 8'h8C, 8'hA1, 8'h89, 8'h0D, 8'hBF, 8'hE6, 8'h42, 8'h68, 8'h41, 8'h99, 8'h2D, 8'h0F, 8'hB0, 8'h54, 8'hBB, 8'h16 } | Define the LUTs |
| SBOX_INV | [7:0] logic [256] | '{ 8'h52, 8'h09, 8'h6a, 8'hd5, 8'h30, 8'h36, 8'ha5, 8'h38, 8'hbf, 8'h40, 8'ha3, 8'h9e, 8'h81, 8'hf3, 8'hd7, 8'hfb, 8'h7c, 8'he3, 8'h39, 8'h82, 8'h9b, 8'h2f, 8'hff, 8'h87, 8'h34, 8'h8e, 8'h43, 8'h44, 8'hc4, 8'hde, 8'he9, 8'hcb, 8'h54, 8'h7b, 8'h94, 8'h32, 8'ha6, 8'hc2, 8'h23, 8'h3d, 8'hee, 8'h4c, 8'h95, 8'h0b, 8'h42, 8'hfa, 8'hc3, 8'h4e, 8'h08, 8'h2e, 8'ha1, 8'h66, 8'h28, 8'hd9, 8'h24, 8'hb2, 8'h76, 8'h5b, 8'ha2, 8'h49, 8'h6d, 8'h8b, 8'hd1, 8'h25, 8'h72, 8'hf8, 8'hf6, 8'h64, 8'h86, 8'h68, 8'h98, 8'h16, 8'hd4, 8'ha4, 8'h5c, 8'hcc, 8'h5d, 8'h65, 8'hb6, 8'h92, 8'h6c, 8'h70, 8'h48, 8'h50, 8'hfd, 8'hed, 8'hb9, 8'hda, 8'h5e, 8'h15, 8'h46, 8'h57, 8'ha7, 8'h8d, 8'h9d, 8'h84, 8'h90, 8'hd8, 8'hab, 8'h00, 8'h8c, 8'hbc, 8'hd3, 8'h0a, 8'hf7, 8'he4, 8'h58, 8'h05, 8'hb8, 8'hb3, 8'h45, 8'h06, 8'hd0, 8'h2c, 8'h1e, 8'h8f, 8'hca, 8'h3f, 8'h0f, 8'h02, 8'hc1, 8'haf, 8'hbd, 8'h03, 8'h01, 8'h13, 8'h8a, 8'h6b, 8'h3a, 8'h91, 8'h11, 8'h41, 8'h4f, 8'h67, 8'hdc, 8'hea, 8'h97, 8'hf2, 8'hcf, 8'hce, 8'hf0, 8'hb4, 8'he6, 8'h73, 8'h96, 8'hac, 8'h74, 8'h22, 8'he7, 8'had, 8'h35, 8'h85, 8'he2, 8'hf9, 8'h37, 8'he8, 8'h1c, 8'h75, 8'hdf, 8'h6e, 8'h47, 8'hf1, 8'h1a, 8'h71, 8'h1d, 8'h29, 8'hc5, 8'h89, 8'h6f, 8'hb7, 8'h62, 8'h0e, 8'haa, 8'h18, 8'hbe, 8'h1b, 8'hfc, 8'h56, 8'h3e, 8'h4b, 8'hc6, 8'hd2, 8'h79, 8'h20, 8'h9a, 8'hdb, 8'hc0, 8'hfe, 8'h78, 8'hcd, 8'h5a, 8'hf4, 8'h1f, 8'hdd, 8'ha8, 8'h33, 8'h88, 8'h07, 8'hc7, 8'h31, 8'hb1, 8'h12, 8'h10, 8'h59, 8'h27, 8'h80, 8'hec, 8'h5f, 8'h60, 8'h51, 8'h7f, 8'ha9, 8'h19, 8'hb5, 8'h4a, 8'h0d, 8'h2d, 8'he5, 8'h7a, 8'h9f, 8'h93, 8'hc9, 8'h9c, 8'hef, 8'ha0, 8'he0, 8'h3b, 8'h4d, 8'hae, 8'h2a, 8'hf5, 8'hb0, 8'hc8, 8'heb, 8'hbb, 8'h3c, 8'h83, 8'h53, 8'h99, 8'h61, 8'h17, 8'h2b, 8'h04, 8'h7e, 8'hba, 8'h77, 8'hd6, 8'h26, 8'he1, 8'h69, 8'h14, 8'h63, 8'h55, 8'h21, 8'h0c, 8'h7d } |
| Name | Direction | Type | Description |
|---|---|---|---|
| op_i | in | ciph_op_e | |
| data_i | in | [7:0] logic | |
| data_o | out | [7:0] logic |
This design unit is implemented in aes_sbox_canright_pkg.sv