Documentation for project OpenTitanRev2

Generated by Sigasi 4.13.0.qualifier

Revision 2021-06-08

Table of Contents

Design Units

This projects has 449 design units.

Module top​_earlgrey​_asic

This design unit is implemented in top​_earlgrey​_asic.sv

This file depends on: pinmux_reg_pkg.sv, entropy_src_pkg.sv, ast.sv, top_pkg.sv, clkmgr_pkg.sv, sensor_ctrl_reg_pkg.sv, jtag_mux.sv, otp_ctrl_pkg.sv, top_earlgrey_pkg.sv, tlul_pkg.sv, prim_usb_diff_rx.sv, pwrmgr_pkg.sv, top_earlgrey.sv, ast_pkg.sv, rstmgr_pkg.sv, padring.sv, edn_pkg.sv, aes_pkg.sv, lc_ctrl_pkg.sv

Parameters

NameTypeDefault ValueDescription
NumIOsintpinmux_reg_pkg::NMioPads + pinmux_reg_pkg::NDioPads
TieOffValues[NumIOs-1:0] logicNumIOs'(1'b1 << ( pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb))

This specifies the tie-off values of the muxed MIO/DIOs when the JTAG is active. SPI CSB is active low.

Ports

NameDirectionTypeDescription
POR​_Ninoutlogic

Clock and Reset

SPI​_HOST​_D0inoutlogic

Bank A (VIOA domain)

SPI​_HOST​_D1inoutlogic
SPI​_HOST​_D2inoutlogic
SPI​_HOST​_D3inoutlogic
SPI​_HOST​_CLKinoutlogic
SPI​_HOST​_CS​_Linoutlogic
SPI​_DEV​_D0inoutlogic
SPI​_DEV​_D1inoutlogic
SPI​_DEV​_D2inoutlogic
SPI​_DEV​_D3inoutlogic
SPI​_DEV​_CLKinoutlogic
SPI​_DEV​_CS​_Linoutlogic
IOA0inoutlogic

MIO 0

IOA1inoutlogic

MIO 1

IOA2inoutlogic

MIO 2

IOA3inoutlogic

MIO 3

IOA4inoutlogic

MIO 4

IOA5inoutlogic

MIO 5

IOB0inoutlogic

MIO 6

IOB1inoutlogic

MIO 7

IOB2inoutlogic

MIO 8

IOB3inoutlogic

MIO 9

IOB4inoutlogic

MIO 10

IOB5inoutlogic

MIO 11

IOB6inoutlogic

MIO 12

IOB7inoutlogic

MIO 13

IOB8inoutlogic

MIO 14

IOB9inoutlogic

MIO 15

IOB10inoutlogic

MIO 16

IOB11inoutlogic

MIO 17

IOC0inoutlogic

MIO 18

IOC1inoutlogic

MIO 19

IOC2inoutlogic

MIO 20

IOC3inoutlogic

MIO 21

IOC4inoutlogic

MIO 22

IOC5inoutlogic

MIO 23

IOC6inoutlogic

MIO 24

IOC7inoutlogic

MIO 25

IOC8inoutlogic

MIO 26

IOC9inoutlogic

MIO 27

IOC10inoutlogic

MIO 28

IOC11inoutlogic

MIO 29

IOR0inoutlogic

MIO 30

IOR1inoutlogic

MIO 31

IOR2inoutlogic

MIO 32

IOR3inoutlogic

MIO 33

IOR4inoutlogic

MIO 34

IOR5inoutlogic

MIO 35

IOR6inoutlogic

MIO 36

IOR7inoutlogic

MIO 37

IOR8inoutlogic

MIO 38

IOR9inoutlogic

MIO 39

IOR10inoutlogic

MIO 40

IOR11inoutlogic

MIO 41

IOR12inoutlogic

MIO 42

IOR13inoutlogic

MIO 43

CC1inoutlogic

DCD (VCC domain)

CC2inoutlogic
USB​_Pinoutlogic

USB (VCC domain)

USB​_Ninoutlogic
FLASH​_TEST​_MODEinout[3:0] logic

FLASH

FLASH​_TEST​_VOLTinoutlogic

Instantiations

Block Diagram

Package aes​_pkg

This design unit is implemented in aes​_pkg.sv

Module ast

This design unit is implemented in ast.sv

This file depends on: adc.sv, io_clk.sv, uvm_pkg.sv, rglts_pdm_3p3v.sv, pinmux_pkg.sv, aon_clk.sv, tlul_pkg.sv, rng.sv, entropy.sv, usb_clk.sv, ana_pkg.sv, ast_pkg.sv, gen_pok.sv, ast_reg_top.sv, edn_pkg.sv, sys_clk.sv, alert.sv, lc_ctrl_pkg.sv, ast_reg_pkg.sv

Parameters

NameTypeDefault ValueDescription
AdcChannelsint2
AdcDataWidthint10
EntropyStreamsint4
Ast2PadOutWidthint16

TODO:final size

Pad2AstInWidthint16

TODO:final size

UsbCalibWidthint16

TODO:final size

EntropyRateWidthint4

Entropy (Always ON)

Ports

NameDirectionTypeDescription
tl​_iintl_h2d_t

TLUL H2D

tl​_oouttl_d2h_t

TLUL D2H

clk​_ast​_adc​_iinlogic

Buffered AST ADC Clock

rst​_ast​_adc​_niinlogic

Buffered AST ADC Reset

clk​_ast​_alert​_iinlogic

Buffered AST Alert Clock

rst​_ast​_alert​_niinlogic

Buffered AST Alert Reset

clk​_ast​_es​_iinlogic

Buffered AST Entropy Source Clock

rst​_ast​_es​_niinlogic

Buffered AST Entropy Source Reset

clk​_ast​_rng​_iinlogic

Buffered AST RNG Clock

rst​_ast​_rng​_niinlogic

Buffered AST RNG Reset

clk​_ast​_tlul​_iinlogic

Buffered AST TLUL Clock

rst​_ast​_tlul​_niinlogic

Buffered AST TLUL Reset

clk​_ast​_usb​_iinlogic

Buffered AST USB Clock

rst​_ast​_usb​_niinlogic

Buffered AST USB Reset

clk​_ast​_ext​_iinlogic

Buffered AST External Clock

por​_niinlogic

Power ON Reset

vcc​_supp​_iinlogic

VCC Supply Test for OS FPGA

vcaon​_supp​_iinlogic

VCAON Supply Test for OS FPGA

vcmain​_supp​_iinlogic

VCMAIN Supply Test for OS FPGA

vioa​_supp​_iinlogic

VIOA Rail Supply Test for OS FPGA

viob​_supp​_iinlogic

VIOB Rail Supply Test for OS FPGA

vcaon​_pok​_ooutlogic

VCAON Power OK

vcmain​_pok​_ooutlogic

VCMAIN Power OK

vioa​_pok​_ooutlogic

VIOA Rail Power OK

viob​_pok​_ooutlogic

VIOB Rail Power OK

main​_pd​_niinlogic

MAIN Regulator Power Down

main​_iso​_en​_iinlogic

Isolation enable for main core power (VCMAIN).

flash​_power​_down​_h​_ooutlogic

Flash Power Down

flash​_power​_ready​_h​_ooutlogic

Flash Power Ready

otp​_power​_seq​_iin[1:0] logic

MMR0,24 in (VDD)

otp​_power​_seq​_h​_oout[1:0] logic

MMR0,24 masked by PDM, out (VCC)

clk​_src​_sys​_en​_iinlogic

SYS Source Clock Enable

clk​_src​_sys​_jen​_iinlogic

SYS Source Clock Jitter Enable

clk​_src​_sys​_ooutlogic

SYS Source Clock

clk​_src​_sys​_val​_ooutlogic

SYS Source Clock Valid

clk​_src​_aon​_ooutlogic

AON Source Clock

clk​_src​_aon​_val​_ooutlogic

AON Source Clock Valid

clk​_src​_io​_en​_iinlogic

IO Source Clock Enable

clk​_src​_io​_ooutlogic

IO Source Clock

clk​_src​_io​_val​_ooutlogic

IO Source Clock Valid

usb​_ref​_pulse​_iinlogic

USB Reference Pulse

usb​_ref​_val​_iinlogic

USB Reference Valid

clk​_src​_usb​_en​_iinlogic

USB Source Clock Enable

clk​_src​_usb​_ooutlogic

USB Source Clock

clk​_src​_usb​_val​_ooutlogic

USB Source Clock Valid

usb​_io​_pu​_cal​_oout[UsbCalibWidth-1:0] logic

USB IO Pull-up Calibration Setting

adc​_pd​_iinlogic

ADC Power Down

adc​_a0​_aiinlogic

ADC A0 Analog Input

adc​_a1​_aiinlogic

ADC A1 Analog Input

adc​_chnsel​_iin[AdcChannels-1:0] logic

ADC Channel Select

adc​_d​_oout[AdcDataWidth-1:0] logic

ADC Digital (per channel)

adc​_d​_val​_ooutlogic

ADC Digital Valid

rng​_en​_iinlogic

RNG Enable

rng​_val​_ooutlogic

RNG Valid

rng​_b​_oout[EntropyStreams-1:0] logic

RNG Bit(s)

entropy​_rsp​_iinedn_rsp_t

Entropy Response

entropy​_req​_ooutedn_req_t

Entropy Request

as​_alert​_trig​_iinast_dif_t

Active Shield Alert Trigger

as​_alert​_ack​_iinast_dif_t

Active Shield Alert Acknowledge

as​_alert​_ooutast_dif_t

Active Shield Alert

cg​_alert​_trig​_iinast_dif_t

Clock Glitch Alert Trigger

cg​_alert​_ack​_iinast_dif_t

Clock Glitch Alert Acknowledge

cg​_alert​_ooutast_dif_t

Clock Glitch Alert

gd​_alert​_trig​_iinast_dif_t

Glitch Detect Alert Trigger

gd​_alert​_ack​_iinast_dif_t

Glitch Detect Alert Acknowledge

gd​_alert​_ooutast_dif_t

Glitch Detect Alert

ts​_alert​_hi​_trig​_iinast_dif_t

Temp Sense High Alert Trigger

ts​_alert​_hi​_ack​_iinast_dif_t

Temp Sense High Alert Acknowledge

ts​_alert​_hi​_ooutast_dif_t

Temp Sense High Alert Positive

ts​_alert​_lo​_trig​_iinast_dif_t

Temp Sense Low Alert Trigger

ts​_alert​_lo​_ack​_iinast_dif_t

Temp Sense Low Alert Acknowledge

ts​_alert​_lo​_ooutast_dif_t

Temp Sense Low Alert

ls​_alert​_trig​_iinast_dif_t

Light Sense Alert Trigger

ls​_alert​_ack​_iinast_dif_t

Light Sense Alert Acknowledge

ls​_alert​_ooutast_dif_t

Light Sense Alert

ot​_alert​_trig​_iinast_dif_t

OTher Alert Trigger

ot​_alert​_ack​_iinast_dif_t

OTher Alert Acknowledge

ot​_alert​_ooutast_dif_t

OTher Alert

dft​_strap​_test​_iindft_strap_test_req_t

DFT Straps

lc​_dft​_en​_iinlc_tx_t

DFT enable (secure bus)

padmux2ast​_iin[Pad2AstInWidth-1:0] logic

IO_2_DFT Input Signals

ast2padmux​_oout[Ast2PadOutWidth-1:0] logic

DFT_2_IO Output Signals

pad2ast​_t0​_aiinlogic

PAD_2_AST Analog T0 Input Signal

pad2ast​_t1​_aiinlogic

PAD_2_AST Analog T1 Input Signal

ast2pad​_t0​_aooutlogic

AST_2_PAD Analog T0 Output Signal

ast2pad​_t1​_aooutlogic

AST_2_PAD Analog T1 Output Signal

lc​_clk​_byp​_req​_iinlc_tx_t

External clock mux override for OTP bootstrap

lc​_clk​_byp​_ack​_ooutlc_tx_t

Switch clocks to External clock

flash​_bist​_en​_ooutlc_tx_t

Flush BIST (TAP) Enable

dpram​_rmf​_ooutdpm_rm_t

Dual Port RAM Read-write Margin Fast

dpram​_rml​_ooutdpm_rm_t

Dual Port RAM Read-write Margin sLow

spram​_rm​_ooutspm_rm_t

Single Port RAM Read-write Margin

sprgf​_rm​_ooutspm_rm_t

Single Port Reg-File Read-write Margin

sprom​_rm​_ooutspm_rm_t

Single Port ROM Read-write Margin

dft​_scan​_md​_ooutlc_tx_t

Scan Mode output

scan​_shift​_en​_ooutlogic

Scan Shift Enable output

scan​_reset​_nooutlogic

Scan Reset output

Instantiations

Block Diagram

Package ast​_pkg

This design unit is implemented in ast​_pkg.sv

This file depends on: top_pkg.sv

Description

of ast_pkg

Package clkmgr​_pkg

This design unit is implemented in clkmgr​_pkg.sv

Description

clkmgr_pkg

Package edn​_pkg

This design unit is implemented in edn​_pkg.sv

This file depends on: entropy_src_pkg.sv

Package entropy​_src​_pkg

This design unit is implemented in entropy​_src​_pkg.sv

Module jtag​_mux

This design unit is implemented in jtag​_mux.sv

This file depends on: uvm_pkg.sv

Parameters

NameTypeDefault ValueDescription
NumIOsint32
TieOffValues[NumIOs-1:0] logic'0
JtagEnIdxint0

Pin to enable JTAG. This is only sampled but not fully muxed.

JtagEnPolaritybit1'b1
TckIdxint0

These signals are fully muxed and tied off if not in use.

TmsIdxint0
TrstIdxint0
SrstIdxint0
TdiIdxint0
TdoIdxint0
UsbDpPuIdxint0

Indices for USB breakout (this is a Bronze workaround)

UsbDnPuIdxint0
UsbDIdxint0
ConnectUSBbit0

Ports

NameDirectionTypeDescription
jtag​_tck​_ooutlogic

To JTAG inside core

jtag​_tms​_ooutlogic
jtag​_trst​_nooutlogic
jtag​_srst​_nooutlogic
jtag​_tdi​_ooutlogic
jtag​_tdo​_iinlogic
out​_core​_iin[NumIOs-1:0] logic

To core side

oe​_core​_iin[NumIOs-1:0] logic
in​_core​_oout[NumIOs-1:0] logic
out​_padring​_oout[NumIOs-1:0] logic

To padring side

oe​_padring​_oout[NumIOs-1:0] logic
in​_padring​_iin[NumIOs-1:0] logic
usb​_pullup​_p​_en​_ooutlogic

USB breakouts for bronze

usb​_pullup​_n​_en​_ooutlogic
usb​_diff​_input​_iinlogic

Block Diagram

Package lc​_ctrl​_pkg

This design unit is implemented in lc​_ctrl​_pkg.sv

This file depends on: lc_ctrl_state_pkg.sv, prim_util_pkg.sv

Package otp​_ctrl​_pkg

This design unit is implemented in otp​_ctrl​_pkg.sv

This file depends on: lc_ctrl_state_pkg.sv, prim_util_pkg.sv, otp_ctrl_reg_pkg.sv

Module padring

This design unit is implemented in padring.sv

This file depends on: pinmux_reg_pkg.sv, prim_pad_wrapper.sv

Parameters

NameTypeDefault ValueDescription
ConnectClkbit1

This allows to selectively connect Pad instances. unconnected inputs are tied to 0, unconnected outputs are high-z.

ConnectRstbit1
ConnectCc[1:0] bit'1
ConnectMioIn[NMioPads-1:0] bit'1
ConnectMioOut[NMioPads-1:0] bit'1
ConnectDioIn[NDioPads-1:0] bit'1
ConnectDioOut[NDioPads-1:0] bit'1
MioPadVariant[1:0] [NMioPads-1:0] bit'0

0: bidir, 1: input, 2: tolerant, 3: open drain

DioPadVariant[1:0] [NDioPads-1:0] bit'0

Ports

NameDirectionTypeDescription
clk​_pad​_iinlogic

pad input

rst​_pad​_niinlogic
clk​_ooutlogic

to clocking/reset infrastructure

rst​_nooutlogic
cc1​_iinlogic

pads for dcd.

cc2​_iinlogic
mio​_pad​_ioinout[NMioPads-1:0] logic

pads

dio​_pad​_ioinout[NDioPads-1:0] logic
mio​_in​_oout[NMioPads-1:0] logic

muxed IO signals coming from pinmux

mio​_out​_iin[NMioPads-1:0] logic
mio​_oe​_iin[NMioPads-1:0] logic
dio​_in​_oout[NDioPads-1:0] logic

dedicated IO signals coming from peripherals

dio​_out​_iin[NDioPads-1:0] logic
dio​_oe​_iin[NDioPads-1:0] logic
mio​_attr​_iin[AttrDw-1:0] [NMioPads-1:0] logic

pad attributes from top level instance

dio​_attr​_iin[AttrDw-1:0] [NDioPads-1:0] logic

Block Diagram

Package pinmux​_reg​_pkg

This design unit is implemented in pinmux​_reg​_pkg.sv

Module prim​_usb​_diff​_rx

This design unit is implemented in prim​_usb​_diff​_rx.sv

This file depends on: prim_generic_usb_diff_rx.sv

Description

This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

Parameters

NameTypeDefault ValueDescription
CalibWint32

Ports

NameDirectionTypeDescription
input​_piinlogic

differential input

input​_niinlogic

differential input

input​_en​_iinlogic

input buffer enable

core​_pok​_iinlogic

core power indication at VCC level

pullup​_p​_en​_iinlogic

pullup enable for P

pullup​_n​_en​_iinlogic

pullup enable for N

calibration​_iin[CalibW-1:0] logic

calibration input

input​_ooutlogic

output of differential input buffer

Block Diagram

Package pwrmgr​_pkg

This design unit is implemented in pwrmgr​_pkg.sv

This file depends on: pwrmgr_reg_pkg.sv

Description

pwrmgr_pkg

Package rstmgr​_pkg

This design unit is implemented in rstmgr​_pkg.sv

Description

rstmgr_pkg

Package sensor​_ctrl​_reg​_pkg

This design unit is implemented in sensor​_ctrl​_reg​_pkg.sv

Package tlul​_pkg

This design unit is implemented in tlul​_pkg.sv

This file depends on: top_pkg.sv

Module top​_earlgrey

This design unit is implemented in top​_earlgrey.sv

This file depends on: usbdev_pkg.sv, csrng.sv, uvm_pkg.sv, otp_ctrl_pkg.sv, flash_ctrl.sv, tlul_pkg.sv, otp_ctrl.sv, flash_phy.sv, aon_timer.sv, ibex_pkg.sv, rv_core_ibex.sv, keymgr_pkg.sv, rstmgr.sv, clkmgr.sv, dm_pkg.sv, gpio.sv, rv_core_ibex_pkg.sv, tl_main_pkg.sv, otp_ctrl_part_pkg.sv, rv_dm.sv, xbar_main.sv, prim_ram_1p_scr.sv, tlul_adapter_sram.sv, pwrmgr.sv, xbar_peri.sv, aes.sv, keymgr.sv, edn.sv, aes_pkg.sv, edn_pkg.sv, alert_handler.sv, otbn_pkg.sv, pinmux_reg_pkg.sv, entropy_src_pkg.sv, csrng_pkg.sv, jtag_pkg.sv, uart.sv, usbdev.sv, alert_pkg.sv, pinmux.sv, pwrmgr_pkg.sv, prim_rom_adv.sv, otbn.sv, sensor_ctrl.sv, kmac.sv, rstmgr_pkg.sv, spi_device.sv, top_earlgrey_rnd_cnst_pkg.sv, entropy_src.sv, lc_ctrl_pkg.sv, rv_plic.sv, hmac.sv, prim_esc_pkg.sv, aes_reg_pkg.sv, sram_ctrl_pkg.sv, top_pkg.sv, clkmgr_pkg.sv, spi_host.sv, pattgen.sv, ast_pkg.sv, i2c.sv, rv_timer.sv, flash_ctrl_pkg.sv, prim_alert_pkg.sv, sram_ctrl.sv, lc_ctrl.sv

Parameters

NameTypeDefault ValueDescription
SramCtrlRetAonInstrExecbit1

Auto-inferred parameters

AesMaskingbit1'b1
AesSBoxImplsbox_impl_eaes_pkg::SBoxImplDom
SecAesStartTriggerDelayint0
SecAesAllowForcingMasksbit1'b0
KmacEnMaskingbit0
KmacReuseShareint0
CsrngSBoxImplsbox_impl_eaes_pkg::SBoxImplCanright
SramCtrlMainInstrExecbit1
OtbnRegFileregfile_eotbn_pkg::RegFileFF
IbexRegFileregfile_eibex_pkg::RegFileFF

Manually defined parameters

IbexICachebit1
IbexPipeLinebit0
BootRomInitFileunknown""
JTAG​_IDCODE[31:0] logic{ 4'h0, 16'h4F54, 11'h426, 1'b1 }

JTAG IDCODE for development versions of this code. Manufacturers of OpenTitan chips must replace this code with one of their own IDs. Field structure as defined in the IEEE 1149.1 (JTAG) specification, section 12.1.1.

Ports

NameDirectionTypeDescription
rst​_niinlogic

Reset, clocks defined as part of intermodule

jtag​_tck​_iinlogic

JTAG interface

jtag​_tms​_iinlogic
jtag​_trst​_niinlogic
jtag​_tdi​_iinlogic
jtag​_tdo​_ooutlogic
mio​_in​_iin[43:0] logic

Multiplexed I/O

mio​_out​_oout[43:0] logic
mio​_oe​_oout[43:0] logic
dio​_in​_iin[20:0] logic

Dedicated I/O

dio​_out​_oout[20:0] logic
dio​_oe​_oout[20:0] logic
mio​_attr​_oout[pinmux_reg_pkg::AttrDw-1:0] [pinmux_reg_pkg::NMioPads-1:0] logic

pad attributes to padring

dio​_attr​_oout[pinmux_reg_pkg::AttrDw-1:0] [pinmux_reg_pkg::NDioPads-1:0] logic
clk​_main​_iinlogic

Inter-module Signal External type

clk​_io​_iinlogic
clk​_usb​_iinlogic
clk​_aon​_iinlogic
clk​_main​_jitter​_en​_ooutlogic
pwrmgr​_ast​_req​_ooutpwr_ast_req_t
pwrmgr​_ast​_rsp​_iinpwr_ast_rsp_t
sensor​_ctrl​_ast​_alert​_req​_iinast_alert_req_t
sensor​_ctrl​_ast​_alert​_rsp​_ooutast_alert_rsp_t
sensor​_ctrl​_ast​_status​_iinast_status_t
usbdev​_usb​_ref​_val​_ooutlogic
usbdev​_usb​_ref​_pulse​_ooutlogic
ast​_tl​_req​_oouttl_h2d_t
ast​_tl​_rsp​_iintl_d2h_t
otp​_ctrl​_otp​_ast​_pwr​_seq​_ooutotp_ast_req_t
otp​_ctrl​_otp​_ast​_pwr​_seq​_h​_iinotp_ast_rsp_t
flash​_bist​_enable​_iinlc_tx_t
flash​_power​_down​_h​_iinlogic
flash​_power​_ready​_h​_iinlogic
flash​_test​_mode​_a​_iin[3:0] logic
flash​_test​_voltage​_h​_iinlogic
es​_rng​_req​_ooutentropy_src_rng_req_t
es​_rng​_rsp​_iinentropy_src_rng_rsp_t
lc​_clk​_byp​_req​_ooutlc_tx_t
lc​_clk​_byp​_ack​_iinlc_tx_t
ast​_edn​_edn​_req​_iinedn_req_t
ast​_edn​_edn​_rsp​_ooutedn_rsp_t
clks​_ast​_ooutclkmgr_ast_out_t
rsts​_ast​_ooutrstmgr_ast_out_t
scan​_rst​_niinlogic

reset used for test mode

scan​_en​_iinlogic
scanmode​_iinlc_tx_t

lc_ctrl_pkg::On for Scan

Instantiations

Block Diagram

Package top​_earlgrey​_pkg

This design unit is implemented in top​_earlgrey​_pkg.sv

Package top​_pkg

This design unit is implemented in top​_pkg.sv

Module adc

This design unit is implemented in adc.sv

This file depends on: ana_pkg.sv, uvm_pkg.sv

Description

of adc

Parameters

NameTypeDefault ValueDescription
AdcCnvtClksint22

JL TODO: Update to actual convertion clock

AdcChannelsint2

ADC number of Channels

AdcDataWidthint10

Ports

NameDirectionTypeDescription
adc​_a0​_aiinlogic

ADC A0 Analog Input

adc​_a1​_aiinlogic

ADC A1 Analog Input

adc​_chnsel​_iin[AdcChannels-1:0] logic

Onehot value only for selection

adc​_pd​_iinlogic

ADC Power Down

clk​_adc​_iinlogic

ADC Clock (aon_clk - 200KHz)

rst​_adc​_niinlogic

ADC Reset active low

adc​_d​_oout[AdcDataWidth-1:0] logic

ADC 10-bit Data Output

adc​_d​_val​_ooutlogic

ADC Data Valid Output

Block Diagram

Module aes

This design unit is implemented in aes.sv

This file depends on: aes_reg_top.sv, uvm_pkg.sv, tlul_pkg.sv, prim_alert_pkg.sv, aes_pkg.sv, prim_alert_sender.sv, aes_core.sv, aes_reg_pkg.sv

Parameters

NameTypeDefault ValueDescription
AES192Enablebit1

Can be 0 (disable), or 1 (enable).

Maskingbit0

Can be 0 (no masking), or 1 (first-order masking) of the cipher core. Masking requires the use of a masked S-Box, see SBoxImpl parameter. Note: currently, constant masks are used, this is of course not secure.

SBoxImplsbox_impl_eSBoxImplLut

See aes_pkg.sv

SecStartTriggerDelayint0

Manual start trigger delay, useful for SCA measurements. A value of e.g. 40 allows the processor to go into sleep before AES starts operation.

SecAllowForcingMasksbit0

Allow forcing masks to 0 using FORCE_ZERO_MASK bit in Control Register. Useful for SCA only.

AlertAsyncOn[NumAlerts-1:0] logic{NumAlerts{1'b1}}
RndCnstClearingLfsrSeedclearing_lfsr_seed_tRndCnstClearingLfsrSeedDefault
RndCnstClearingLfsrPermclearing_lfsr_perm_tRndCnstClearingLfsrPermDefault
RndCnstMaskingLfsrSeedmasking_lfsr_seed_tRndCnstMaskingLfsrSeedDefault
RndCnstMskgChunkLfsrPermmskg_chunk_lfsr_perm_tRndCnstMskgChunkLfsrPermDefault

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
idle​_ooutlogic

Idle indicator for clock manager

tl​_iintl_h2d_t

Bus interface

tl​_oouttl_d2h_t
alert​_rx​_iin[NumAlerts-1:0] alert_rx_t

Alerts

alert​_tx​_oout[NumAlerts-1:0] alert_tx_t

Instantiations

Block Diagram

Package aes​_reg​_pkg

This design unit is implemented in aes​_reg​_pkg.sv

Module alert

This design unit is implemented in alert.sv

This file depends on: ast_pkg.sv

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
alert​_in​_iinast_dif_t
alert​_trig​_iinast_dif_t
alert​_ack​_iinast_dif_t
alert​_req​_ooutast_dif_t

Block Diagram

Module alert​_handler

This design unit is implemented in alert​_handler.sv

This file depends on: prim_esc_sender.sv, uvm_pkg.sv, alert_handler_class.sv, prim_edn_req.sv, alert_pkg.sv, tlul_pkg.sv, alert_handler_accu.sv, prim_alert_receiver.sv, alert_handler_esc_timer.sv, alert_handler_ping_timer.sv, prim_alert_pkg.sv, edn_pkg.sv, alert_handler_reg_wrap.sv, prim_esc_pkg.sv

Parameters

NameTypeDefault ValueDescription
RndCnstLfsrSeedlfsr_seed_tRndCnstLfsrSeedDefault

Compile time random constants, to be overriden by topgen.

RndCnstLfsrPermlfsr_perm_tRndCnstLfsrPermDefault

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
clk​_edn​_iinlogic
rst​_edn​_niinlogic
tl​_iintl_h2d_t

Bus Interface (device)

tl​_oouttl_d2h_t
intr​_classa​_ooutlogic

Interrupt Requests

intr​_classb​_ooutlogic
intr​_classc​_ooutlogic
intr​_classd​_ooutlogic
crashdump​_ooutalert_crashdump_t

State information for HW crashdump

edn​_ooutedn_req_t

Entropy Input

edn​_iinedn_rsp_t
alert​_tx​_iin[NAlerts-1:0] alert_tx_t

Alert Sources

alert​_rx​_oout[NAlerts-1:0] alert_rx_t
esc​_rx​_iin[N_ESC_SEV-1:0] esc_rx_t

Escalation outputs

esc​_tx​_oout[N_ESC_SEV-1:0] esc_tx_t

Instantiations

Block Diagram

Package alert​_pkg

This design unit is implemented in alert​_pkg.sv

This file depends on: alert_handler_reg_pkg.sv

Package ana​_pkg

This design unit is implemented in ana​_pkg.sv

Description

of ana_pkg

Module aon​_clk

This design unit is implemented in aon​_clk.sv

This file depends on: aon_osc.sv

Description

of aon_clk

Parameters

NameTypeDefault ValueDescription
AON​_EN​_RDLYtime5us

Ports

NameDirectionTypeDescription
clk​_src​_aon​_en​_iinlogic

AON Source Clock Enable

clk​_aon​_pd​_niinlogic

AON Clock Power-down

rst​_aon​_clk​_niinlogic

AON Clock Logic reset

vcore​_pok​_h​_iinlogic

VCORE POK @3.3V (for OSC)

clk​_src​_aon​_ooutlogic

AON Source Clock

clk​_src​_aon​_val​_ooutlogic

AON Source Clock Valid

Instantiations

Block Diagram

Module aon​_timer

This design unit is implemented in aon​_timer.sv

This file depends on: aon_timer_reg_pkg.sv, prim_lc_sync.sv, aon_timer_reg_top.sv, aon_timer_core.sv, prim_pulse_sync.sv, prim_intr_hw.sv, tlul_pkg.sv, prim_fifo_async.sv, lc_ctrl_pkg.sv, prim_sync_slow_fast.sv

Parameters

NameTypeDefault ValueDescription
AON​_WKUPint0
AON​_WDOGint1

Ports

NameDirectionTypeDescription
clk​_iinlogic
clk​_aon​_iinlogic
rst​_niinlogic
rst​_aon​_niinlogic
tl​_iintl_h2d_t

TLUL interface on clk_i domain

tl​_oouttl_d2h_t
lc​_escalate​_en​_iinlc_tx_t

clk_i domain

intr​_wkup​_timer​_expired​_ooutlogic
intr​_wdog​_timer​_bark​_ooutlogic
sleep​_mode​_iinlogic

TODO where will this come from?

aon​_timer​_wkup​_req​_ooutlogic
aon​_timer​_rst​_req​_ooutlogic

Instantiations

Block Diagram

Package ast​_reg​_pkg

This design unit is implemented in ast​_reg​_pkg.sv

Module ast​_reg​_top

This design unit is implemented in ast​_reg​_top.sv

This file depends on: prim_subreg.sv, uvm_pkg.sv, tlul_adapter_reg.sv, tlul_pkg.sv, ast_reg_pkg.sv

Parameters

NameTypeDefault ValueDescription
AWint4
DWint32
DBWintDW/8

Byte Width

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Below Regster interface can be changed

tl​_oouttl_d2h_t
reg2hwoutast_reg2hw_t

Write

hw2reginast_hw2reg_t

Read

devmode​_iinlogic

If 1, explicit error return for unmapped register access

Instantiations

Block Diagram

Module clkmgr

This design unit is implemented in clkmgr.sv

This file depends on: uvm_pkg.sv, prim_lc_sync.sv, clkmgr_pkg.sv, tlul_pkg.sv, prim_clock_gating.sv, clkmgr_reg_top.sv, prim_clock_gating_sync.sv, pwrmgr_pkg.sv, prim_lc_sender.sv, prim_flop_2sync.sv, prim_clock_div.sv, clkmgr_reg_pkg.sv, lc_ctrl_pkg.sv, prim_clock_buf.sv

Description

clkmgr

Ports

NameDirectionTypeDescription
clk​_iinlogic

Primary module control clocks and resets This drives the register interface

rst​_niinlogic
clk​_main​_iinlogic

System clocks and resets These are the source clocks for the system

rst​_main​_niinlogic
clk​_io​_iinlogic
rst​_io​_niinlogic
clk​_usb​_iinlogic
rst​_usb​_niinlogic
clk​_aon​_iinlogic
rst​_io​_div2​_niinlogic

Resets for derived clocks clocks are derived locally

rst​_io​_div4​_niinlogic
tl​_iintl_h2d_t

Bus Interface

tl​_oouttl_d2h_t
pwr​_iinpwr_clk_req_t

pwrmgr interface

pwr​_ooutpwr_clk_rsp_t
scanmode​_iinlc_tx_t

dft interface

idle​_iin[3:0] logic

idle hints

ast​_clk​_bypass​_ack​_iinlc_tx_t

clock bypass control

lc​_clk​_bypass​_ack​_ooutlc_tx_t
jitter​_en​_ooutlogic

jittery enable

clocks​_ast​_ooutclkmgr_ast_out_t

clock output interface

clocks​_ooutclkmgr_out_t

Instantiations

Block Diagram

Module csrng

This design unit is implemented in csrng.sv

This file depends on: csrng_pkg.sv, entropy_src_pkg.sv, csrng_reg_top.sv, uvm_pkg.sv, csrng_core.sv, tlul_pkg.sv, prim_alert_pkg.sv, aes_pkg.sv, csrng_reg_pkg.sv, lc_ctrl_pkg.sv, prim_alert_sender.sv

Parameters

NameTypeDefault ValueDescription
SBoxImplsbox_impl_eaes_pkg::SBoxImplLut
AlertAsyncOn[NumAlerts-1:0] logic{NumAlerts{1'b1}}
NHwAppsint2

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Tilelink Bus Interface

tl​_oouttl_d2h_t
efuse​_sw​_app​_enable​_iinlogic

Efuse Interface

lc​_hw​_debug​_en​_iinlc_tx_t

Lifecycle broadcast inputs

entropy​_src​_hw​_if​_ooutentropy_src_hw_if_req_t

Entropy Interface

entropy​_src​_hw​_if​_iinentropy_src_hw_if_rsp_t
csrng​_cmd​_iin[NHwApps-1:0] csrng_req_t

Application Interfaces

csrng​_cmd​_oout[NHwApps-1:0] csrng_rsp_t
alert​_rx​_iin[NumAlerts-1:0] alert_rx_t

Alerts

alert​_tx​_oout[NumAlerts-1:0] alert_tx_t
intr​_cs​_cmd​_req​_done​_ooutlogic

Interrupts

intr​_cs​_entropy​_req​_ooutlogic
intr​_cs​_hw​_inst​_exc​_ooutlogic
intr​_cs​_fatal​_err​_ooutlogic

Instantiations

Block Diagram

Package csrng​_pkg

This design unit is implemented in csrng​_pkg.sv

This file depends on: entropy_src_pkg.sv

Package dm

This design unit is implemented in dm​_pkg.sv

Module edn

This design unit is implemented in edn.sv

This file depends on: csrng_pkg.sv, edn_core.sv, uvm_pkg.sv, edn_reg_top.sv, edn_reg_pkg.sv, tlul_pkg.sv, prim_alert_pkg.sv, edn_pkg.sv, prim_alert_sender.sv

Parameters

NameTypeDefault ValueDescription
NumEndPointsint4
AlertAsyncOn[NumAlerts-1:0] logic{NumAlerts{1'b1}}
BootInsCmdint32'h0000_0001
BootGenCmdint32'h0000_3003

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Tilelink Bus registers

tl​_oouttl_d2h_t
edn​_iin[NumEndPoints-1:0] edn_req_t

EDN interfaces

edn​_oout[NumEndPoints-1:0] edn_rsp_t
csrng​_cmd​_ooutcsrng_req_t

CSRNG Application Interface

csrng​_cmd​_iincsrng_rsp_t
alert​_rx​_iin[NumAlerts-1:0] alert_rx_t

Alerts

alert​_tx​_oout[NumAlerts-1:0] alert_tx_t
intr​_edn​_cmd​_req​_done​_ooutlogic

Interrupts

intr​_edn​_fatal​_err​_ooutlogic

Instantiations

Block Diagram

Module entropy

This design unit is implemented in entropy.sv

This file depends on: prim_generic_flop_2sync.sv, edn_pkg.sv, prim_packer_fifo.sv

Description

of entropy

Parameters

NameTypeDefault ValueDescription
EntropyRateWidthint4

Ports

NameDirectionTypeDescription
entropy​_rsp​_iinedn_rsp_t

Entropy Response

entropy​_rate​_iin[EntropyRateWidth-1:0] logic

Entropy Rate

clk​_ast​_es​_iinlogic

Entropy Clock

rst​_ast​_es​_niinlogic

Entropy Reset

clk​_src​_sys​_en​_iinlogic

System Source Clock Enable

clk​_src​_sys​_jen​_iinlogic

System Source Clock Jitter Enable

entropy​_req​_ooutedn_req_t

Entropy Request

Instantiations

Block Diagram

Module entropy​_src

This design unit is implemented in entropy​_src.sv

This file depends on: entropy_src_pkg.sv, entropy_src_reg_top.sv, uvm_pkg.sv, entropy_src_reg_pkg.sv, tlul_pkg.sv, prim_alert_pkg.sv, prim_alert_sender.sv, entropy_src_core.sv

Parameters

NameTypeDefault ValueDescription
AlertAsyncOn[NumAlerts-1:0] logic{NumAlerts{1'b1}}
EsFifoDepthint2

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Bus Interface

tl​_oouttl_d2h_t
efuse​_es​_sw​_reg​_en​_iinlogic

Efuse Interface

entropy​_src​_hw​_if​_iinentropy_src_hw_if_req_t

Entropy Interface

entropy​_src​_hw​_if​_ooutentropy_src_hw_if_rsp_t
entropy​_src​_rng​_ooutentropy_src_rng_req_t

RNG Interface

entropy​_src​_rng​_iinentropy_src_rng_rsp_t
entropy​_src​_xht​_ooutentropy_src_xht_req_t

External Health Test Interface

entropy​_src​_xht​_iinentropy_src_xht_rsp_t
alert​_rx​_iin[NumAlerts-1:0] alert_rx_t

Alerts

alert​_tx​_oout[NumAlerts-1:0] alert_tx_t
intr​_es​_entropy​_valid​_ooutlogic

Interrupts

intr​_es​_health​_test​_failed​_ooutlogic
intr​_es​_fatal​_err​_ooutlogic

Instantiations

Block Diagram

Module flash​_ctrl

This design unit is implemented in flash​_ctrl.sv

This file depends on: jtag_pkg.sv, uvm_pkg.sv, top_pkg.sv, prim_lc_sync.sv, flash_ctrl_reg_top.sv, prim_lfsr.sv, flash_mp.sv, otp_ctrl_pkg.sv, tlul_pkg.sv, flash_ctrl_rd.sv, prim_alert_sender.sv, pwrmgr_pkg.sv, tlul_adapter_sram.sv, prim_flop.sv, flash_ctrl_erase.sv, flash_ctrl_info_cfg.sv, flash_ctrl_arb.sv, flash_ctrl_prog.sv, flash_ctrl_pkg.sv, prim_fifo_sync.sv, prim_alert_pkg.sv, flash_ctrl_reg_pkg.sv, lc_ctrl_pkg.sv, flash_ctrl_lcmgr.sv

Parameters

NameTypeDefault ValueDescription
AlertAsyncOnlogic1'b1
RndCnstAddrKeyflash_key_tRndCnstAddrKeyDefault
RndCnstDataKeyflash_key_tRndCnstDataKeyDefault
RndCnstLfsrSeedlfsr_seed_tRndCnstLfsrSeedDefault
RndCnstLfsrPermlfsr_perm_tRndCnstLfsrPermDefault
InfoBitsint$bits(info_page_cfg_t) * InfosPerBank

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
clk​_otp​_iinlogic
rst​_otp​_niinlogic
lc​_creator​_seed​_sw​_rw​_en​_iinlc_tx_t

life cycle interface

lc​_owner​_seed​_sw​_rw​_en​_iinlc_tx_t
lc​_iso​_part​_sw​_rd​_en​_iinlc_tx_t
lc​_iso​_part​_sw​_wr​_en​_iinlc_tx_t
lc​_seed​_hw​_rd​_en​_iinlc_tx_t
tl​_iintl_h2d_t

Bus Interface

tl​_oouttl_d2h_t
flash​_iinflash_rsp_t

Flash Interface

flash​_ooutflash_req_t
otp​_ooutflash_otp_key_req_t

otp/lc/pwrmgr/keymgr Interface

otp​_iinflash_otp_key_rsp_t
rma​_req​_iinlc_tx_t
rma​_seed​_iinlc_flash_rma_seed_t
rma​_ack​_ooutlc_tx_t
pwrmgr​_iinpwr_flash_req_t
pwrmgr​_ooutpwr_flash_rsp_t
keymgr​_ooutkeymgr_flash_t
cio​_tck​_iinlogic

IOs

cio​_tms​_iinlogic
cio​_tdi​_iinlogic
cio​_tdo​_en​_ooutlogic
cio​_tdo​_ooutlogic
intr​_prog​_empty​_ooutlogic

Program fifo is empty

intr​_prog​_lvl​_ooutlogic

Program fifo is empty

intr​_rd​_full​_ooutlogic

Read fifo is full

intr​_rd​_lvl​_ooutlogic

Read fifo is full

intr​_op​_done​_ooutlogic

Requested flash operation (wr/erase) done

alert​_rx​_iin[flash_ctrl_reg_pkg::NumAlerts-1:0] alert_rx_t

Alerts

alert​_tx​_oout[flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_t

Instantiations

Block Diagram

Package flash​_ctrl​_pkg

This design unit is implemented in flash​_ctrl​_pkg.sv

This file depends on: jtag_pkg.sv, top_pkg.sv, prim_util_pkg.sv, tlul_pkg.sv, flash_ctrl_reg_pkg.sv, edn_pkg.sv

Module flash​_phy

This design unit is implemented in flash​_phy.sv

This file depends on: jtag_pkg.sv, flash_phy_core.sv, prim_flash.sv, prim_lc_sync.sv, flash_ctrl_pkg.sv, prim_fifo_sync.sv, flash_phy_pkg.sv, flash_ctrl_reg_pkg.sv, lc_ctrl_pkg.sv, flash_mp_data_region_sel.sv

Description

flash_phy

Parameters

NameTypeDefault ValueDescription
FlashMacroOustandingint1

Flash macro outstanding refers to how many reads we allow a macro to move ahead of an in order blocking read. Since the data cannot be returned out of order, this simply does the reads in advance and store them in a FIFO

SeqFifoDepthintFlashMacroOustanding * NumBanks
TotalRegionsintMpRegions + 1

Generate host scramble_en indication, broadcasted to all banks

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
host​_req​_iinlogic
host​_addr​_iin[BusAddrW-1:0] logic
host​_req​_rdy​_ooutlogic
host​_req​_done​_ooutlogic
host​_rdata​_oout[BusWidth-1:0] logic
host​_rderr​_ooutlogic
flash​_ctrl​_iinflash_req_t
flash​_ctrl​_ooutflash_rsp_t
scanmode​_iinlc_tx_t
scan​_en​_iinlogic
scan​_rst​_niinlogic
flash​_power​_ready​_h​_iinlogic
flash​_power​_down​_h​_iinlogic
flash​_test​_mode​_a​_iin[3:0] logic
flash​_test​_voltage​_h​_iinlogic
flash​_bist​_enable​_iinlc_tx_t
lc​_nvm​_debug​_en​_iinlc_tx_t

Instantiations

Block Diagram

Module gen​_pok

This design unit is implemented in gen​_pok.sv

Description

of gen_pok

Parameters

NameTypeDefault ValueDescription
POK​_RDLYtime3us
POK​_FDLYtime500ns

Ports

NameDirectionTypeDescription
gen​_pok​_ooutlogic

Block Diagram

Module gpio

This design unit is implemented in gpio.sv

This file depends on: gpio_reg_pkg.sv, uvm_pkg.sv, gpio_reg_top.sv, prim_intr_hw.sv, tlul_pkg.sv, prim_filter_ctr.sv

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Below Regster interface can be changed

tl​_oouttl_d2h_t
cio​_gpio​_iin[31:0] logic
cio​_gpio​_oout[31:0] logic
cio​_gpio​_en​_oout[31:0] logic
intr​_gpio​_oout[31:0] logic

Instantiations

Block Diagram

Module hmac

This design unit is implemented in hmac.sv

This file depends on: tlul_adapter_sram.sv, hmac_reg_top.sv, uvm_pkg.sv, hmac_pkg.sv, hmac_reg_pkg.sv, prim_intr_hw.sv, prim_fifo_sync.sv, sha2.sv, tlul_pkg.sv, prim_packer.sv, hmac_core.sv

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t
tl​_oouttl_d2h_t
intr​_hmac​_done​_ooutlogic
intr​_fifo​_empty​_ooutlogic
intr​_hmac​_err​_ooutlogic
idle​_ooutlogic

Instantiations

Block Diagram

Module i2c

This design unit is implemented in i2c.sv

This file depends on: i2c_reg_pkg.sv, uvm_pkg.sv, i2c_core.sv, i2c_reg_top.sv, tlul_pkg.sv

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Bus Interface

tl​_oouttl_d2h_t
cio​_scl​_iinlogic

Generic IO

cio​_scl​_ooutlogic
cio​_scl​_en​_ooutlogic
cio​_sda​_iinlogic
cio​_sda​_ooutlogic
cio​_sda​_en​_ooutlogic
intr​_fmt​_watermark​_ooutlogic

Interrupts

intr​_rx​_watermark​_ooutlogic
intr​_fmt​_overflow​_ooutlogic
intr​_rx​_overflow​_ooutlogic
intr​_nak​_ooutlogic
intr​_scl​_interference​_ooutlogic
intr​_sda​_interference​_ooutlogic
intr​_stretch​_timeout​_ooutlogic
intr​_sda​_unstable​_ooutlogic
intr​_trans​_complete​_ooutlogic
intr​_tx​_empty​_ooutlogic
intr​_tx​_nonempty​_ooutlogic
intr​_tx​_overflow​_ooutlogic
intr​_acq​_overflow​_ooutlogic
intr​_ack​_stop​_ooutlogic
intr​_host​_timeout​_ooutlogic

Instantiations

Block Diagram

Package ibex​_pkg

This design unit is implemented in ibex​_pkg.sv

Description

Module io​_clk

This design unit is implemented in io​_clk.sv

This file depends on: io_osc.sv

Description

of io_clk

Parameters

NameTypeDefault ValueDescription
IO​_EN​_RDLYtime5us

Ports

NameDirectionTypeDescription
clk​_src​_io​_en​_iinlogic

IO Source Clock Enable

clk​_io​_pd​_niinlogic

IO Clock Power-down

rst​_io​_clk​_niinlogic

IO Clock Logic reset

vcore​_pok​_h​_iinlogic

VCORE POK @3.3V (for OSC)

clk​_src​_io​_ooutlogic

IO Source Clock

clk​_src​_io​_val​_ooutlogic

IO Source Clock Valid

Instantiations

Block Diagram

Package jtag​_pkg

This design unit is implemented in jtag​_pkg.sv

Module keymgr

This design unit is implemented in keymgr.sv

This file depends on: keymgr_input_checks.sv, keymgr_reseed_ctrl.sv, uvm_pkg.sv, prim_lc_sync.sv, keymgr_reg_pkg.sv, prim_lfsr.sv, otp_ctrl_pkg.sv, keymgr_cfg_en.sv, otp_ctrl_part_pkg.sv, prim_intr_hw.sv, tlul_pkg.sv, prim_alert_sender.sv, keymgr_kmac_if.sv, keymgr_pkg.sv, flash_ctrl_pkg.sv, prim_alert_pkg.sv, keymgr_ctrl.sv, edn_pkg.sv, keymgr_reg_top.sv, lc_ctrl_pkg.sv, keymgr_sideload_key_ctrl.sv

Description

keymgr

Parameters

NameTypeDefault ValueDescription
AlertAsyncOnlogic1'b1
RndCnstLfsrSeedlfsr_seed_tRndCnstLfsrSeedDefault
RndCnstLfsrPermlfsr_perm_tRndCnstLfsrPermDefault
RndCnstRandPermrand_perm_tRndCnstRandPermDefault
RndCnstRevisionSeedseed_tRndCnstRevisionSeedDefault
RndCnstCreatorIdentitySeedseed_tRndCnstCreatorIdentitySeedDefault
RndCnstOwnerIntIdentitySeedseed_tRndCnstOwnerIntIdentitySeedDefault
RndCnstOwnerIdentitySeedseed_tRndCnstOwnerIdentitySeedDefault
RndCnstSoftOutputSeedseed_tRndCnstSoftOutputSeedDefault
RndCnstHardOutputSeedseed_tRndCnstHardOutputSeedDefault
RndCnstNoneSeedseed_tRndCnstNoneSeedDefault
RndCnstAesSeedseed_tRndCnstAesSeedDefault
RndCnstHmacSeedseed_tRndCnstHmacSeedDefault
RndCnstKmacSeedseed_tRndCnstKmacSeedDefault
AdvLfsrCopiesintAdvDataWidth / 32

Number of times the lfsr output fits into the inputs

IdLfsrCopiesintIdDataWidth / 32
GenLfsrCopiesintGenDataWidth / 32

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
clk​_edn​_iinlogic
rst​_edn​_niinlogic
tl​_iintl_h2d_t

Bus Interface

tl​_oouttl_d2h_t
aes​_key​_oouthw_key_req_t

key interface to crypto modules

hmac​_key​_oouthw_key_req_t
kmac​_key​_oouthw_key_req_t
kmac​_data​_ooutkmac_data_req_t

data interface to/from crypto modules

kmac​_data​_iinkmac_data_rsp_t
lc​_keymgr​_en​_iinlc_tx_t

the following signals should eventually be wrapped into structs from other modules

lc​_keymgr​_div​_iinlc_keymgr_div_t
otp​_key​_iinotp_keymgr_key_t
otp​_hw​_cfg​_iinotp_hw_cfg_t
flash​_iinkeymgr_flash_t
edn​_ooutedn_req_t

connection to edn

edn​_iinedn_rsp_t
intr​_op​_done​_ooutlogic

interrupts and alerts

alert​_rx​_iin[keymgr_reg_pkg::NumAlerts-1:0] alert_rx_t
alert​_tx​_oout[keymgr_reg_pkg::NumAlerts-1:0] alert_tx_t

Instantiations

Block Diagram

Package keymgr​_pkg

This design unit is implemented in keymgr​_pkg.sv

This file depends on: edn_pkg.sv

Module kmac

This design unit is implemented in kmac.sv

This file depends on: kmac_reg_pkg.sv, uvm_pkg.sv, sha3.sv, kmac_keymgr.sv, kmac_staterd.sv, prim_edn_req.sv, prim_intr_hw.sv, tlul_pkg.sv, kmac_entropy.sv, kmac_core.sv, tlul_adapter_sram.sv, kmac_msgfifo.sv, kmac_pkg.sv, sha3_pkg.sv, keymgr_pkg.sv, kmac_reg_top.sv, edn_pkg.sv

Parameters

NameTypeDefault ValueDescription
EnMaskingbit1

EnMasking: Enable masking security hardening inside keccak_round If it is enabled, the result digest will be two set of 1600bit.

ReuseSharebit0

ReuseShare: If set, keccak_round logic only consumes small portion of entropy, not 1600bit of entropy at every round. It uses adjacent shares as entropy inside Domain-Oriented Masking AND logic. This parameter only affects when EnMasking is set.

Shareint(EnMasking) ? 2 : 1

Parameters //

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
clk​_edn​_iinlogic
rst​_edn​_niinlogic
tl​_iintl_h2d_t
tl​_oouttl_d2h_t
keymgr​_key​_iinhw_key_req_t

KeyMgr sideload (secret key) interface

keymgr​_kdf​_iinkmac_data_req_t

KeyMgr KDF data path

keymgr​_kdf​_ooutkmac_data_rsp_t
entropy​_ooutedn_req_t

EDN interface

entropy​_iinedn_rsp_t
intr​_kmac​_done​_ooutlogic

interrupts

intr​_fifo​_empty​_ooutlogic
intr​_kmac​_err​_ooutlogic
idle​_ooutlogic

Idle signal

Instantiations

Block Diagram

State Machines

Module lc​_ctrl

This design unit is implemented in lc​_ctrl.sv

This file depends on: jtag_pkg.sv, dmi_jtag.sv, uvm_pkg.sv, top_pkg.sv, prim_esc_receiver.sv, prim_lc_sync.sv, lc_ctrl_reg_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, tlul_pkg.sv, prim_alert_sender.sv, pwrmgr_pkg.sv, prim_flop_2sync.sv, lc_ctrl_fsm.sv, lc_ctrl_reg_top.sv, lc_ctrl_state_pkg.sv, prim_clock_mux2.sv, prim_alert_pkg.sv, lc_ctrl_pkg.sv, dm_pkg.sv, prim_esc_pkg.sv

Parameters

NameTypeDefault ValueDescription
AlertAsyncOn[NumAlerts-1:0] logic{NumAlerts{1'b1}}

Enable asynchronous transitions on alerts.

IdcodeValue[31:0] logic32'h00000001

Idcode value for the JTAG.

RndCnstLcKeymgrDivInvalidlc_keymgr_div_tLcKeymgrDivWidth'(0)

Random netlist constants

RndCnstLcKeymgrDivTestDevRmalc_keymgr_div_tLcKeymgrDivWidth'(1)
RndCnstLcKeymgrDivProductionlc_keymgr_div_tLcKeymgrDivWidth'(2)

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Bus Interface (device)

tl​_oouttl_d2h_t
jtag​_iinjtag_req_t

JTAG TAP.

jtag​_ooutjtag_rsp_t
scanmode​_iinlc_tx_t

This bypasses the clock inverter inside the JTAG TAP for scanmmode.

alert​_rx​_iin[NumAlerts-1:0] alert_rx_t

Alert outputs.

alert​_tx​_oout[NumAlerts-1:0] alert_tx_t
esc​_wipe​_secrets​_tx​_iinesc_rx_t

Escalation inputs (severity 1 and 2). These need not be synchronized since the alert handler is in the same clock domain as the LC controller.

esc​_wipe​_secrets​_rx​_ooutesc_tx_t
esc​_scrap​_state​_tx​_iinesc_rx_t
esc​_scrap​_state​_rx​_ooutesc_tx_t
pwr​_lc​_iinpwr_lc_req_t

Power manager interface (inputs are synced to lifecycle clock domain).

pwr​_lc​_ooutpwr_lc_rsp_t
lc​_otp​_program​_ooutlc_otp_program_req_t

Life cycle transition command interface. No sync required since LC and OTP are in the same clock domain.

lc​_otp​_program​_iinlc_otp_program_rsp_t
lc​_otp​_token​_ooutlc_otp_token_req_t

Life cycle hashing interface for raw unlock No sync required since LC and OTP are in the same clock domain.

lc​_otp​_token​_iinlc_otp_token_rsp_t
otp​_lc​_data​_iinotp_lc_data_t

OTP broadcast outputs No sync required since LC and OTP are in the same clock domain.

lc​_dft​_en​_ooutlc_tx_t

Life cycle broadcast outputs (all of them are registered).

lc​_nvm​_debug​_en​_ooutlc_tx_t
lc​_hw​_debug​_en​_ooutlc_tx_t
lc​_cpu​_en​_ooutlc_tx_t
lc​_creator​_seed​_sw​_rw​_en​_ooutlc_tx_t
lc​_owner​_seed​_sw​_rw​_en​_ooutlc_tx_t
lc​_iso​_part​_sw​_rd​_en​_ooutlc_tx_t
lc​_iso​_part​_sw​_wr​_en​_ooutlc_tx_t
lc​_seed​_hw​_rd​_en​_ooutlc_tx_t
lc​_keymgr​_en​_ooutlc_tx_t
lc​_escalate​_en​_ooutlc_tx_t
lc​_check​_byp​_en​_ooutlc_tx_t
lc​_clk​_byp​_req​_ooutlc_tx_t

Request and feedback to/from clock manager and AST. The ack is synced to the lc clock domain using prim_lc_sync.

lc​_clk​_byp​_ack​_iinlc_tx_t
lc​_flash​_rma​_seed​_ooutlc_flash_rma_seed_t

Request and feedback to/from flash controller. The ack is synced to the lc clock domain using prim_lc_sync.

lc​_flash​_rma​_req​_ooutlc_tx_t
lc​_flash​_rma​_ack​_iinlc_tx_t
lc​_keymgr​_div​_ooutlc_keymgr_div_t

State group diversification value for keymgr.

otp​_hw​_cfg​_iinotp_hw_cfg_t

Hardware config input, needed for the DEVICE_ID field.

Instantiations

Block Diagram

Package lc​_ctrl​_state​_pkg

This design unit is implemented in lc​_ctrl​_state​_pkg.sv

This file depends on: prim_util_pkg.sv

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

Life cycle state encoding definition.

DO NOT EDIT THIS FILE DIRECTLY. It has been generated with $ ./util/design/gen-lc-state-enc.py --seed 10167336684108184581

Module otbn

This design unit is implemented in otbn.sv

This file depends on: uvm_pkg.sv, top_pkg.sv, prim_edn_req.sv, prim_intr_hw.sv, tlul_pkg.sv, prim_util_pkg.sv, otbn_reg_pkg.sv, prim_alert_sender.sv, otbn_core.sv, tlul_adapter_sram.sv, prim_ram_1p_adv.sv, otbn_reg_top.sv, prim_alert_pkg.sv, edn_pkg.sv, otbn_pkg.sv

Description

Parameters

NameTypeDefault ValueDescription
RegFileregfile_eRegFileFF
AlertAsyncOn[NumAlerts-1:0] logic{NumAlerts{1'b1}}
ImemSizeByteintint'(otbn_reg_pkg::OTBN_IMEM_SIZE)

The OTBN_*_SIZE parameters are auto-generated by regtool and come from the bus window sizes; they are given in bytes and must be powers of two.

DmemSizeByteintint'(otbn_reg_pkg::OTBN_DMEM_SIZE)
ImemAddrWidthintvbits(ImemSizeByte)
DmemAddrWidthintvbits(DmemSizeByte)
ImemSizeWordsintImemSizeByte / 4
ImemIndexWidthintvbits(ImemSizeWords)
DmemSizeWordsintDmemSizeByte / (WLEN / 8)
DmemIndexWidthintvbits(DmemSizeWords)

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t
tl​_oouttl_d2h_t
idle​_ooutlogic

Inter-module signals

intr​_done​_ooutlogic

Interrupts

alert​_rx​_iin[NumAlerts-1:0] alert_rx_t

Alerts

alert​_tx​_oout[NumAlerts-1:0] alert_tx_t
clk​_edn​_iinlogic

EDN clock and interface

rst​_edn​_niinlogic
edn​_ooutedn_req_t
edn​_iinedn_rsp_t

Instantiations

Block Diagram

Package otbn​_pkg

This design unit is implemented in otbn​_pkg.sv

Module otp​_ctrl

This design unit is implemented in otp​_ctrl.sv

This file depends on: uvm_pkg.sv, prim_edn_req.sv, otp_ctrl_pkg.sv, otp_ctrl_lci.sv, otp_ctrl_reg_pkg.sv, tlul_pkg.sv, prim_alert_sender.sv, otp_ctrl_lfsr_timer.sv, prim_arbiter_tree.sv, pwrmgr_pkg.sv, otp_ctrl_dai.sv, otp_ctrl_reg_top.sv, prim_flop_2sync.sv, otp_ctrl_scrmbl.sv, otp_ctrl_part_buf.sv, prim_arbiter_fixed.sv, lc_ctrl_state_pkg.sv, prim_fifo_sync.sv, lc_ctrl_pkg.sv, prim_lc_sync.sv, otp_ctrl_part_unbuf.sv, otp_ctrl_part_pkg.sv, prim_intr_hw.sv, prim_util_pkg.sv, tlul_adapter_sram.sv, prim_otp.sv, otp_ctrl_kdi.sv, prim_alert_pkg.sv, prim_otp_pkg.sv, edn_pkg.sv

Parameters

NameTypeDefault ValueDescription
AlertAsyncOn[NumAlerts-1:0] logic{NumAlerts{1'b1}}

Enable asynchronous transitions on alerts.

RndCnstLfsrSeedlfsr_seed_tRndCnstLfsrSeedDefault

Compile time random constants, to be overriden by topgen.

RndCnstLfsrPermlfsr_perm_tRndCnstLfsrPermDefault
MemInitFileunknown""

Hexfile file to initialize the OTP macro. Note that the hexdump needs to account for ECC.

Ports

NameDirectionTypeDescription
clk​_iinlogic

OTP clock

rst​_niinlogic
clk​_edn​_iinlogic

EDN clock and interface

rst​_edn​_niinlogic
edn​_ooutedn_req_t
edn​_iinedn_rsp_t
tl​_iintl_h2d_t

Bus Interface (device)

tl​_oouttl_d2h_t
intr​_otp​_operation​_done​_ooutlogic

Interrupt Requests

intr​_otp​_error​_ooutlogic
alert​_rx​_iin[NumAlerts-1:0] alert_rx_t

Alerts

alert​_tx​_oout[NumAlerts-1:0] alert_tx_t
otp​_ast​_pwr​_seq​_ooutotp_ast_req_t

Macro-specific power sequencing signals to/from AST.

otp​_ast​_pwr​_seq​_h​_iinotp_ast_rsp_t
pwr​_otp​_iinpwr_otp_req_t

Power manager interface (inputs are synced to OTP clock domain)

pwr​_otp​_ooutpwr_otp_rsp_t
lc​_otp​_program​_iinlc_otp_program_req_t

Lifecycle transition command interface

lc​_otp​_program​_ooutlc_otp_program_rsp_t
lc​_otp​_token​_iinlc_otp_token_req_t

Lifecycle hashing interface for raw unlock

lc​_otp​_token​_ooutlc_otp_token_rsp_t
lc​_creator​_seed​_sw​_rw​_en​_iinlc_tx_t

Lifecycle broadcast inputs

lc​_seed​_hw​_rd​_en​_iinlc_tx_t
lc​_dft​_en​_iinlc_tx_t
lc​_escalate​_en​_iinlc_tx_t
lc​_check​_byp​_en​_iinlc_tx_t
otp​_lc​_data​_ooutotp_lc_data_t

OTP broadcast outputs

otp​_keymgr​_key​_ooutotp_keymgr_key_t
flash​_otp​_key​_iinflash_otp_key_req_t

Scrambling key requests

flash​_otp​_key​_ooutflash_otp_key_rsp_t
sram​_otp​_key​_iin[NumSramKeyReqSlots-1:0] sram_otp_key_req_t
sram​_otp​_key​_oout[NumSramKeyReqSlots-1:0] sram_otp_key_rsp_t
otbn​_otp​_key​_iinotbn_otp_key_req_t
otbn​_otp​_key​_ooutotbn_otp_key_rsp_t
otp​_hw​_cfg​_ooutotp_hw_cfg_t

Hardware config bits

Instantiations

Block Diagram

Package otp​_ctrl​_part​_pkg

This design unit is implemented in otp​_ctrl​_part​_pkg.sv

This file depends on: otp_ctrl_pkg.sv, prim_util_pkg.sv, otp_ctrl_reg_pkg.sv, lc_ctrl_pkg.sv

Package otp​_ctrl​_reg​_pkg

This design unit is implemented in otp​_ctrl​_reg​_pkg.sv

Module pattgen

This design unit is implemented in pattgen.sv

This file depends on: pattgen_reg_top.sv, uvm_pkg.sv, pattgen_core.sv, tlul_pkg.sv, pattgen_reg_pkg.sv

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t
tl​_oouttl_d2h_t
cio​_pda0​_tx​_ooutlogic
cio​_pcl0​_tx​_ooutlogic
cio​_pda1​_tx​_ooutlogic
cio​_pcl1​_tx​_ooutlogic
cio​_pda0​_tx​_en​_ooutlogic
cio​_pcl0​_tx​_en​_ooutlogic
cio​_pda1​_tx​_en​_ooutlogic
cio​_pcl1​_tx​_en​_ooutlogic
intr​_done​_ch0​_ooutlogic
intr​_done​_ch1​_ooutlogic

Instantiations

Block Diagram

Module pinmux

This design unit is implemented in pinmux.sv

This file depends on: pinmux_reg_pkg.sv, jtag_pkg.sv, usbdev_pkg.sv, uvm_pkg.sv, usbdev_aon_wake.sv, pinmux_reg_top.sv, pinmux_pkg.sv, pinmux_wkup.sv, tlul_pkg.sv, lc_ctrl_pkg.sv, pinmux_strap_sampling.sv

Parameters

NameTypeDefault ValueDescription
AlignedMuxSizeint(NMioPads + 2 > NDioPads) ? 2**$clog2(NMioPads + 2) : 2**$clog2(NDioPads)

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
clk​_aon​_iinlogic

Slow always-on clock

rst​_aon​_niinlogic
aon​_wkup​_req​_ooutlogic

Wakeup request, running on clk_aon_i

usb​_wkup​_req​_ooutlogic
sleep​_en​_iinlogic

Sleep enable and strap sample enable from pwrmgr, running on clk_i TODO(#5198): figure out the connections.

strap​_en​_iinlogic
lc​_dft​_en​_iinlc_tx_t

LC signals for TAP qualification

lc​_hw​_debug​_en​_iinlc_tx_t
dft​_strap​_test​_ooutdft_strap_test_req_t

Sampled values for DFT straps

lc​_jtag​_ooutjtag_req_t

Qualified JTAG signals for TAPs

lc​_jtag​_iinjtag_rsp_t
rv​_jtag​_ooutjtag_req_t
rv​_jtag​_iinjtag_rsp_t
dft​_jtag​_ooutjtag_req_t
dft​_jtag​_iinjtag_rsp_t
usb​_out​_of​_rst​_iinlogic

Direct USB connection

usb​_aon​_wake​_en​_iinlogic
usb​_aon​_wake​_ack​_iinlogic
usb​_suspend​_iinlogic
usb​_state​_debug​_ooutawk_state_t
tl​_iintl_h2d_t

Bus Interface (device)

tl​_oouttl_d2h_t
periph​_to​_mio​_iin[NMioPeriphOut-1:0] logic

Muxed Peripheral side

periph​_to​_mio​_oe​_iin[NMioPeriphOut-1:0] logic
mio​_to​_periph​_oout[NMioPeriphIn-1:0] logic
periph​_to​_dio​_iin[NDioPads-1:0] logic

Dedicated Peripheral side

periph​_to​_dio​_oe​_iin[NDioPads-1:0] logic
dio​_to​_periph​_oout[NDioPads-1:0] logic
mio​_attr​_oout[AttrDw-1:0] [NMioPads-1:0] logic

Pad side MIOs

mio​_out​_oout[NMioPads-1:0] logic
mio​_oe​_oout[NMioPads-1:0] logic
mio​_in​_iin[NMioPads-1:0] logic
dio​_attr​_oout[AttrDw-1:0] [NDioPads-1:0] logic

DIOs

dio​_out​_oout[NDioPads-1:0] logic
dio​_oe​_oout[NDioPads-1:0] logic
dio​_in​_iin[NDioPads-1:0] logic

Instantiations

Block Diagram

Package pinmux​_pkg

This design unit is implemented in pinmux​_pkg.sv

Package prim​_alert​_pkg

This design unit is implemented in prim​_alert​_pkg.sv

Package prim​_esc​_pkg

This design unit is implemented in prim​_esc​_pkg.sv

Module prim​_generic​_usb​_diff​_rx

This design unit is implemented in prim​_generic​_usb​_diff​_rx.sv

Parameters

NameTypeDefault ValueDescription
CalibWint32

Ports

NameDirectionTypeDescription
input​_piinlogic

differential input

input​_niinlogic

differential input

input​_en​_iinlogic

input buffer enable

core​_pok​_iinlogic

core power indication at VCC level

pullup​_p​_en​_iinlogic

pullup enable for P

pullup​_n​_en​_iinlogic

pullup enable for N

calibration​_iin[CalibW-1:0] logic

calibration input

input​_ooutlogic

output of differential input buffer

Block Diagram

Module prim​_pad​_wrapper

This design unit is implemented in prim​_pad​_wrapper.sv

This file depends on: prim_xilinx_pad_wrapper.sv, prim_generic_pad_wrapper.sv, prim_pkg.sv

Description

This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

Parameters

NameTypeDefault ValueDescription
Variantint0

currently ignored

AttrDwint10
WarlOnlybit0

If set to 1, no pad is instantiated and only warl_o is driven

Implimpl_eprim_pkg::ImplGeneric

Ports

NameDirectionTypeDescription
inout​_ioinoutlogic

bidirectional pad

in​_ooutlogic

input data

ie​_iinlogic

input enable

out​_iinlogic

output data

oe​_iinlogic

output enable

attr​_iin[AttrDw-1:0] logic

additional attributes

warl​_oout[AttrDw-1:0] logic

Block Diagram

Module prim​_ram​_1p​_scr

This design unit is implemented in prim​_ram​_1p​_scr.sv

This file depends on: uvm_pkg.sv, prim_ram_1p_adv.sv, prim_util_pkg.sv, prim_subst_perm.sv, prim_prince.sv

Parameters

NameTypeDefault ValueDescription
Depthint16*1024

Needs to be a power of 2 if NumAddrScrRounds > 0.

Widthint32

Needs to be byte aligned if byte parity is enabled.

DataBitsPerMaskint8

Needs to be set to 8 in case of byte parity.

EnableParitybit1

Enable byte parity.

CfgWidthint8

WTC, RTC, etc

NumPrinceRoundsHalfint2

Scrambling parameters. Note that this needs to be low-latency, hence we have to keep the amount of cipher rounds low. PRINCE has 5 half rounds in its original form, which corresponds to 2*5 + 1 effective rounds. Setting this to 2 halves this to approximately 5 effective rounds. Number of PRINCE half rounds, can be 1..5

NumDiffRoundsint2

Number of extra diffusion rounds. Setting this to 0 to disable diffusion.

DiffWidthintDataBitsPerMask

This parameter governs the block-width of additional diffusion layers. For intra-byte diffusion, set this parameter to 8. Note that DataBitsPerMask must be a multiple of this parameter.

NumAddrScrRoundsint2

Number of address scrambling rounds. Setting this to 0 disables address scrambling.

ReplicateKeyStreambit1'b0

If set to 1, the same 64bit key stream is replicated if the data port is wider than 64bit. If set to 0, the cipher primitive is replicated, and together with a wider nonce input, a unique keystream is generated for the full data width.

AddrWidthintprim_util_pkg::vbits(Depth)

Derived parameters

NumParScrint(ReplicateKeyStream) ? 1 : (Width + 63) / 64

Depending on the data width, we need to instantiate multiple parallel cipher primitives to create a keystream that is wide enough (PRINCE has a block size of 64bit)

NumParKeystrint(ReplicateKeyStream) ? (Width + 63) / 64 : 1
DataKeyWidthint128

This is given by the PRINCE cipher primitive. All parallel cipher modules use the same key, but they use a different IV

NonceWidthint64 * NumParScr

Each 64 bit scrambling primitive requires a 64bit IV

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
key​_valid​_iinlogic

Key interface. Memory requests will not be granted if key_valid is set to 0.

key​_iin[DataKeyWidth-1:0] logic
nonce​_iin[NonceWidth-1:0] logic
req​_iinlogic

Interface to TL-UL SRAM adapter

gnt​_ooutlogic
write​_iinlogic
addr​_iin[AddrWidth-1:0] logic
wdata​_iin[Width-1:0] logic
wmask​_iin[Width-1:0] logic

Needs to be byte-aligned for parity

rdata​_oout[Width-1:0] logic
rvalid​_ooutlogic

Read response (rdata_o) is valid

rerror​_oout[1:0] logic

Bit1: Uncorrectable, Bit0: Correctable

raddr​_oout[31:0] logic

Read address for error reporting.

cfg​_iin[CfgWidth-1:0] logic

config

Instantiations

Block Diagram

Module prim​_rom​_adv

This design unit is implemented in prim​_rom​_adv.sv

This file depends on: uvm_pkg.sv, prim_rom.sv

Parameters

NameTypeDefault ValueDescription
Widthint32

Parameters passed on the the ROM primitive.

Depthint2048

8kB default

MemInitFileunknown""

VMEM file to initialize the memory with

CfgWint8

WTC, RTC, etc

Awint$clog2(Depth)

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
req​_iinlogic
addr​_iin[Aw-1:0] logic
rvalid​_ooutlogic
rdata​_oout[Width-1:0] logic
cfg​_iin[CfgW-1:0] logic

Instantiations

Block Diagram

Package prim​_util​_pkg

This design unit is implemented in prim​_util​_pkg.sv

Description

Module pwrmgr

This design unit is implemented in pwrmgr.sv

This file depends on: uvm_pkg.sv, prim_esc_receiver.sv, pwrmgr_cdc.sv, pwrmgr_reg_top.sv, pwrmgr_fsm.sv, pwrmgr_wake_info.sv, prim_intr_hw.sv, tlul_pkg.sv, pwrmgr_reg_pkg.sv, pwrmgr_slow_fsm.sv, pwrmgr_pkg.sv, prim_esc_pkg.sv

Description

pwrmgr

Ports

NameDirectionTypeDescription
clk​_slow​_iinlogic

Clocks and resets

clk​_iinlogic
rst​_slow​_niinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Bus Interface

tl​_oouttl_d2h_t
pwr​_ast​_iinpwr_ast_rsp_t

AST interface

pwr​_ast​_ooutpwr_ast_req_t
pwr​_rst​_iinpwr_rst_rsp_t

rstmgr interface

pwr​_rst​_ooutpwr_rst_req_t
pwr​_clk​_ooutpwr_clk_req_t

clkmgr interface

pwr​_clk​_iinpwr_clk_rsp_t
pwr​_otp​_iinpwr_otp_rsp_t

otp interface

pwr​_otp​_ooutpwr_otp_req_t
pwr​_lc​_iinpwr_lc_rsp_t

life cycle interface

pwr​_lc​_ooutpwr_lc_req_t
pwr​_flash​_ooutpwr_flash_req_t

flash interface

pwr​_flash​_iinpwr_flash_rsp_t
pwr​_cpu​_iinpwr_cpu_t

processor interface

wakeups​_iin[NumWkups-1:0] logic

peripherals wakeup and reset requests

rstreqs​_iin[NumRstReqs-1:0] logic
esc​_rst​_tx​_iinesc_tx_t

escalation interface

esc​_rst​_rx​_ooutesc_rx_t
intr​_wakeup​_ooutlogic

Instantiations

Block Diagram

Package pwrmgr​_reg​_pkg

This design unit is implemented in pwrmgr​_reg​_pkg.sv

Module rglts​_pdm​_3p3v

This design unit is implemented in rglts​_pdm​_3p3v.sv

This file depends on: ast_pkg.sv, gen_pok.sv

Description

of rglts_pdm_3p3v

Parameters

NameTypeDefault ValueDescription
MRVCC​_RDLYtime5us
MRVCC​_FDLYtime100ns
MRPD​_RDLYtime50us
MRPD​_FDLYtime1us

Ports

NameDirectionTypeDescription
vcc​_pok​_h​_iinlogic

VCC (3.3V) Exist @3.3v

vcmain​_pok​_h​_iinlogic

VCMAIN (1.1v) Exist @3.3v

clk​_src​_aon​_h​_iinlogic

AON Clock @3.3v

main​_pd​_h​_niinlogic

VCMAIN/Regulator Power Down @3.3v

otp​_power​_seq​_h​_iin[1:0] logic

MMR0,24 in @3.3v

vcaon​_pok​_h​_ooutlogic

VCAON (1.1v) Exist @3.3v

main​_pwr​_dly​_ooutlogic

For modeling only.

flash​_power​_down​_h​_ooutlogic
flash​_power​_ready​_h​_ooutlogic
otp​_power​_seq​_h​_oout[1:0] logic

MMR0,24 masked by PDM, out (VCC)

Instantiations

Block Diagram

Module rng

This design unit is implemented in rng.sv

This file depends on: rng_osc.sv

Description

of rng

Parameters

NameTypeDefault ValueDescription
RNG​_EN​_RDLYtime5us
EntropyStreamsint4

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
vcaon​_pok​_iinlogic
rng​_en​_iinlogic
rng​_b​_oout[EntropyStreams-1:0] logic
rng​_val​_ooutlogic

Instantiations

Block Diagram

Module rstmgr

This design unit is implemented in rstmgr.sv

This file depends on: uvm_pkg.sv, rv_core_ibex_pkg.sv, prim_lc_sync.sv, rstmgr_por.sv, rstmgr_ctrl.sv, alert_pkg.sv, tlul_pkg.sv, pwrmgr_pkg.sv, rstmgr_reg_pkg.sv, prim_flop_2sync.sv, prim_subreg.sv, rstmgr_reg_top.sv, prim_clock_mux2.sv, rstmgr_pkg.sv, lc_ctrl_pkg.sv, rstmgr_crash_info.sv

Description

rstmgr

Ports

NameDirectionTypeDescription
clk​_iinlogic

Primary module clocks

rst​_niinlogic

this is connected to the top level reset

clk​_aon​_iinlogic
clk​_io​_div4​_iinlogic
clk​_main​_iinlogic
clk​_io​_iinlogic
clk​_io​_div2​_iinlogic
clk​_usb​_iinlogic
tl​_iintl_h2d_t

Bus Interface

tl​_oouttl_d2h_t
pwr​_iinpwr_rst_req_t

pwrmgr interface

pwr​_ooutpwr_rst_rsp_t
cpu​_iinrstmgr_cpu_t

cpu related inputs

alert​_dump​_iinalert_crashdump_t

Interface to alert handler

cpu​_dump​_iincrashdump_t

Interface to cpu crash dump

scan​_rst​_niinlogic

dft bypass

scanmode​_iinlc_tx_t
resets​_ast​_ooutrstmgr_ast_out_t

reset outputs

resets​_ooutrstmgr_out_t

Instantiations

Block Diagram

Module rv​_core​_ibex

This design unit is implemented in rv​_core​_ibex.sv

This file depends on: rv_core_ibex_pkg.sv, top_pkg.sv, prim_esc_receiver.sv, prim_lc_sync.sv, ibex_tracer.sv, tlul_pkg.sv, ibex_core.sv, tlul_fifo_sync.sv, prim_flop_2sync.sv, tlul_adapter_host.sv, ibex_pkg.sv, lc_ctrl_pkg.sv, prim_esc_pkg.sv

Description

Parameters

NameTypeDefault ValueDescription
PMPEnablebit1'b0
PMPGranularityint0
PMPNumRegionsint4
MHPMCounterNumint10
MHPMCounterWidthint32
RV32Ebit0
RV32Mrv32m_eibex_pkg::RV32MSingleCycle
RV32Brv32b_eibex_pkg::RV32BNone
RegFileregfile_eibex_pkg::RegFileFF
BranchTargetALUbit1'b1
WritebackStagebit1'b1
ICachebit1'b0
ICacheECCbit1'b0
BranchPredictorbit1'b0
DbgTriggerEnbit1'b1
SecureIbexbit1'b0
DmHaltAddrint32'h1A110800
DmExceptionAddrint32'h1A110808
PipeLinebit1'b0
FifoPassbitPipeLine ? 1'b0 : 1'b1

if pipeline=1, do not allow pass through and always break the path if pipeline is 0, passthrough the fifo completely

FifoDepthintPipeLine ? 2 : 0
NumOutstandingReqsintICache ? 8 : 2

ICache creates more outstanding transactions

Ports

NameDirectionTypeDescription
clk​_iinlogic

Clock and Reset

rst​_niinlogic
clk​_esc​_iinlogic

Clock domain for escalation receiver

rst​_esc​_niinlogic
test​_en​_iinlogic

enable all clock gates for testing

hart​_id​_iin[31:0] logic
boot​_addr​_iin[31:0] logic
tl​_i​_oouttl_h2d_t

Instruction memory interface

tl​_i​_iintl_d2h_t
tl​_d​_oouttl_h2d_t

Data memory interface

tl​_d​_iintl_d2h_t
irq​_software​_iinlogic

Interrupt inputs

irq​_timer​_iinlogic
irq​_external​_iinlogic
esc​_tx​_iinesc_tx_t

Escalation input for NMI

esc​_rx​_ooutesc_rx_t
debug​_req​_iinlogic

Debug Interface

crash​_dump​_ooutcrashdump_t

Crash dump information

fetch​_enable​_iinlc_tx_t

CPU Control Signals

core​_sleep​_ooutlogic

Instantiations

Block Diagram

Package rv​_core​_ibex​_pkg

This design unit is implemented in rv​_core​_ibex​_pkg.sv

This file depends on: top_pkg.sv

Module rv​_dm

This design unit is implemented in rv​_dm.sv

This file depends on: jtag_pkg.sv, dm_sba.sv, tlul_adapter_sram.sv, uvm_pkg.sv, tlul_adapter_host.sv, prim_lc_sync.sv, dm_csrs.sv, dm_mem.sv, tlul_pkg.sv, lc_ctrl_pkg.sv, dm_pkg.sv

Parameters

NameTypeDefault ValueDescription
NrHartsint1
IdcodeValue[31:0] logic32'h 0000_0001
BusWidthint32

Currently only 32 bit busses are supported by our TL-UL IP

SelectableHarts[NrHarts-1:0] logic{NrHarts{1'b1}}

all harts have contiguous IDs

DebugHartInfohartinfo_t'{ zero1: '0, nscratch: 2, zero0: 0, dataaccess: 1'b1, datasize: dm::DataCount, dataaddr: dm::DataAddr }

static debug hartinfo

AddressWidthWordsintBusWidth - $clog2(BusWidth/8)

Ports

NameDirectionTypeDescription
clk​_iinlogic

clock

rst​_niinlogic

asynchronous reset active low, connect PoR

hw​_debug​_en​_iinlc_tx_t
scanmode​_iinlc_tx_t
ndmreset​_ooutlogic

non-debug module reset

dmactive​_ooutlogic

debug module is active

debug​_req​_oout[NrHarts-1:0] logic

async debug request

unavailable​_iin[NrHarts-1:0] logic

communicate whether the hart is unavailable

tl​_d​_iintl_h2d_t

bus device with debug memory, for an execution based technique

tl​_d​_oouttl_d2h_t
tl​_h​_oouttl_h2d_t

bus host, for system bus accesses

tl​_h​_iintl_d2h_t
jtag​_req​_iinjtag_req_t
jtag​_rsp​_ooutjtag_rsp_t

Instantiations

Block Diagram

Module rv​_plic

This design unit is implemented in rv​_plic.sv

This file depends on: rv_plic_reg_top.sv, rv_plic_gateway.sv, rv_plic_target.sv, uvm_pkg.sv, rv_plic_reg_pkg.sv, tlul_pkg.sv

Parameters

NameTypeDefault ValueDescription
SRCWint$clog2(NumSrc)

derived parameter

MAX​_PRIOint3
PRIOWint$clog2(MAX_PRIO+1)

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Bus Interface (device)

tl​_oouttl_d2h_t
intr​_src​_iin[NumSrc-1:0] logic

Interrupt Sources

irq​_oout[NumTarget-1:0] logic

Interrupt notification to targets

irq​_id​_oout[SRCW-1:0] logic [NumTarget]
msip​_oout[NumTarget-1:0] logic

Instantiations

Block Diagram

Module rv​_timer

This design unit is implemented in rv​_timer.sv

This file depends on: rv_timer_reg_pkg.sv, timer_core.sv, uvm_pkg.sv, prim_intr_hw.sv, tlul_pkg.sv, rv_timer_reg_top.sv

Parameters

NameTypeDefault ValueDescription
N​_HARTSint1
N​_TIMERSint1

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t
tl​_oouttl_d2h_t
intr​_timer​_expired​_0​_0​_ooutlogic

Instantiations

Block Diagram

Module sensor​_ctrl

This design unit is implemented in sensor​_ctrl.sv

This file depends on: ast_pkg.sv, sensor_ctrl_reg_pkg.sv, sensor_ctrl_reg_top.sv, sensor_ctrl_pkg.sv, tlul_pkg.sv, prim_alert_pkg.sv, prim_alert_sender.sv

Description

sensor_ctrl

Parameters

NameTypeDefault ValueDescription
AsyncOnlogic1'b0

Ports

NameDirectionTypeDescription
clk​_iinlogic

Primary module clocks

rst​_niinlogic
tl​_iintl_h2d_t

Bus Interface

tl​_oouttl_d2h_t
ast​_alert​_iinast_alert_req_t

Interface from AST

ast​_alert​_ooutast_alert_rsp_t
ast​_status​_iinast_status_t
alert​_rx​_iin[NumAlerts-1:0] alert_rx_t

Alerts

alert​_tx​_oout[NumAlerts-1:0] alert_tx_t

Instantiations

Block Diagram

Module spi​_device

This design unit is implemented in spi​_device.sv

This file depends on: spi_device_reg_pkg.sv, uvm_pkg.sv, prim_lc_sync.sv, prim_sram_arbiter.sv, spi_device_pkg.sv, tlul_pkg.sv, spi_fwmode.sv, prim_clock_inv.sv, prim_fifo_async.sv, spi_fwm_txf_ctrl.sv, tlul_adapter_sram.sv, prim_flop_2sync.sv, prim_clock_mux2.sv, prim_pulse_sync.sv, spi_fwm_rxf_ctrl.sv, spi_p2s.sv, prim_ram_2p_adv.sv, lc_ctrl_pkg.sv, spi_s2p.sv, prim_clock_buf.sv, spi_device_reg_top.sv

Parameters

NameTypeDefault ValueDescription
FifoWidthint$bits(spi_byte_t)
FifoDepthint8

2 DWords

SDWint$clog2(SramDw/FifoWidth)
PtrWintSramAw + 1 + SDW
AsFifoDepthWint$clog2(FifoDepth+1)

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Register interface

tl​_oouttl_d2h_t
cio​_sck​_iinlogic

SPI Interface

cio​_csb​_iinlogic
cio​_sd​_oout[3:0] logic
cio​_sd​_en​_oout[3:0] logic
cio​_sd​_iin[3:0] logic
intr​_rxf​_ooutlogic

RX FIFO Full

intr​_rxlvl​_ooutlogic

RX FIFO above level

intr​_txlvl​_ooutlogic

TX FIFO below level

intr​_rxerr​_ooutlogic

RX Frame error

intr​_rxoverflow​_ooutlogic

RX Async FIFO Overflow

intr​_txunderflow​_ooutlogic

TX Async FIFO Underflow

scan​_clk​_iinlogic

DFT related controls

scan​_rst​_niinlogic
scanmode​_iinlc_tx_t

Instantiations

Block Diagram

Module spi​_host

This design unit is implemented in spi​_host.sv

This file depends on: spi_host_reg_top.sv, spi_host_reg_pkg.sv, tlul_pkg.sv, lc_ctrl_pkg.sv

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
scanmode​_iinlc_tx_t
tl​_iintl_h2d_t

Register interface

tl​_oouttl_d2h_t
cio​_sck​_ooutlogic

SPI Interface

cio​_sck​_en​_ooutlogic
cio​_csb​_ooutlogic
cio​_csb​_en​_ooutlogic
cio​_sd​_oout[3:0] logic
cio​_sd​_en​_oout[3:0] logic
cio​_sd​_iin[3:0] logic

Instantiations

Block Diagram

Module sram​_ctrl

This design unit is implemented in sram​_ctrl.sv

This file depends on: prim_sync_reqack_data.sv, sram_ctrl_pkg.sv, uvm_pkg.sv, prim_lc_sync.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, tlul_pkg.sv, prim_alert_pkg.sv, sram_ctrl_reg_pkg.sv, sram_ctrl_reg_top.sv, lc_ctrl_pkg.sv, prim_alert_sender.sv

Parameters

NameTypeDefault ValueDescription
AlertAsyncOn[NumAlerts-1:0] logic{NumAlerts{1'b1}}

Enable asynchronous transitions on alerts.

InstrExecbit1
RndCnstSramKeysram_key_tRndCnstSramKeyDefault

Random netlist constants

RndCnstSramNoncesram_nonce_tRndCnstSramNonceDefault

Ports

NameDirectionTypeDescription
clk​_iinlogic

SRAM Clock

rst​_niinlogic
clk​_otp​_iinlogic

OTP Clock (for key interface)

rst​_otp​_niinlogic
tl​_iintl_h2d_t

Bus Interface (device) for CSRs

tl​_oouttl_d2h_t
alert​_rx​_iin[NumAlerts-1:0] alert_rx_t

Alert outputs.

alert​_tx​_oout[NumAlerts-1:0] alert_tx_t
lc​_escalate​_en​_iinlc_tx_t

Life-cycle escalation input (scraps the scrambling keys)

lc​_hw​_debug​_en​_iinlc_tx_t
otp​_hw​_cfg​_iinotp_hw_cfg_t

Otp configuration for sram execution

sram​_otp​_key​_ooutsram_otp_key_req_t

Key request to OTP (running on clk_fixed)

sram​_otp​_key​_iinsram_otp_key_rsp_t
sram​_scr​_ooutsram_scr_req_t

Interface with SRAM scrambling wrapper

sram​_scr​_iinsram_scr_rsp_t
en​_ifetch​_oouttl_instr_en_e

Interface with corresponding tlul adapters

Instantiations

Block Diagram

Package sram​_ctrl​_pkg

This design unit is implemented in sram​_ctrl​_pkg.sv

This file depends on: otp_ctrl_pkg.sv

Module sys​_clk

This design unit is implemented in sys​_clk.sv

This file depends on: sys_osc.sv

Description

of sys_clk

Parameters

NameTypeDefault ValueDescription
SYS​_EN​_RDLYtime5us

Ports

NameDirectionTypeDescription
clk​_src​_sys​_en​_iinlogic

System Source Clock Enable

clk​_src​_sys​_jen​_iinlogic

System Source Clock Jitter Enable

clk​_sys​_pd​_niinlogic

System Clock Power-down

rst​_sys​_clk​_niinlogic

System Clock Logic reset

vcore​_pok​_h​_iinlogic

VCORE POK @3.3V (for OSC)

clk​_src​_sys​_ooutlogic

System Source Clock

clk​_src​_sys​_val​_ooutlogic

System Source Clock Valid

Instantiations

Block Diagram

Package tl​_main​_pkg

This design unit is implemented in tl​_main​_pkg.sv

Module tlul​_adapter​_sram

This design unit is implemented in tlul​_adapter​_sram.sv

This file depends on: tlul_err.sv, uvm_pkg.sv, top_pkg.sv, prim_fifo_sync.sv, tlul_pkg.sv, prim_util_pkg.sv

Description

Parameters

NameTypeDefault ValueDescription
SramAwint12
SramDwint32

Must be multiple of the TL width

Outstandingint1

Only one request is accepted

ByteAccessbit1

1: true, 0: false

ErrOnWritebit0

1: Writes not allowed, automatically error

ErrOnReadbit0

1: Reads not allowed, automatically error

SramByteintSramDw/8
DataBitWidthintprim_util_pkg::vbits(SramByte)
WidthMultintSramDw / top_pkg::TL_DW
WoffsetWidthint(SramByte == top_pkg::TL_DBW) ? 1 : DataBitWidth - prim_util_pkg::vbits(top_pkg::TL_DBW)
SramReqFifoWidthint$bits(sram_req_t)
ReqFifoWidthint$bits(req_t)
RspFifoWidthint$bits(rsp_t)

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

TL-UL interface

tl​_oouttl_d2h_t
en​_ifetch​_iintl_instr_en_e

control interface

req​_ooutlogic

SRAM interface

gnt​_iinlogic
we​_ooutlogic
addr​_oout[SramAw-1:0] logic
wdata​_oout[SramDw-1:0] logic
wmask​_oout[SramDw-1:0] logic
rdata​_iin[SramDw-1:0] logic
rvalid​_iinlogic
rerror​_iin[1:0] logic

2 bit error 1: Uncorrectable, 0: Correctable

Instantiations

Block Diagram

Package top​_earlgrey​_rnd​_cnst​_pkg

This design unit is implemented in top​_earlgrey​_rnd​_cnst​_pkg.sv

This file depends on: keymgr_pkg.sv, otp_ctrl_pkg.sv, alert_pkg.sv, flash_ctrl_pkg.sv, lc_ctrl_pkg.sv

Module uart

This design unit is implemented in uart.sv

This file depends on: uvm_pkg.sv, uart_core.sv, uart_reg_pkg.sv, uart_reg_top.sv, tlul_pkg.sv

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
tl​_iintl_h2d_t

Bus Interface

tl​_oouttl_d2h_t
cio​_rx​_iinlogic

Generic IO

cio​_tx​_ooutlogic
cio​_tx​_en​_ooutlogic
intr​_tx​_watermark​_ooutlogic

Interrupts

intr​_rx​_watermark​_ooutlogic
intr​_tx​_empty​_ooutlogic
intr​_rx​_overflow​_ooutlogic
intr​_rx​_frame​_err​_ooutlogic
intr​_rx​_break​_err​_ooutlogic
intr​_rx​_timeout​_ooutlogic
intr​_rx​_parity​_err​_ooutlogic

Instantiations

Block Diagram

Module usb​_clk

This design unit is implemented in usb​_clk.sv

This file depends on: usb_osc.sv

Description

of usb_clk

Parameters

NameTypeDefault ValueDescription
USB​_EN​_RDLYtime5us
USB​_VAL​_RDLYtime50ms
USB​_VAL​_FDLYtime80ns

Ports

NameDirectionTypeDescription
clk​_src​_usb​_en​_iinlogic

USB Source Clock Enable

usb​_ref​_pulse​_iinlogic

USB Reference Pulse

usb​_ref​_val​_iinlogic

USB Reference (Pulse) Valid

clk​_usb​_pd​_niinlogic

USB Clock Power-down

rst​_usb​_clk​_niinlogic

USB Clock Logic reset

vcore​_pok​_h​_iinlogic

VCORE POK @3.3V (for OSC)

clk​_src​_usb​_ooutlogic

USB Source Clock

clk​_src​_usb​_val​_ooutlogic

USB Source Clock Valid

Instantiations

Block Diagram

Module usbdev

This design unit is implemented in usbdev.sv

This file depends on: usbdev_pkg.sv, usbdev_reg_pkg.sv, usbdev_iomux.sv, prim_intr_hw.sv, tlul_pkg.sv, prim_fifo_async.sv, prim_ram_2p_async_adv.sv, tlul_adapter_sram.sv, prim_flop_2sync.sv, prim_pulse_sync.sv, usbdev_reg_top.sv, usbdev_flop_2syncpulse.sv, usbdev_usbif.sv

Parameters

NameTypeDefault ValueDescription
SramDwint32

Places packing bytes to SRAM assume this

SramDepthint512

2kB, SRAM Width is DW

MaxPktSizeByteint64
SramAwint$clog2(SramDepth)
SizeWidthint$clog2(MaxPktSizeByte)
NBufint(SramDepth * SramDw) / (MaxPktSizeByte * 8)
NBufWidthint$clog2(NBuf)
AVFifoWidthintNBufWidth

AV fifo just stores buffer numbers

AVFifoDepthint4
RXFifoWidthintNBufWidth + (1+SizeWidth) + 4 + 1

RX fifo stores buf# + size(0-MaxPktSizeByte) + EP# + Type

RXFifoDepthint4

Ports

NameDirectionTypeDescription
clk​_iinlogic
rst​_niinlogic
clk​_aon​_iinlogic
rst​_aon​_niinlogic
clk​_usb​_48mhz​_iinlogic

use usb_ prefix for signals in this clk

rst​_usb​_48mhz​_niinlogic

async reset, with relase sync to clk_usb_48_mhz_i

tl​_iintl_h2d_t

Register interface

tl​_oouttl_d2h_t
cio​_d​_iinlogic

differential

cio​_dp​_iinlogic

single-ended, can be used in differential mode to detect SE0

cio​_dn​_iinlogic

single-ended, can be used in differential mode to detect SE0

cio​_d​_ooutlogic

Data outputs

cio​_d​_en​_ooutlogic
cio​_dp​_ooutlogic
cio​_dp​_en​_ooutlogic
cio​_dn​_ooutlogic
cio​_dn​_en​_ooutlogic
cio​_sense​_iinlogic

Non-data I/O

cio​_se0​_ooutlogic
cio​_se0​_en​_ooutlogic
cio​_dp​_pullup​_ooutlogic
cio​_dp​_pullup​_en​_ooutlogic
cio​_dn​_pullup​_ooutlogic
cio​_dn​_pullup​_en​_ooutlogic
cio​_suspend​_ooutlogic
cio​_suspend​_en​_ooutlogic
cio​_tx​_mode​_se​_ooutlogic
cio​_tx​_mode​_se​_en​_ooutlogic
usb​_out​_of​_rst​_ooutlogic

Direct pinmux aon detect connections

usb​_aon​_wake​_en​_ooutlogic
usb​_aon​_wake​_ack​_ooutlogic
usb​_suspend​_ooutlogic
usb​_state​_debug​_iinawk_state_t

Debug info from wakeup module

usb​_ref​_val​_ooutlogic

SOF reference for clock calibration

usb​_ref​_pulse​_ooutlogic
intr​_pkt​_received​_ooutlogic

Packet received

intr​_pkt​_sent​_ooutlogic

Packet sent

intr​_connected​_ooutlogic
intr​_disconnected​_ooutlogic
intr​_host​_lost​_ooutlogic
intr​_link​_reset​_ooutlogic
intr​_link​_suspend​_ooutlogic
intr​_link​_resume​_ooutlogic
intr​_av​_empty​_ooutlogic
intr​_rx​_full​_ooutlogic
intr​_av​_overflow​_ooutlogic
intr​_link​_in​_err​_ooutlogic
intr​_link​_out​_err​_ooutlogic
intr​_rx​_crc​_err​_ooutlogic
intr​_rx​_pid​_err​_ooutlogic
intr​_rx​_bitstuff​_err​_ooutlogic
intr​_frame​_ooutlogic

Instantiations

Block Diagram

Package usbdev​_pkg

This design unit is implemented in usbdev​_pkg.sv

Package uvm​_pkg

This design unit is implemented in uvm​_pkg.sv

Classes

Virtual class uvm​_coreservice​_t

    Fields Summary
    TypeNameDescription
    uvm_default_coreservice_tinst
    Method Summary
    TypeMethodDescription
    uvm_factoryget​_factory()
    voidset​_factory(uvm_factory f)
    uvm_report_serverget​_report​_server()
    voidset​_report​_server(uvm_report_server server)
    uvm_tr_databaseget​_default​_tr​_database()
    voidset​_default​_tr​_database(uvm_tr_database db)
    voidset​_component​_visitor(uvm_visitor v)
    uvm_visitorget​_component​_visitor()
    uvm_rootget​_root()
    uvm_coreservice_tget()

    get

Class uvm​_default​_coreservice​_t

  • Extends: uvm​_coreservice​_t

  • Description

    Class: uvm_default_coreservice_t

    uvm_default_coreservice_t provides a default implementation of the uvm_coreservice_t API. It instantiates uvm_default_factory, uvm_default_report_server, uvm_root.

    Fields Summary
    TypeNameDescription
    uvm_factoryfactory
    uvm_tr_databasetr​_database
    uvm_report_serverreport​_server
    uvm_visitor​_visitor
    Method Summary
    TypeMethodDescription
    uvm_factoryget​_factory()
    voidset​_factory(uvm_factory f)
    uvm_tr_databaseget​_default​_tr​_database()
    voidset​_default​_tr​_database(uvm_tr_database db)
    uvm_report_serverget​_report​_server()
    voidset​_report​_server(uvm_report_server server)
    uvm_rootget​_root()
    voidset​_component​_visitor(uvm_visitor v)
    uvm_visitorget​_component​_visitor()

Virtual class uvm​_void

    Class uvm​_scope​_stack

      Fields Summary
      TypeNameDescription
      stringm​_arg
      string[]m​_stack
      Method Summary
      TypeMethodDescription
      intdepth()
      stringget()
      stringget​_arg()
      voidset(string s)
      voiddown(string s)
      voiddown​_element(int element)
      voidup​_element()
      voidup(byte separator)
      voidset​_arg(string arg)
      voidset​_arg​_element(string arg, int ele)
      voidunset​_arg(string arg)

    Class uvm​_status​_container

      Fields Summary
      TypeNameDescription
      bitclone

      The clone setting is used by the set/get config to know if cloning is on.

      bitwarning

      Information variables used by the macro functions for storage.

      bitstatus
      uvm_bitstream_tbitstream
      intintv
      intelement
      stringstringv
      stringscratch1
      stringscratch2
      stringkey
      uvm_objectobject
      bitarray​_warning​_done
      bit[]field​_array
      bitprint​_matches
      uvm_scope_stackscope

      The scope stack is used for messages that are emitted by policy classes.

      bit[]cycle​_check

      Used for checking cycles. When a data function is entered, if the depth is non-zero, then then the existeance of the object in the map means that a cycle has occured and the function should immediately exit. When the function exits, it should reset the cycle map so that there is no memory leak.

      uvm_comparercomparer

      These are the policy objects currently in use. The policy object gets set when a function starts up. The macros use this.

      uvm_packerpacker
      uvm_recorderrecorder
      uvm_printerprinter
      uvm_object[]m​_uvm​_cycle​_scopes

      utility function used to perform a cycle check when config setting are pushed to uvm_objects. the function has to look at the current object stack representing the call stack of all __m_uvm_field_automation() invocations. it is a only a cycle if the previous __m_uvm_field_automation call scope is not identical with the current scope AND the scope is already present in the object stack

      Method Summary
      TypeMethodDescription
      voiddo​_field​_check(string field, uvm_object obj)
      stringget​_function​_type(int what)
      stringget​_full​_scope​_arg()
      bitm​_do​_cycle​_check(uvm_object scope)

    Class uvm​_seed​_map

      Description

      Class- uvm_seed_map

      This map is a seed map that can be used to update seeds. The update is done automatically by the seed hashing routine. The seed_table_lookup uses an instance name lookup and the seed_table inside a given map uses a type name for the lookup.

      Fields Summary
      TypeNameDescription
      int[]seed​_table
      int[]count

    Class uvm​_utils

      Method Summary
      TypeMethodDescription
      types_tfind​_all(uvm_component start)
      TYPEfind(uvm_component start)
      TYPEcreate​_type​_by​_name(string type_name, string contxt)
      TYPEget​_config(uvm_component comp, bit is_fatal)

    Virtual class uvm​_object

    • Extends: uvm​_void

    • Fields Summary
      TypeNameDescription
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      Method Summary
      TypeMethodDescription
      uvm_objectnew(string name)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()

    Class uvm​_pool

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      this_typem​_global​_pool
      T[]pool
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      this_typeget​_global​_pool()
      Tget​_global(KEY key)
      Tget(KEY key)
      voidadd(KEY key, T item)
      intnum()
      voiddelete(KEY key)
      intexists(KEY key)
      intfirst(KEY key)
      intlast(KEY key)
      intnext(KEY key)
      intprev(KEY key)
      uvm_objectcreate(string name)
      stringget​_type​_name()
      voiddo​_copy(uvm_object rhs)
      voiddo​_print(uvm_printer printer)

    Class uvm​_object​_string​_pool

      Fields Summary
      TypeNameDescription
      this_typem​_global​_pool
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      T[]pool
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      stringget​_type​_name()
      this_typeget​_global​_pool()
      Tget​_global(string key)
      Tget(string key)
      voiddelete(string key)
      voiddo​_print(uvm_printer printer)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      voidadd(KEY key, T item)
      intnum()
      intexists(KEY key)
      intfirst(KEY key)
      intlast(KEY key)
      intnext(KEY key)
      intprev(KEY key)

    Class uvm​_queue

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      this_typem​_global​_queue
      T[]queue
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      this_typeget​_global​_queue()
      Tget​_global(int index)
      Tget(int index)
      intsize()
      voidinsert(int index, T item)
      voiddelete(int index)
      Tpop​_front()
      Tpop​_back()
      voidpush​_front(T item)
      voidpush​_back(T item)
      uvm_objectcreate(string name)
      stringget​_type​_name()
      voiddo​_copy(uvm_object rhs)
      stringconvert2string()

    Class uvm​_factory​_queue​_class

      Description

      Instance overrides by requested type lookup

      Fields Summary
      TypeNameDescription
      uvm_factory_override[]queue

    Virtual class uvm​_factory

      Method Summary
      TypeMethodDescription
      uvm_factoryget()
      voidregister(uvm_object_wrapper obj)
      voidset​_inst​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path)
      voidset​_inst​_override​_by​_name(string original_type_name, string override_type_name, string full_inst_path)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_type​_override​_by​_name(string original_type_name, string override_type_name, bit replace)
      uvm_objectcreate​_object​_by​_type(uvm_object_wrapper requested_type, string parent_inst_path, string name)
      uvm_componentcreate​_component​_by​_type(uvm_object_wrapper requested_type, string parent_inst_path, string name, uvm_component parent)
      uvm_objectcreate​_object​_by​_name(string requested_type_name, string parent_inst_path, string name)
      uvm_componentcreate​_component​_by​_name(string requested_type_name, string parent_inst_path, string name, uvm_component parent)
      voiddebug​_create​_by​_type(uvm_object_wrapper requested_type, string parent_inst_path, string name)
      voiddebug​_create​_by​_name(string requested_type_name, string parent_inst_path, string name)
      uvm_object_wrapperfind​_override​_by​_type(uvm_object_wrapper requested_type, string full_inst_path)
      uvm_object_wrapperfind​_override​_by​_name(string requested_type_name, string full_inst_path)
      uvm_object_wrapperfind​_wrapper​_by​_name(string type_name)
      voidprint(int all_types)

    Class uvm​_default​_factory

    • Extends: uvm​_factory

    • Fields Summary
      TypeNameDescription
      bit[]m​_types
      bit[]m​_lookup​_strs
      uvm_object_wrapper[]m​_type​_names
      uvm_factory_override[]m​_type​_overrides
      uvm_factory_queue_class[]m​_inst​_override​_queues
      uvm_factory_queue_class[]m​_inst​_override​_name​_queues
      uvm_factory_override[]m​_wildcard​_inst​_overrides
      uvm_factory_override[]m​_override​_info
      bitm​_debug​_pass
      Method Summary
      TypeMethodDescription
      voidregister(uvm_object_wrapper obj)
      voidset​_inst​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path)
      voidset​_inst​_override​_by​_name(string original_type_name, string override_type_name, string full_inst_path)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_type​_override​_by​_name(string original_type_name, string override_type_name, bit replace)
      uvm_objectcreate​_object​_by​_type(uvm_object_wrapper requested_type, string parent_inst_path, string name)
      uvm_componentcreate​_component​_by​_type(uvm_object_wrapper requested_type, string parent_inst_path, string name, uvm_component parent)
      uvm_objectcreate​_object​_by​_name(string requested_type_name, string parent_inst_path, string name)
      uvm_componentcreate​_component​_by​_name(string requested_type_name, string parent_inst_path, string name, uvm_component parent)
      voiddebug​_create​_by​_type(uvm_object_wrapper requested_type, string parent_inst_path, string name)
      voiddebug​_create​_by​_name(string requested_type_name, string parent_inst_path, string name)
      uvm_object_wrapperfind​_override​_by​_type(uvm_object_wrapper requested_type, string full_inst_path)
      uvm_object_wrapperfind​_override​_by​_name(string requested_type_name, string full_inst_path)
      uvm_object_wrapperfind​_wrapper​_by​_name(string type_name)
      voidprint(int all_types)
      voidm​_debug​_create(string requested_type_name, uvm_object_wrapper requested_type, string parent_inst_path, string name)
      voidm​_debug​_display(string requested_type_name, uvm_object_wrapper result, string full_inst_path)
      bitm​_has​_wildcard(string nm)
      bitcheck​_inst​_override​_exists(uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path)

    Virtual class uvm​_object​_wrapper

      Method Summary
      TypeMethodDescription
      uvm_objectcreate​_object(string name)
      uvm_componentcreate​_component(string name, uvm_component parent)
      stringget​_type​_name()

    Class uvm​_factory​_override

      Fields Summary
      TypeNameDescription
      stringfull​_inst​_path
      stringorig​_type​_name
      stringovrd​_type​_name
      bitselected
      intused
      uvm_object_wrapperorig​_type
      uvm_object_wrapperovrd​_type
      Method Summary
      TypeMethodDescription
      logicnew(string full_inst_path, string orig_type_name, uvm_object_wrapper orig_type, uvm_object_wrapper ovrd_type)

    Class uvm​_component​_registry

    • Extends: uvm​_object​_wrapper

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      this_typeme
      Method Summary
      TypeMethodDescription
      uvm_componentcreate​_component(string name, uvm_component parent)
      stringget​_type​_name()
      this_typeget()
      Tcreate(string name, uvm_component parent, string contxt)
      voidset​_type​_override(uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent)

    Class uvm​_object​_registry

    • Extends: uvm​_object​_wrapper

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      this_typeme
      Method Summary
      TypeMethodDescription
      uvm_objectcreate​_object(string name)
      stringget​_type​_name()
      this_typeget()
      Tcreate(string name, uvm_component parent, string contxt)
      voidset​_type​_override(uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override(uvm_object_wrapper override_type, string inst_path, uvm_component parent)

    Class uvm​_spell​_chkr

      Description

      class uvm_spell_chkr

      Fields Summary
      TypeNameDescription
      intmax
      Method Summary
      TypeMethodDescription
      bitcheck(tab_t strtab, string s)
      intlevenshtein​_distance(string s, string t)
      intminimum(int a, int b, int c)

    Class uvm​_resource​_types

      Description

      Class: uvm_resource_types

      Provides typedefs and enums used throughout the resources facility. This class has no members or methods, only typedefs. It's used in lieu of package-scope types. When needed, other classes can use these types by prefixing their usage with uvm_resource_types::. E.g.

      | uvm_resource_types::rsrc_q_t queue;

    Class uvm​_resource​_options

      Description

      Options include:

      • auditing: on/off

        The default for auditing is on. You may wish to turn it off to for performance reasons. With auditing off memory is not consumed for storage of auditing information and time is not spent collecting and storing auditing information. Of course, during the period when auditing is off no audit trail information is available

      Fields Summary
      TypeNameDescription
      bitauditing
      Method Summary
      TypeMethodDescription
      voidturn​_on​_auditing()
      voidturn​_off​_auditing()
      bitis​_auditing()

    Virtual class uvm​_resource​_base

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringscope
      bitmodified
      bitread​_only
      access_t[]access
      intprecedence
      intdefault​_precedence
      Method Summary
      TypeMethodDescription
      logicnew(string name, string s)
      uvm_resource_baseget​_type​_handle()
      voidset​_read​_only()
      voidset​_read​_write()
      bitis​_read​_only()

      Function: is_read_only

      Returns one if this resource has been set to read-only, zero otherwise

      voidwait​_modified()
      voidset​_scope(string s)

      Function: set_scope

      Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored.

      stringget​_scope()

      Function: get_scope

      Retrieve the regular expression string that identifies the set of scopes over which this resource is visible.

      bitmatch​_scope(string s)

      Function: match_scope

      Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise.

      voidset​_priority(priority_e pri)
      stringconvert2string()
      voiddo​_print(uvm_printer printer)
      voidrecord​_read​_access(uvm_object accessor)
      voidrecord​_write​_access(uvm_object accessor)
      voidprint​_accessors()
      voidinit​_access​_record(access_t access_record)

      Function: init_access_record

      Initialize a new access record

    Class get​_t

      Description

      Class - get_t

      Instances of get_t are stored in the history list as a record of each get. Failed gets are indicated with rsrc set to ~null~. This is part of the audit trail facility for resources.

      Fields Summary
      TypeNameDescription
      stringname
      stringscope
      uvm_resource_basersrc
      timet

    Class uvm​_resource​_pool

      Fields Summary
      TypeNameDescription
      uvm_resource_poolrp
      rsrc_q_t[]rtab
      rsrc_q_t[]ttab
      get_t[]get​_record

      history of gets

      Method Summary
      TypeMethodDescription
      logicnew()
      uvm_resource_poolget()
      bitspell​_check(string s)
      voidset(uvm_resource_base rsrc, override_t override)

      Function: set

      Add a new resource to the resource pool. The resource is inserted into both the name map and type map so it can be located by either.

      An object creates a resources and ~sets~ it into the resource pool. Later, other objects that want to access the resource must ~get~ it from the pool

      Overrides can be specified using this interface. Either a name override, a type override or both can be specified. If an override is specified then the resource is entered at the front of the queue instead of at the back. It is not recommended that users specify the override parameter directly, rather they use the <set_override>, <set_name_override>, or <set_type_override> functions.

      voidset​_override(uvm_resource_base rsrc)
      voidset​_name​_override(uvm_resource_base rsrc)
      voidset​_type​_override(uvm_resource_base rsrc)
      voidpush​_get​_record(string name, string scope, uvm_resource_base rsrc)
      voiddump​_get​_records()
      rsrc_q_tlookup​_name(string scope, string name, uvm_resource_base type_handle, bit rpterr)
      uvm_resource_baseget​_highest​_precedence(rsrc_q_t q)
      voidsort​_by​_precedence(rsrc_q_t q)
      uvm_resource_baseget​_by​_name(string scope, string name, uvm_resource_base type_handle, bit rpterr)
      rsrc_q_tlookup​_type(string scope, uvm_resource_base type_handle)
      uvm_resource_baseget​_by​_type(string scope, uvm_resource_base type_handle)
      rsrc_q_tlookup​_regex​_names(string scope, string name, uvm_resource_base type_handle)
      rsrc_q_tlookup​_regex(string re, string scope)
      rsrc_q_tlookup​_scope(string scope)
      voidset​_priority​_queue(uvm_resource_base rsrc, rsrc_q_t q, priority_e pri)
      voidset​_priority​_type(uvm_resource_base rsrc, priority_e pri)
      voidset​_priority​_name(uvm_resource_base rsrc, priority_e pri)
      voidset​_priority(uvm_resource_base rsrc, priority_e pri)
      rsrc_q_tfind​_unused​_resources()
      voidprint​_resources(rsrc_q_t rq, bit audit)
      voiddump(bit audit)

    Class uvm​_resource

    • Extends: uvm​_resource​_base

    • Fields Summary
      TypeNameDescription
      this_typemy​_type
      Tval
      m_uvm_resource_converterm​_r2s
      Method Summary
      TypeMethodDescription
      m_uvm_resource_converterm​_get​_converter()
      voidm​_set​_converter(m_uvm_resource_converter r2s)
      logicnew(string name, string scope)
      stringconvert2string()
      this_typeget​_type()
      uvm_resource_baseget​_type​_handle()
      voidset()
      voidset​_override(override_t override)
      this_typeget​_by​_name(string scope, string name, bit rpterr)
      this_typeget​_by​_type(string scope, uvm_resource_base type_handle)
      Tread(uvm_object accessor)
      voidwrite(T t, uvm_object accessor)
      voidset​_priority(priority_e pri)
      this_typeget​_highest​_precedence(rsrc_q_t q)

    Class m​_uvm​_resource​_converter

      Description

      CLASS- uvm_resource_converter#(T)

      The uvm_resource_converter class provides a policy object for doing convertion from resource value to string.

      Method Summary
      TypeMethodDescription
      stringconvert2string(T val)

    Class m​_uvm​_resource​_default​_converter

      Fields Summary
      TypeNameDescription
      m_uvm_resource_default_converterm​_singleton
      stringm​_name
      Method Summary
      TypeMethodDescription
      stringconvert2string(T val)
      logicnew()
      bitregister(string typename)

    Class m​_uvm​_resource​_convert2string​_converter

      Fields Summary
      TypeNameDescription
      m_uvm_resource_convert2string_converterm​_singleton
      Method Summary
      TypeMethodDescription
      stringconvert2string(T val)
      logicnew()
      bitregister()

    Class m​_uvm​_resource​_sprint​_converter

      Fields Summary
      TypeNameDescription
      m_uvm_resource_sprint_converterm​_singleton
      Method Summary
      TypeMethodDescription
      stringconvert2string(T val)
      logicnew()
      bitregister()

    Class m​_uvm​_resource​_default​_converters

      Description

      CLASS- m_uvm_resource_default_converters Singleton used to register default resource value converters for the built-in singular types.

      Fields Summary
      TypeNameDescription
      bitm​_singleton
      Method Summary
      TypeMethodDescription
      logicnew()
      bitregister()

    Class uvm​_int​_rsrc

      Description

      uvm_int_rsrc

      specialization of uvm_resource #(T) for T = int

      Fields Summary
      TypeNameDescription
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      stringscope
      bitmodified
      bitread​_only
      access_t[]access
      intprecedence
      intdefault​_precedence
      uvm_resourcemy​_type
      unknownval
      m_uvm_resource_converterm​_r2s
      Method Summary
      TypeMethodDescription
      logicnew(string name, string s)
      stringconvert2string()
      this_subtypeget​_by​_name(string scope, string name, bit rpterr)
      this_subtypeget​_by​_type(string scope, uvm_resource_base type_handle)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_resourceget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_resource_baseget​_type​_handle()
      voidset​_read​_only()
      voidset​_read​_write()
      bitis​_read​_only()

      Function: is_read_only

      Returns one if this resource has been set to read-only, zero otherwise

      voidwait​_modified()
      voidset​_scope(string s)

      Function: set_scope

      Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored.

      stringget​_scope()

      Function: get_scope

      Retrieve the regular expression string that identifies the set of scopes over which this resource is visible.

      bitmatch​_scope(string s)

      Function: match_scope

      Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise.

      voidset​_priority(priority_e pri)
      voidrecord​_read​_access(uvm_object accessor)
      voidrecord​_write​_access(uvm_object accessor)
      voidprint​_accessors()
      voidinit​_access​_record(access_t access_record)

      Function: init_access_record

      Initialize a new access record

      m_uvm_resource_converterm​_get​_converter()
      voidm​_set​_converter(m_uvm_resource_converter r2s)
      voidset()
      voidset​_override(override_t override)
      unknownread(uvm_object accessor)
      voidwrite(T t, uvm_object accessor)
      uvm_resourceget​_highest​_precedence(rsrc_q_t q)

    Class uvm​_string​_rsrc

      Description

      uvm_string_rsrc

      specialization of uvm_resource #(T) for T = string

      Fields Summary
      TypeNameDescription
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      stringscope
      bitmodified
      bitread​_only
      access_t[]access
      intprecedence
      intdefault​_precedence
      uvm_resourcemy​_type
      unknownval
      m_uvm_resource_converterm​_r2s
      Method Summary
      TypeMethodDescription
      logicnew(string name, string s)
      stringconvert2string()
      this_subtypeget​_by​_name(string scope, string name, bit rpterr)
      this_subtypeget​_by​_type(string scope, uvm_resource_base type_handle)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_resourceget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_resource_baseget​_type​_handle()
      voidset​_read​_only()
      voidset​_read​_write()
      bitis​_read​_only()

      Function: is_read_only

      Returns one if this resource has been set to read-only, zero otherwise

      voidwait​_modified()
      voidset​_scope(string s)

      Function: set_scope

      Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored.

      stringget​_scope()

      Function: get_scope

      Retrieve the regular expression string that identifies the set of scopes over which this resource is visible.

      bitmatch​_scope(string s)

      Function: match_scope

      Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise.

      voidset​_priority(priority_e pri)
      voidrecord​_read​_access(uvm_object accessor)
      voidrecord​_write​_access(uvm_object accessor)
      voidprint​_accessors()
      voidinit​_access​_record(access_t access_record)

      Function: init_access_record

      Initialize a new access record

      m_uvm_resource_converterm​_get​_converter()
      voidm​_set​_converter(m_uvm_resource_converter r2s)
      voidset()
      voidset​_override(override_t override)
      unknownread(uvm_object accessor)
      voidwrite(T t, uvm_object accessor)
      uvm_resourceget​_highest​_precedence(rsrc_q_t q)

    Class uvm​_obj​_rsrc

      Description

      uvm_obj_rsrc

      specialization of uvm_resource #(T) for T = uvm_object

      Fields Summary
      TypeNameDescription
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      stringscope
      bitmodified
      bitread​_only
      access_t[]access
      intprecedence
      intdefault​_precedence
      uvm_resourcemy​_type
      uvm_objectval
      m_uvm_resource_converterm​_r2s
      Method Summary
      TypeMethodDescription
      logicnew(string name, string s)
      this_subtypeget​_by​_name(string scope, string name, bit rpterr)
      this_subtypeget​_by​_type(string scope, uvm_resource_base type_handle)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_resourceget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_resource_baseget​_type​_handle()
      voidset​_read​_only()
      voidset​_read​_write()
      bitis​_read​_only()

      Function: is_read_only

      Returns one if this resource has been set to read-only, zero otherwise

      voidwait​_modified()
      voidset​_scope(string s)

      Function: set_scope

      Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored.

      stringget​_scope()

      Function: get_scope

      Retrieve the regular expression string that identifies the set of scopes over which this resource is visible.

      bitmatch​_scope(string s)

      Function: match_scope

      Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise.

      voidset​_priority(priority_e pri)
      voidrecord​_read​_access(uvm_object accessor)
      voidrecord​_write​_access(uvm_object accessor)
      voidprint​_accessors()
      voidinit​_access​_record(access_t access_record)

      Function: init_access_record

      Initialize a new access record

      m_uvm_resource_converterm​_get​_converter()
      voidm​_set​_converter(m_uvm_resource_converter r2s)
      voidset()
      voidset​_override(override_t override)
      uvm_objectread(uvm_object accessor)
      voidwrite(T t, uvm_object accessor)
      uvm_resourceget​_highest​_precedence(rsrc_q_t q)

    Class uvm​_bit​_rsrc

      Description

      uvm_bit_rsrc

      specialization of uvm_resource #(T) for T = vector of bits

      Fields Summary
      TypeNameDescription
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      stringscope
      bitmodified
      bitread​_only
      access_t[]access
      intprecedence
      intdefault​_precedence
      uvm_resourcemy​_type
      unknownval
      m_uvm_resource_converterm​_r2s
      Method Summary
      TypeMethodDescription
      logicnew(string name, string s)
      stringconvert2string()
      this_subtypeget​_by​_name(string scope, string name, bit rpterr)
      this_subtypeget​_by​_type(string scope, uvm_resource_base type_handle)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_resourceget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_resource_baseget​_type​_handle()
      voidset​_read​_only()
      voidset​_read​_write()
      bitis​_read​_only()

      Function: is_read_only

      Returns one if this resource has been set to read-only, zero otherwise

      voidwait​_modified()
      voidset​_scope(string s)

      Function: set_scope

      Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored.

      stringget​_scope()

      Function: get_scope

      Retrieve the regular expression string that identifies the set of scopes over which this resource is visible.

      bitmatch​_scope(string s)

      Function: match_scope

      Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise.

      voidset​_priority(priority_e pri)
      voidrecord​_read​_access(uvm_object accessor)
      voidrecord​_write​_access(uvm_object accessor)
      voidprint​_accessors()
      voidinit​_access​_record(access_t access_record)

      Function: init_access_record

      Initialize a new access record

      m_uvm_resource_converterm​_get​_converter()
      voidm​_set​_converter(m_uvm_resource_converter r2s)
      voidset()
      voidset​_override(override_t override)
      unknownread(uvm_object accessor)
      voidwrite(T t, uvm_object accessor)
      uvm_resourceget​_highest​_precedence(rsrc_q_t q)

    Class uvm​_byte​_rsrc

      Description

      uvm_byte_rsrc

      specialization of uvm_resource #T() for T = vector of bytes

      Fields Summary
      TypeNameDescription
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      stringscope
      bitmodified
      bitread​_only
      access_t[]access
      intprecedence
      intdefault​_precedence
      uvm_resourcemy​_type
      unknownval
      m_uvm_resource_converterm​_r2s
      Method Summary
      TypeMethodDescription
      logicnew(string name, string s)
      stringconvert2string()
      this_subtypeget​_by​_name(string scope, string name, bit rpterr)
      this_subtypeget​_by​_type(string scope, uvm_resource_base type_handle)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_resourceget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_resource_baseget​_type​_handle()
      voidset​_read​_only()
      voidset​_read​_write()
      bitis​_read​_only()

      Function: is_read_only

      Returns one if this resource has been set to read-only, zero otherwise

      voidwait​_modified()
      voidset​_scope(string s)

      Function: set_scope

      Set the value of the regular expression that identifies the set of scopes over which this resource is visible. If the supplied argument is a glob it will be converted to a regular expression before it is stored.

      stringget​_scope()

      Function: get_scope

      Retrieve the regular expression string that identifies the set of scopes over which this resource is visible.

      bitmatch​_scope(string s)

      Function: match_scope

      Using the regular expression facility, determine if this resource is visible in a scope. Return one if it is, zero otherwise.

      voidset​_priority(priority_e pri)
      voidrecord​_read​_access(uvm_object accessor)
      voidrecord​_write​_access(uvm_object accessor)
      voidprint​_accessors()
      voidinit​_access​_record(access_t access_record)

      Function: init_access_record

      Initialize a new access record

      m_uvm_resource_converterm​_get​_converter()
      voidm​_set​_converter(m_uvm_resource_converter r2s)
      voidset()
      voidset​_override(override_t override)
      unknownread(uvm_object accessor)
      voidwrite(T t, uvm_object accessor)
      uvm_resourceget​_highest​_precedence(rsrc_q_t q)

    Class uvm​_resource​_db

      Description

      class: uvm_resource_db

      All of the functions in uvm_resource_db#(T) are static, so they must be called using the :: operator. For example:

      | uvm_resource_db#(int)::set("A", "*", 17, this);

      The parameter value "int" identifies the resource type as uvm_resource#(int). Thus, the type of the object in the resource container is int. This maintains the type-safety characteristics of resource operations.

      Method Summary
      TypeMethodDescription
      logicnew()
      rsrc_tget​_by​_type(string scope)
      rsrc_tget​_by​_name(string scope, string name, bit rpterr)
      rsrc_tset​_default(string scope, string name)
      voidm​_show​_msg(string id, string rtype, string action, string scope, string name, uvm_object accessor, rsrc_t rsrc)
      voidset(string scope, string name, T val, uvm_object accessor)
      voidset​_anonymous(string scope, T val, uvm_object accessor)
      voidset​_override(string scope, string name, T val, uvm_object accessor)
      voidset​_override​_type(string scope, string name, T val, uvm_object accessor)
      voidset​_override​_name(string scope, string name, T val, uvm_object accessor)
      bitread​_by​_name(string scope, string name, T val, uvm_object accessor)
      bitread​_by​_type(string scope, T val, uvm_object accessor)
      bitwrite​_by​_name(string scope, string name, T val, uvm_object accessor)
      bitwrite​_by​_type(string scope, T val, uvm_object accessor)
      voiddump()

    Class uvm​_resource​_db​_options

      Description

      Options include:

      • tracing: on/off

        The default for tracing is off.

      Fields Summary
      TypeNameDescription
      bitready
      bittracing
      Method Summary
      TypeMethodDescription
      voidturn​_on​_tracing()
      voidturn​_off​_tracing()
      bitis​_tracing()
      voidinit()

    Class m​_uvm​_waiter

      Description

      Internal class for config waiters

      Fields Summary
      TypeNameDescription
      stringinst​_name
      stringfield​_name
      eventtrigger
      Method Summary
      TypeMethodDescription
      logicnew(string inst_name, string field_name)

    Class uvm​_config​_db

      Description

      class: uvm_config_db

      All of the functions in uvm_config_db#(T) are static, so they must be called using the :: operator. For example:

      | uvm_config_db#(int)::set(this, "*", "A");

      The parameter value "int" identifies the configuration type as an int property.

      The and methods provide the same API and semantics as the set/get_config_* functions in <uvm_component>.

      Fields Summary
      TypeNameDescription
      uvm_pool[]m​_rsc
      uvm_queue[]m​_waiters
      Method Summary
      TypeMethodDescription
      bitget(uvm_component cntxt, string inst_name, string field_name, T value)
      voidset(uvm_component cntxt, string inst_name, string field_name, T value)
      bitexists(uvm_component cntxt, string inst_name, string field_name, bit spell_chk)
      voidwait​_modified(uvm_component cntxt, string inst_name, string field_name)
      uvm_resourceget​_by​_type(string scope)
      uvm_resourceget​_by​_name(string scope, string name, bit rpterr)
      uvm_resourceset​_default(string scope, string name)
      voidm​_show​_msg(string id, string rtype, string action, string scope, string name, uvm_object accessor, rsrc_t rsrc)
      voidset​_anonymous(string scope, T val, uvm_object accessor)
      voidset​_override(string scope, string name, T val, uvm_object accessor)
      voidset​_override​_type(string scope, string name, T val, uvm_object accessor)
      voidset​_override​_name(string scope, string name, T val, uvm_object accessor)
      bitread​_by​_name(string scope, string name, T val, uvm_object accessor)
      bitread​_by​_type(string scope, T val, uvm_object accessor)
      bitwrite​_by​_name(string scope, string name, T val, uvm_object accessor)
      bitwrite​_by​_type(string scope, T val, uvm_object accessor)
      voiddump()

    Class uvm​_config​_db​_options

      Description

      Options include:

      • tracing: on/off

        The default for tracing is off.

      Fields Summary
      TypeNameDescription
      bitready
      bittracing
      Method Summary
      TypeMethodDescription
      voidturn​_on​_tracing()
      voidturn​_off​_tracing()
      bitis​_tracing()
      voidinit()

    Virtual class uvm​_printer

      Description

      Class: uvm_printer

      The uvm_printer class provides an interface for printing <uvm_objects> in various formats. Subtypes of uvm_printer implement different print formats, or policies.

      A user-defined printer format can be created, or one of the following four built-in printers can be used:

      • <uvm_printer> - provides base printer functionality; must be overridden.

      • <uvm_table_printer> - prints the object in a tabular form.

      • <uvm_tree_printer> - prints the object in a tree form.

      • <uvm_line_printer> - prints the information on a single line, but uses the same object separators as the tree printer.

      Printers have knobs that you use to control what and how information is printed. These knobs are contained in a separate knob class:

      • <uvm_printer_knobs> - common printer settings

      For convenience, global instances of each printer type are available for direct reference in your testbenches.

      • <uvm_default_tree_printer>

      • <uvm_default_line_printer>

      • <uvm_default_table_printer>

      • <uvm_default_printer> (set to default_table_printer by default)

      When <uvm_object::print> and <uvm_object::sprint> are called without specifying a printer, the <uvm_default_printer> is used.

      Fields Summary
      TypeNameDescription
      uvm_printer_knobsknobs

      Variable: knobs

      The knob object provides access to the variety of knobs associated with a specific printer instance.

      bit[]m​_array​_stack
      uvm_scope_stackm​_scope
      stringm​_string
      uvm_printer_row_info[]m​_rows
      Method Summary
      TypeMethodDescription
      voidprint​_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix, byte scope_separator, string type_name)
      voidprint​_int(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix, byte scope_separator, string type_name)
      voidprint​_field​_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix, byte scope_separator, string type_name)
      voidprint​_object(string name, uvm_object value, byte scope_separator)
      voidprint​_object​_header(string name, uvm_object value, byte scope_separator)
      voidprint​_string(string name, string value, byte scope_separator)
      voidprint​_time(string name, time value, byte scope_separator)
      voidprint​_real(string name, real value, byte scope_separator)
      voidprint​_generic(string name, string type_name, int size, string value, byte scope_separator)
      stringemit()
      stringformat​_row(uvm_printer_row_info row)
      stringformat​_header()
      stringformat​_footer()
      stringadjust​_name(string id, byte scope_separator)
      voidprint​_array​_header(string name, int size, string arraytype, byte scope_separator)
      voidprint​_array​_range(int min, int max)
      voidprint​_array​_footer(int size)
      bitistop()
      stringindex​_string(int index, string name)

    Class uvm​_table​_printer

    • Extends: uvm​_printer

    • Fields Summary
      TypeNameDescription
      intm​_max​_name
      intm​_max​_type
      intm​_max​_size
      intm​_max​_value
      Method Summary
      TypeMethodDescription
      uvm_table_printernew()
      stringemit()
      voidcalculate​_max​_widths()

    Class uvm​_tree​_printer

    • Extends: uvm​_printer

    • Fields Summary
      TypeNameDescription
      stringnewline
      Method Summary
      TypeMethodDescription
      uvm_tree_printernew()
      stringemit()

    Class uvm​_line​_printer

    Class uvm​_printer​_knobs

      Fields Summary
      TypeNameDescription
      bitheader
      bitfooter
      bitfull​_name
      bitidentifier
      bittype​_name
      bitsize
      intdepth
      bitreference
      intbegin​_elements
      intend​_elements
      stringprefix
      intindent
      bitshow​_root
      intmcd
      stringseparator
      bitshow​_radix
      uvm_radix_enumdefault​_radix
      stringdec​_radix
      stringbin​_radix
      stringoct​_radix
      stringunsigned​_radix
      stringhex​_radix
      intmax​_width

      Deprecated knobs, hereafter ignored

      stringtruncation
      intname​_width
      inttype​_width
      intsize​_width
      intvalue​_width
      bitsprint
      Method Summary
      TypeMethodDescription
      stringget​_radix​_str(uvm_radix_enum radix)

    Class uvm​_comparer

      Fields Summary
      TypeNameDescription
      uvm_recursion_policy_enumpolicy
      intshow​_max
      intverbosity
      uvm_severitysev
      stringmiscompares
      bitphysical
      bitabstract
      bitcheck​_type
      intresult
      intdepth

      current depth of objects

      uvm_object[]compare​_map
      uvm_scope_stackscope
      Method Summary
      TypeMethodDescription
      bitcompare​_field(string name, uvm_bitstream_t lhs, uvm_bitstream_t rhs, int size, uvm_radix_enum radix)
      bitcompare​_field​_int(string name, uvm_integral_t lhs, uvm_integral_t rhs, int size, uvm_radix_enum radix)
      bitcompare​_field​_real(string name, real lhs, real rhs)
      bitcompare​_object(string name, uvm_object lhs, uvm_object rhs)
      bitcompare​_string(string name, string lhs, string rhs)
      voidprint​_msg(string msg)
      voidprint​_rollup(uvm_object rhs, uvm_object lhs)

      Need this function because sformat doesn't support objects

      voidprint​_msg​_object(uvm_object lhs, uvm_object rhs)
      uvm_comparerinit()

    Class uvm​_packer

      Fields Summary
      TypeNameDescription
      bitphysical
      bitabstract
      bituse​_metadata
      bitbig​_endian
      bit[]bitstream

      local bits for (un)pack_bytes

      bit[]fabitstream

      field automation bits for (un)pack_bytes

      intcount

      used to count the number of packed bits

      uvm_scope_stackscope
      bitreverse​_order

      flip the bit order around

      bytebyte​_size

      set up bytesize for endianess

      intword​_size

      set up worksize for endianess

      bitnopack

      only count packable bits

      uvm_recursion_policy_enumpolicy
      uvm_pack_bitstream_tm​_bits
      intm​_packed​_size
      Method Summary
      TypeMethodDescription
      voidpack​_field(uvm_bitstream_t value, int size)
      voidpack​_field​_int(uvm_integral_t value, int size)
      voidpack​_bits(bit[] value, int size)
      voidpack​_bytes(byte[] value, int size)
      voidpack​_ints(int[] value, int size)
      voidpack​_string(string value)
      voidpack​_time(time value)
      voidpack​_real(real value)
      voidpack​_object(uvm_object value)
      bitis​_null()
      uvm_bitstream_tunpack​_field(int size)
      uvm_integral_tunpack​_field​_int(int size)
      voidunpack​_bits(bit[] value, int size)
      voidunpack​_bytes(byte[] value, int size)
      voidunpack​_ints(int[] value, int size)
      stringunpack​_string(int num_chars)
      timeunpack​_time()
      realunpack​_real()
      voidunpack​_object(uvm_object value)
      intget​_packed​_size()
      voidunpack​_object​_ext(uvm_object value)
      uvm_pack_bitstream_tget​_packed​_bits()
      bitget​_bit(int index)
      byteget​_byte(int index)
      intget​_int(int index)
      voidget​_bits(bit[] bits)
      voidget​_bytes(byte[] bytes)
      voidget​_ints(int[] ints)
      voidput​_bits(bit[] bitstream)
      voidput​_bytes(byte[] bytestream)
      voidput​_ints(int[] intstream)
      voidset​_packed​_size()
      voidindex​_error(int index, string id, int sz)
      bitenough​_bits(int needed, string id)
      voidreset()

    Virtual class uvm​_link​_base

    • Extends: uvm​_object

    • Description

      CLASS: uvm_link_base

      The ~uvm_link_base~ class presents a simple API for defining a link between any two objects.

      Using extensions of this class, a <uvm_tr_database> can determine the type of links being passed, without relying on "magic" string names.

      For example: | | virtual function void do_establish_link(uvm_link_base link); | uvm_parent_child_link pc_link; | uvm_cause_effect_link ce_link; | | if ($cast(pc_link, link)) begin | // Record the parent-child relationship | end | else if ($cast(ce_link, link)) begin | // Record the cause-effect relationship | end | else begin | // Unsupported relationship! | end | endfunction : do_establish_link

      Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new Constructor

      Parameters: name - Instance name

      voidset​_lhs(uvm_object lhs)

      Function: set_lhs Sets the left-hand-side of the link

      Triggers the <do_set_lhs> callback.

      uvm_objectget​_lhs()

      Function: get_lhs Gets the left-hand-side of the link

      Triggers the <do_get_lhs> callback

      voidset​_rhs(uvm_object rhs)

      Function: set_rhs Sets the right-hand-side of the link

      Triggers the <do_set_rhs> callback.

      uvm_objectget​_rhs()

      Function: get_rhs Gets the right-hand-side of the link

      Triggers the <do_get_rhs> callback

      voidset(uvm_object lhs, uvm_object rhs)

      Function: set Convenience method for setting both sides in one call.

      Triggers both the <do_set_rhs> and <do_set_lhs> callbacks.

      voiddo​_set​_lhs(uvm_object lhs)
      uvm_objectdo​_get​_lhs()
      voiddo​_set​_rhs(uvm_object rhs)
      uvm_objectdo​_get​_rhs()

    Class uvm​_parent​_child​_link

    • Extends: uvm​_link​_base

    • Fields Summary
      TypeNameDescription
      uvm_objectm​_lhs
      uvm_objectm​_rhs
      stringtype​_name
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new Constructor

      Parameters: name - Instance name

      uvm_parent_child_linkget​_link(uvm_object lhs, uvm_object rhs, string name)
      voiddo​_set​_lhs(uvm_object lhs)
      uvm_objectdo​_get​_lhs()
      voiddo​_set​_rhs(uvm_object rhs)
      uvm_objectdo​_get​_rhs()

    Class uvm​_cause​_effect​_link

    • Extends: uvm​_link​_base

    • Fields Summary
      TypeNameDescription
      uvm_objectm​_lhs
      uvm_objectm​_rhs
      stringtype​_name
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new Constructor

      Parameters: name - Instance name

      uvm_cause_effect_linkget​_link(uvm_object lhs, uvm_object rhs, string name)
      voiddo​_set​_lhs(uvm_object lhs)
      uvm_objectdo​_get​_lhs()
      voiddo​_set​_rhs(uvm_object rhs)
      uvm_objectdo​_get​_rhs()

    Class uvm​_related​_link

    • Extends: uvm​_link​_base

    • Fields Summary
      TypeNameDescription
      uvm_objectm​_lhs
      uvm_objectm​_rhs
      stringtype​_name
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new Constructor

      Parameters: name - Instance name

      uvm_related_linkget​_link(uvm_object lhs, uvm_object rhs, string name)
      voiddo​_set​_lhs(uvm_object lhs)
      uvm_objectdo​_get​_lhs()
      voiddo​_set​_rhs(uvm_object rhs)
      uvm_objectdo​_get​_rhs()

    Virtual class uvm​_tr​_database

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      bitm​_is​_opened
      bit[]m​_streams
      Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new Constructor

      Parameters: name - Instance name

      bitopen​_db()

      Function: open_db Open the backend connection to the database.

      If the database is already open, then this method will return 1.

      Otherwise, the method will call <do_open_db>, and return the result.

      bitclose​_db()

      Function: close_db Closes the backend connection to the database.

      Closing a database implicitly closes and frees all <uvm_tr_streams> within the database.

      If the database is already closed, then this method will return 1.

      Otherwise, this method will trigger a <do_close_db> call, and return the result.

      bitis​_open()

      Function: is_open Returns the open/closed status of the database.

      This method returns 1 if the database has been successfully opened, but not yet closed.

      uvm_tr_streamopen​_stream(string name, string scope, string type_name)

      Function: open_stream Provides a reference to a ~stream~ within the database.

      Parameters: name - A string name for the stream. This is the name associated with the stream in the database. scope - An optional scope for the stream. type_name - An optional name describing the type of records which will be created in this stream.

      The method returns a reference to a <uvm_tr_stream> object if successful, ~null~ otherwise.

      This method will trigger a <do_open_stream> call, and if a non ~null~ stream is returned, then <uvm_tr_stream::do_open> will be called.

      Streams can only be opened if the database is open (per <is_open>). Otherwise the request will be ignored, and ~null~ will be returned.

      voidm​_free​_stream(uvm_tr_stream stream)

      Function- m_free_stream Removes stream from the internal array

      logicget​_streams(uvm_tr_stream[] q)

      Function: get_streams Provides a queue of all streams within the database.

      Parameters: q - A reference to a queue of <uvm_tr_stream>s

      The ~get_streams~ method returns the size of the queue, such that the user can conditionally process the elements.

      | uvm_tr_stream stream_q$; | if (my_db.get_streams(stream_q)) begin | // Process the queue... | end

      voidestablish​_link(uvm_link_base link)

      Function: establish_link Establishes a ~link~ between two elements in the database

      Links are only supported between ~streams~ and ~records~ within a single database.

      This method will trigger a <do_establish_link> call.

      bitdo​_open​_db()
      bitdo​_close​_db()
      uvm_tr_streamdo​_open​_stream(string name, string scope, string type_name)
      voiddo​_establish​_link(uvm_link_base link)

    Class uvm​_text​_tr​_database

    • Extends: uvm​_tr​_database

    • Fields Summary
      TypeNameDescription
      uvm_simple_lock_dapm​_filename​_dap
      UVM_FILEm​_file

      Variable- m_file

      stringtype​_name
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new Constructor

      Parameters: name - Instance name

      bitdo​_open​_db()
      bitdo​_close​_db()
      uvm_tr_streamdo​_open​_stream(string name, string scope, string type_name)
      voiddo​_establish​_link(uvm_link_base link)
      voidset​_file​_name(string filename)

      Function: set_file_name Sets the file name which will be used for output.

      The ~set_file_name~ method can only be called prior to ~open_db~.

      By default, the database will use a file named "tr_db.log".

    Class m​_uvm​_tr​_stream​_cfg

      Description

      class- m_uvm_tr_stream_cfg Undocumented helper class for storing stream initialization values.

      Fields Summary
      TypeNameDescription
      uvm_tr_databasedb
      stringscope
      stringstream​_type​_name

    Virtual class uvm​_tr​_stream

    • Extends: uvm​_object

    • Description

      CLASS: uvm_tr_stream

      The ~uvm_tr_stream~ base class is a representation of a stream of records within a <uvm_tr_database>.

      The record stream is intended to hide the underlying database implementation from the end user, as these details are often vendor or tool-specific.

      The ~uvm_tr_stream~ class is pure virtual, and must be extended with an implementation. A default text-based implementation is provided via the <uvm_text_tr_stream> class.

      Fields Summary
      TypeNameDescription
      uvm_set_before_get_dapm​_cfg​_dap
      bit[]m​_records
      bitm​_warn​_null​_cfg
      bitm​_is​_opened
      bitm​_is​_closed
      integer[]m​_ids​_by​_stream
      uvm_tr_stream[]m​_streams​_by​_id
      Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new Constructor

      Parameters: name - Stream instance name

      uvm_tr_databaseget​_db()

      Function: get_db Returns a reference to the database which contains this stream.

      A warning will be asserted if get_db is called prior to the stream being initialized via <do_open>.

      stringget​_scope()

      Function: get_scope Returns the ~scope~ supplied when opening this stream.

      A warning will be asserted if get_scope is called prior to the stream being initialized via <do_open>.

      stringget​_stream​_type​_name()

      Function: get_stream_type_name Returns a reference to the database which contains this stream.

      A warning will be asserted if get_stream_type_name is called prior to the stream being initialized via <do_open>.

      voidclose()

      Function: close Closes this stream.

      Closing a stream closes all open recorders in the stream.

      This method will trigger a <do_close> call, followed by <uvm_recorder::close> on all open recorders within the stream.

      voidfree()

      Function: free Frees this stream.

      Freeing a stream indicates that the database can free any references to the stream (including references to records within the stream).

      This method will trigger a <do_free> call, followed by <uvm_recorder::free> on all recorders within the stream.

      voidm​_do​_open(uvm_tr_database db, string scope, string stream_type_name)

      Function- m_do_open Initializes the state of the stream

      Parameters- db - Database which the stream belongs to scope - Optional scope stream_type_name - Optional type name for the stream

      This method will trigger a <do_open> call.

      An error will be asserted if-

      • m_do_open is called more than once without the stream being ~freed~ between.

      • m_do_open is passed a ~null~ db

      bitis​_open()

      Function: is_open Returns true if this ~uvm_tr_stream~ was opened on the database, but has not yet been closed.

      bitis​_closed()

      Function: is_closed Returns true if this ~uvm_tr_stream~ was closed on the database, but has not yet been freed.

      uvm_recorderopen​_recorder(string name, time open_time, string type_name)

      Function: open_recorder Marks the opening of a new transaction recorder on the stream.

      Parameters: name - A name for the new transaction open_time - Optional time to record as the opening of this transaction type_name - Optional type name for the transaction

      If ~open_time~ is omitted (or set to 0), then the stream will use the current time.

      This method will trigger a <do_open_recorder> call. If ~do_open_recorder~ returns a non-~null~ value, then the <uvm_recorder::do_open> method will be called in the recorder.

      Transaction recorders can only be opened if the stream is ~open~ on the database (per <is_open>). Otherwise the request will be ignored, and ~null~ will be returned.

      voidm​_free​_recorder(uvm_recorder recorder)

      Function- m_free_recorder Removes recorder from the internal array

      logicget​_recorders(uvm_recorder[] q)

      Function: get_recorders Provides a queue of all transactions within the stream.

      Parameters: q - A reference to the queue of <uvm_recorder>s

      The <get_recorders> method returns the size of the queue, such that the user can conditionally process the elements.

      | uvm_recorder tr_q$; | if (my_stream.get_recorders(tr_q)) begin | // Process the queue... | end

      integerget​_handle()

      Function: get_handle Returns a unique ID for this stream.

      A value of ~0~ indicates that the recorder has been ~freed~, and no longer has a valid ID.

      integerm​_get​_handle()
      uvm_tr_streamget​_stream​_from​_handle(integer id)
      voidm​_free​_id(integer id)
      voiddo​_open(uvm_tr_database db, string scope, string stream_type_name)
      voiddo​_close()
      voiddo​_free()
      uvm_recorderdo​_open​_recorder(string name, time open_time, string type_name)

    Class uvm​_text​_tr​_stream

    • Extends: uvm​_tr​_stream

    • Fields Summary
      TypeNameDescription
      uvm_text_tr_databasem​_text​_db
      stringtype​_name
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new Constructor

      Parameters: name - Instance name

      voiddo​_open(uvm_tr_database db, string scope, string stream_type_name)
      voiddo​_close()
      voiddo​_free()
      uvm_recorderdo​_open​_recorder(string name, time open_time, string type_name)

    Virtual class uvm​_recorder

    • Extends: uvm​_object

    • Description

      uvm_recorder

      Fields Summary
      TypeNameDescription
      uvm_set_before_get_dapm​_stream​_dap
      bitm​_warn​_null​_stream
      bitm​_is​_opened
      bitm​_is​_closed
      timem​_open​_time
      timem​_close​_time
      intrecording​_depth

      Variable- recording_depth

      uvm_radix_enumdefault​_radix
      bitphysical
      bitabstract
      bitidentifier
      uvm_recursion_policy_enumpolicy
      integer[]m​_ids​_by​_recorder
      uvm_recorder[]m​_recorders​_by​_id
      integerm​_id
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      uvm_tr_streamget​_stream()

      Function: get_stream Returns a reference to the stream which created this record.

      A warning will be asserted if get_stream is called prior to the record being initialized via <do_open>.

      voidclose(time close_time)

      Function: close Closes this recorder.

      Closing a recorder marks the end of the transaction in the stream.

      Parameters: close_time - Optional time to record as the closing time of this transaction.

      This method will trigger a <do_close> call.

      voidfree(time close_time)

      Function: free Frees this recorder

      Freeing a recorder indicates that the stream and database can release any references to the recorder.

      Parameters: close_time - Optional time to record as the closing time of this transaction.

      If a recorder has not yet been closed (via a call to ), then will automatically be called, and passed the ~close_time~. If the recorder has already been closed, then the ~close_time~ will be ignored.

      This method will trigger a <do_free> call.

      bitis​_open()

      Function: is_open Returns true if this ~uvm_recorder~ was opened on its stream, but has not yet been closed.

      timeget​_open​_time()

      Function: get_open_time Returns the ~open_time~

      bitis​_closed()

      Function: is_closed Returns true if this ~uvm_recorder~ was closed on its stream, but has not yet been freed.

      timeget​_close​_time()

      Function: get_close_time Returns the ~close_time~

      voidm​_do​_open(uvm_tr_stream stream, time open_time, string type_name)

      Function- m_do_open Initializes the internal state of the recorder.

      Parameters: stream - The stream which spawned this recorder

      This method will trigger a <do_open> call.

      An error will be asserted if:

      • ~m_do_open~ is called more than once without the recorder being ~freed~ in between.

      • ~stream~ is ~null~

      voidm​_free​_id(integer id)
      integerget​_handle()

      Function: get_handle Returns a unique ID for this recorder.

      A value of ~0~ indicates that the recorder has been ~freed~, and no longer has a valid ID.

      uvm_recorderget​_recorder​_from​_handle(integer id)
      voidrecord​_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix)

      Function: record_field Records an integral field (less than or equal to 4096 bits).

      Parameters: name - Name of the field value - Value of the field to record. size - Number of bits of the field which apply (Usually obtained via $bits). radix - The <uvm_radix_enum> to use.

      This method will trigger a <do_record_field> call.

      voidrecord​_field​_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix)

      Function: record_field_int Records an integral field (less than or equal to 64 bits).

      This optimized version of <record_field> is useful for sizes up to 64 bits.

      Parameters: name - Name of the field value - Value of the field to record size - Number of bits of the wfield which apply (Usually obtained via $bits). radix - The <uvm_radix_enum> to use.

      This method will trigger a <do_record_field_int> call.

      voidrecord​_field​_real(string name, real value)

      Function: record_field_real Records a real field.

      Parameters: name - Name of the field value - Value of the field to record

      This method will trigger a <do_record_field_real> call.

      voidrecord​_object(string name, uvm_object value)

      Function: record_object Records an object field.

      Parameters: name - Name of the field value - Object to record

      The implementation must use the <recursion_policy> and to determine exactly what should be recorded.

      voidrecord​_string(string name, string value)

      Function: record_string Records a string field.

      Parameters: name - Name of the field value - Value of the field

      voidrecord​_time(string name, time value)

      Function: record_time Records a time field.

      Parameters: name - Name of the field value - Value of the field

      voidrecord​_generic(string name, string value, string type_name)

      Function: record_generic Records a name/value pair, where ~value~ has been converted to a string.

      For example: | recorder.record_generic("myvar","var_type", $sformatf("%0d",myvar), 32);

      Parameters: name - Name of the field value - Value of the field type_name - ~optional~ Type name of the field

      bituse​_record​_attribute()
      integerget​_record​_attribute​_handle()
      voiddo​_open(uvm_tr_stream stream, time open_time, string type_name)
      voiddo​_close(time close_time)
      voiddo​_free()
      voiddo​_record​_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix)
      voiddo​_record​_field​_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix)
      voiddo​_record​_field​_real(string name, real value)
      voiddo​_record​_object(string name, uvm_object value)
      voiddo​_record​_string(string name, string value)
      voiddo​_record​_time(string name, time value)
      voiddo​_record​_generic(string name, string value, string type_name)
      bitopen​_file()
      integercreate​_stream(string name, string t, string scope)
      voidm​_set​_attribute(integer txh, string nm, string value)
      voidset​_attribute(integer txh, string nm, anonymous value, uvm_radix_enum radix, integer numbits)
      integercheck​_handle​_kind(string htype, integer handle)
      integerbegin​_tr(string txtype, integer stream, string nm, string label, string desc, time begin_time)
      voidend​_tr(integer handle, time end_time)
      voidlink​_tr(integer h1, integer h2, string relation)
      voidfree​_tr(integer handle)

    Class uvm​_text​_recorder

    • Extends: uvm​_recorder

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_text_tr_databasem​_text​_db

      Variable- m_text_db

      Reference to the text database backend

      uvm_scope_stackscope

      Variable- scope Imeplementation detail

      stringfilename
      bitfilename​_set
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new Constructor

      Parameters: name - Instance name

      voiddo​_open(uvm_tr_stream stream, time open_time, string type_name)
      voiddo​_close(time close_time)
      voiddo​_free()
      voiddo​_record​_field(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix)
      voiddo​_record​_field​_int(string name, uvm_integral_t value, int size, uvm_radix_enum radix)
      voiddo​_record​_field​_real(string name, real value)
      voiddo​_record​_object(string name, uvm_object value)
      voiddo​_record​_string(string name, string value)
      voiddo​_record​_time(string name, time value)
      voiddo​_record​_generic(string name, string value, string type_name)
      voidwrite​_attribute(string nm, uvm_bitstream_t value, uvm_radix_enum radix, integer numbits)

      Function: write_attribute Outputs an integral attribute to the textual log

      Parameters: nm - Name of the attribute value - Value radix - Radix of the output numbits - number of valid bits

      voidwrite​_attribute​_int(string nm, uvm_integral_t value, uvm_radix_enum radix, integer numbits)

      Function: write_attribute_int Outputs an integral attribute to the textual log

      Parameters: nm - Name of the attribute value - Value radix - Radix of the output numbits - number of valid bits

      bitopen​_file()
      integercreate​_stream(string name, string t, string scope)
      voidm​_set​_attribute(integer txh, string nm, string value)
      voidset​_attribute(integer txh, string nm, anonymous value, uvm_radix_enum radix, integer numbits)
      integercheck​_handle​_kind(string htype, integer handle)
      integerbegin​_tr(string txtype, integer stream, string nm, string label, string desc, time begin_time)
      voidend​_tr(integer handle, time end_time)
      voidlink​_tr(integer h1, integer h2, string relation)
      voidfree​_tr(integer handle)

      free_tr

    Virtual class uvm​_event​_callback

    • Extends: uvm​_object

    • Method Summary
      TypeMethodDescription
      logicnew(string name)
      bitpre​_trigger(uvm_event e, T data)
      voidpost​_trigger(uvm_event e, T data)
      uvm_objectcreate(string name)

    Virtual class uvm​_event​_base

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      eventm​_event
      intnum​_waiters
      biton
      timetrigger​_time
      uvm_event_callback[]callbacks
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidwait​_on(bit delta)
      voidwait​_off(bit delta)
      voidwait​_trigger()
      voidwait​_ptrigger()
      timeget​_trigger​_time()
      bitis​_on()
      bitis​_off()
      voidreset(bit wakeup)
      voidcancel()
      intget​_num​_waiters()
      stringget​_type​_name()
      voiddo​_print(uvm_printer printer)
      voiddo​_copy(uvm_object rhs)

    Class uvm​_event

    • Extends: uvm​_event​_base

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      Ttrigger​_data
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidwait​_trigger​_data(T data)
      voidwait​_ptrigger​_data(T data)
      voidtrigger(T data)
      Tget​_trigger​_data()
      stringget​_type​_name()
      voidadd​_callback(uvm_event_callback cb, bit append)
      voiddelete​_callback(uvm_event_callback cb)
      voiddo​_print(uvm_printer printer)
      voiddo​_copy(uvm_object rhs)

      do_copy

      uvm_objectcreate(string name)

    Class uvm​_barrier

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      intthreshold
      intnum​_waiters
      bitat​_threshold
      bitauto​_reset
      uvm_eventm​_event
      stringtype​_name
      Method Summary
      TypeMethodDescription
      logicnew(string name, int threshold)
      voidwait​_for()
      voidreset(bit wakeup)
      voidset​_auto​_reset(bit value)
      voidset​_threshold(int threshold)
      intget​_threshold()
      intget​_num​_waiters()
      voidcancel()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      voidm​_trigger()
      voiddo​_print(uvm_printer printer)
      voiddo​_copy(uvm_object rhs)

    Class uvm​_typeid​_base

      Fields Summary
      TypeNameDescription
      stringtypename
      uvm_callbacks_base[]typeid​_map
      uvm_typeid_base[]type​_map

    Class uvm​_typeid

    • Extends: uvm​_typeid​_base

    • Fields Summary
      TypeNameDescription
      uvm_typeidm​_b​_inst
      Method Summary
      TypeMethodDescription
      uvm_typeidget()

    Class uvm​_callbacks​_base

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      bitm​_tracing
      this_typem​_b​_inst
      uvm_poolm​_pool
      this_type[]m​_this​_type

      one to many T->T/CB

      uvm_typeid_basem​_super​_type

      one to one relation

      uvm_typeid_base[]m​_derived​_types

      one to many relation

      Method Summary
      TypeMethodDescription
      this_typem​_initialize()
      bitm​_am​_i​_a(uvm_object obj)
      bitm​_is​_for​_me(uvm_callback cb)
      bitm​_is​_registered(uvm_object obj, uvm_callback cb)
      uvm_queuem​_get​_tw​_cb​_q(uvm_object obj)
      voidm​_add​_tw​_cbs(uvm_callback cb, uvm_apprepend ordering)
      bitm​_delete​_tw​_cbs(uvm_callback cb)
      bitcheck​_registration(uvm_object obj, uvm_callback cb)

      Check registration. To test registration, start at this class and work down the class hierarchy. If any class returns true then the pair is legal.

    Class uvm​_typed​_callbacks

    • Extends: uvm​_callbacks​_base

    • Fields Summary
      TypeNameDescription
      uvm_queuem​_tw​_cb​_q
      stringm​_typename
      this_typem​_t​_inst
      Method Summary
      TypeMethodDescription
      this_typem​_initialize()
      bitm​_am​_i​_a(uvm_object obj)
      uvm_queuem​_get​_tw​_cb​_q(uvm_object obj)
      intm​_cb​_find(uvm_queue q, uvm_callback cb)
      intm​_cb​_find​_name(uvm_queue q, string name, string where)
      voidm​_add​_tw​_cbs(uvm_callback cb, uvm_apprepend ordering)
      bitm​_delete​_tw​_cbs(uvm_callback cb)
      voiddisplay(T obj)

    Class uvm​_callbacks

      Fields Summary
      TypeNameDescription
      this_typem​_inst
      uvm_typeid_basem​_typeid
      uvm_typeid_basem​_cb​_typeid
      stringm​_typename
      stringm​_cb​_typename
      uvm_report_objectreporter
      uvm_callbacksm​_base​_inst
      bitm​_registered
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      bitm​_tracing
      this_typem​_b​_inst
      uvm_poolm​_pool
      this_type[]m​_this​_type

      one to many T->T/CB

      uvm_typeid_basem​_super​_type

      one to one relation

      uvm_typeid_base[]m​_derived​_types

      one to many relation

      uvm_queuem​_tw​_cb​_q
      uvm_typed_callbacksm​_t​_inst
      Method Summary
      TypeMethodDescription
      this_typeget()
      bitm​_register​_pair(string tname, string cbname)
      bitm​_is​_registered(uvm_object obj, uvm_callback cb)
      bitm​_is​_for​_me(uvm_callback cb)
      voidadd(T obj, uvm_callback cb, uvm_apprepend ordering)
      voidadd​_by​_name(string name, uvm_callback cb, uvm_component root, uvm_apprepend ordering)
      voiddelete(T obj, uvm_callback cb)
      voiddelete​_by​_name(string name, uvm_callback cb, uvm_component root)
      voidm​_get​_q(uvm_queue q, T obj)
      CBget​_first(int itr, T obj)
      CBget​_last(int itr, T obj)
      CBget​_next(int itr, T obj)
      CBget​_prev(int itr, T obj)
      voiddisplay(T obj)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_typed_callbacksm​_initialize()
      bitm​_am​_i​_a(uvm_object obj)
      uvm_queuem​_get​_tw​_cb​_q(uvm_object obj)
      voidm​_add​_tw​_cbs(uvm_callback cb, uvm_apprepend ordering)
      bitm​_delete​_tw​_cbs(uvm_callback cb)
      bitcheck​_registration(uvm_object obj, uvm_callback cb)

      Check registration. To test registration, start at this class and work down the class hierarchy. If any class returns true then the pair is legal.

      intm​_cb​_find(uvm_queue q, uvm_callback cb)
      intm​_cb​_find​_name(uvm_queue q, string name, string where)

    Class uvm​_derived​_callbacks

      Fields Summary
      TypeNameDescription
      this_typem​_d​_inst
      this_user_typem​_user​_inst
      this_super_typem​_super​_inst
      uvm_typeid_basem​_s​_typeid
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      bitm​_tracing
      this_typem​_b​_inst
      uvm_poolm​_pool
      this_type[]m​_this​_type

      one to many T->T/CB

      uvm_typeid_basem​_super​_type

      one to one relation

      uvm_typeid_base[]m​_derived​_types

      one to many relation

      uvm_queuem​_tw​_cb​_q
      stringm​_typename
      uvm_typed_callbacksm​_t​_inst
      uvm_callbacksm​_inst
      uvm_typeid_basem​_typeid
      uvm_typeid_basem​_cb​_typeid
      stringm​_cb​_typename
      uvm_report_objectreporter
      uvm_callbacksm​_base​_inst
      bitm​_registered
      Method Summary
      TypeMethodDescription
      this_typeget()
      bitregister​_super​_type(string tname, string sname)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_typed_callbacksm​_initialize()
      bitm​_am​_i​_a(uvm_object obj)
      bitm​_is​_for​_me(uvm_callback cb)
      bitm​_is​_registered(uvm_object obj, uvm_callback cb)
      uvm_queuem​_get​_tw​_cb​_q(uvm_object obj)
      voidm​_add​_tw​_cbs(uvm_callback cb, uvm_apprepend ordering)
      bitm​_delete​_tw​_cbs(uvm_callback cb)
      bitcheck​_registration(uvm_object obj, uvm_callback cb)

      Check registration. To test registration, start at this class and work down the class hierarchy. If any class returns true then the pair is legal.

      intm​_cb​_find(uvm_queue q, uvm_callback cb)
      intm​_cb​_find​_name(uvm_queue q, string name, string where)
      voiddisplay(T obj)
      bitm​_register​_pair(string tname, string cbname)
      voidadd(T obj, uvm_callback cb, uvm_apprepend ordering)
      voidadd​_by​_name(string name, uvm_callback cb, uvm_component root, uvm_apprepend ordering)
      voiddelete(T obj, uvm_callback cb)
      voiddelete​_by​_name(string name, uvm_callback cb, uvm_component root)
      voidm​_get​_q(uvm_queue q, T obj)
      CBget​_first(int itr, T obj)
      CBget​_last(int itr, T obj)
      CBget​_next(int itr, T obj)
      CBget​_prev(int itr, T obj)

    Class uvm​_callback​_iter

      Fields Summary
      TypeNameDescription
      intm​_i
      Tm​_obj
      CBm​_cb
      Method Summary
      TypeMethodDescription
      logicnew(T obj)
      CBfirst()
      CBlast()
      CBnext()
      CBprev()
      CBget​_cb()

    Class uvm​_callback

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      uvm_report_objectreporter
      bitm​_enabled
      stringtype​_name
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      bitcallback​_mode(int on)
      bitis​_enabled()
      stringget​_type​_name()

    Virtual class uvm​_report​_message​_element​_base

      Fields Summary
      TypeNameDescription
      uvm_action​_action
      string​_name
      Method Summary
      TypeMethodDescription
      stringget​_name()
      voidset​_name(string name)
      uvm_actionget​_action()
      voidset​_action(uvm_action action)
      voidprint(uvm_printer printer)
      voidrecord(uvm_recorder recorder)
      voidcopy(uvm_report_message_element_base rhs)
      uvm_report_message_element_baseclone()
      voiddo​_print(uvm_printer printer)
      voiddo​_record(uvm_recorder recorder)
      voiddo​_copy(uvm_report_message_element_base rhs)
      uvm_report_message_element_basedo​_clone()

    Class uvm​_report​_message​_int​_element

    • Extends: uvm​_report​_message​_element​_base

    • Fields Summary
      TypeNameDescription
      uvm_bitstream_t​_val
      int​_size
      uvm_radix_enum​_radix
      Method Summary
      TypeMethodDescription
      uvm_bitstream_tget​_value(int size, uvm_radix_enum radix)
      voidset​_value(uvm_bitstream_t value, int size, uvm_radix_enum radix)
      voiddo​_print(uvm_printer printer)
      voiddo​_record(uvm_recorder recorder)
      voiddo​_copy(uvm_report_message_element_base rhs)
      uvm_report_message_element_basedo​_clone()

    Class uvm​_report​_message​_string​_element

    • Extends: uvm​_report​_message​_element​_base

    • Fields Summary
      TypeNameDescription
      string​_val
      Method Summary
      TypeMethodDescription
      stringget​_value()
      voidset​_value(string value)
      voiddo​_print(uvm_printer printer)
      voiddo​_record(uvm_recorder recorder)
      voiddo​_copy(uvm_report_message_element_base rhs)
      uvm_report_message_element_basedo​_clone()

    Class uvm​_report​_message​_object​_element

    • Extends: uvm​_report​_message​_element​_base

    • Fields Summary
      TypeNameDescription
      uvm_object​_val
      Method Summary
      TypeMethodDescription
      uvm_objectget​_value()
      voidset​_value(uvm_object value)
      voiddo​_print(uvm_printer printer)
      voiddo​_record(uvm_recorder recorder)
      voiddo​_copy(uvm_report_message_element_base rhs)
      uvm_report_message_element_basedo​_clone()

    Class uvm​_report​_message​_element​_container

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      uvm_report_message_element_base[]elements
      stringtype​_name
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      intsize()
      voiddelete(int index)
      voiddelete​_elements()
      queue_of_elementget​_elements()
      voidadd​_int(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix, uvm_action action)
      voidadd​_string(string name, string value, uvm_action action)
      voidadd​_object(string name, uvm_object obj, uvm_action action)
      voiddo​_print(uvm_printer printer)
      voiddo​_record(uvm_recorder recorder)
      voiddo​_copy(uvm_object rhs)

    Class uvm​_report​_message

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      uvm_report_object​_report​_object
      uvm_report_handler​_report​_handler
      uvm_report_server​_report​_server
      uvm_severity​_severity
      string​_id
      string​_message
      int​_verbosity
      string​_filename
      int​_line
      string​_context​_name
      uvm_action​_action
      UVM_FILE​_file
      uvm_report_message_element_container​_report​_message​_element​_container
      stringtype​_name
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      uvm_report_messagenew​_report​_message(string name)
      voiddo​_print(uvm_printer printer)
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      voiddo​_copy(uvm_object rhs)
      uvm_report_objectget​_report​_object()
      voidset​_report​_object(uvm_report_object ro)
      uvm_report_handlerget​_report​_handler()
      voidset​_report​_handler(uvm_report_handler rh)
      uvm_report_serverget​_report​_server()
      voidset​_report​_server(uvm_report_server rs)
      uvm_severityget​_severity()
      voidset​_severity(uvm_severity sev)
      stringget​_id()
      voidset​_id(string id)
      stringget​_message()
      voidset​_message(string msg)
      intget​_verbosity()
      voidset​_verbosity(int ver)
      stringget​_filename()
      voidset​_filename(string fname)
      intget​_line()
      voidset​_line(int ln)
      stringget​_context()
      voidset​_context(string cn)
      uvm_actionget​_action()
      voidset​_action(uvm_action act)
      UVM_FILEget​_file()
      voidset​_file(UVM_FILE fl)
      uvm_report_message_element_containerget​_element​_container()
      voidset​_report​_message(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name)
      voidm​_record​_message(uvm_recorder recorder)
      voidm​_record​_core​_properties(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidadd​_int(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix, uvm_action action)
      voidadd​_string(string name, string value, uvm_action action)
      voidadd​_object(string name, uvm_object obj, uvm_action action)

    Class sev​_id​_struct

      Fields Summary
      TypeNameDescription
      bitsev​_specified
      bitid​_specified
      uvm_severitysev
      stringid
      bitis​_on

    Virtual class uvm​_report​_catcher

    • Extends: uvm​_callback

    • Fields Summary
      TypeNameDescription
      bitm​_register​_cb​_uvm​_report​_catcher
      uvm_report_messagem​_modified​_report​_message
      uvm_report_messagem​_orig​_report​_message
      bitm​_set​_action​_called
      intm​_demoted​_fatal
      intm​_demoted​_error
      intm​_demoted​_warning
      intm​_caught​_fatal
      intm​_caught​_error
      intm​_caught​_warning
      intDO​_NOT​_CATCH
      intDO​_NOT​_MODIFY
      intm​_debug​_flags
      bitdo​_report
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      uvm_report_objectget​_client()
      uvm_severityget​_severity()
      stringget​_context()
      intget​_verbosity()
      stringget​_id()
      stringget​_message()
      uvm_actionget​_action()
      stringget​_fname()
      intget​_line()
      uvm_report_message_element_containerget​_element​_container()
      voidset​_severity(uvm_severity severity)
      voidset​_verbosity(int verbosity)
      voidset​_id(string id)
      voidset​_message(string message)
      voidset​_action(uvm_action action)
      voidset​_context(string context_str)
      voidadd​_int(string name, uvm_bitstream_t value, int size, uvm_radix_enum radix, uvm_action action)
      voidadd​_string(string name, string value, uvm_action action)
      voidadd​_object(string name, uvm_object obj, uvm_action action)
      uvm_report_catcherget​_report​_catcher(string name)
      voidprint​_catcher(UVM_FILE file)
      voiddebug​_report​_catcher(int what)
      action_ecatch()
      voiduvm​_report​_fatal(string id, string message, int verbosity, string fname, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string fname, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string fname, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string fname, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string fname, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message msg)
      voidissue()
      intprocess​_all​_report​_catchers(uvm_report_message rm)
      intprocess​_report​_catcher()
      voidsummarize()

    Virtual class uvm​_report​_server

    • Extends: uvm​_object

    • Method Summary
      TypeMethodDescription
      stringget​_type​_name()
      logicnew(string name)
      voidset​_max​_quit​_count(int count, bit overridable)
      intget​_max​_quit​_count()
      voidset​_quit​_count(int quit_count)
      intget​_quit​_count()
      voidset​_severity​_count(uvm_severity severity, int count)
      intget​_severity​_count(uvm_severity severity)
      voidset​_id​_count(string id, int count)
      intget​_id​_count(string id)
      voidget​_id​_set(string[] q)
      voidget​_severity​_set(uvm_severity[] q)
      voidset​_message​_database(uvm_tr_database database)
      uvm_tr_databaseget​_message​_database()
      voiddo​_copy(uvm_object rhs)

      Function: do_copy copies all message statistic severity,id counts to the destination uvm_report_server the copy is cummulative (only items from the source are transferred, already existing entries are not deleted, existing entries/counts are overridden when they exist in the source set)

      voidprocess​_report​_message(uvm_report_message report_message)
      voidexecute​_report​_message(uvm_report_message report_message, string composed_message)
      stringcompose​_report​_message(uvm_report_message report_message, string report_object_name)
      voidreport​_summarize(UVM_FILE file)
      voidsummarize(UVM_FILE file)
      voidset​_server(uvm_report_server server)
      uvm_report_serverget​_server()

    Class uvm​_default​_report​_server

    • Extends: uvm​_report​_server

    • Fields Summary
      TypeNameDescription
      intm​_quit​_count
      intm​_max​_quit​_count
      bitmax​_quit​_overridable
      int[]m​_severity​_count
      int[]m​_id​_count
      uvm_tr_databasem​_message​_db
      unknown[]m​_streams

      ro.name,rh.name

      bitenable​_report​_id​_count​_summary

      Variable: enable_report_id_count_summary

      A flag to enable report count summary for each ID

      bitrecord​_all​_messages

      Variable: record_all_messages

      A flag to force recording of all messages (add UVM_RM_RECORD action)

      bitshow​_verbosity

      Variable: show_verbosity

      A flag to include verbosity in the messages, e.g.

      "UVM_INFO(UVM_MEDIUM) file.v(3) @ 60: reporter ID0 Message 0"

      bitshow​_terminator

      Variable: show_terminator

      A flag to add a terminator in the messages, e.g.

      "UVM_INFO file.v(3) @ 60: reporter ID0 Message 0 -UVM_INFO"

      Method Summary
      TypeMethodDescription
      stringget​_type​_name()

      Needed for callbacks

      logicnew(string name)
      voiddo​_print(uvm_printer printer)
      intget​_max​_quit​_count()
      voidset​_max​_quit​_count(int count, bit overridable)
      intget​_quit​_count()
      voidset​_quit​_count(int quit_count)
      voidincr​_quit​_count()
      voidreset​_quit​_count()
      bitis​_quit​_count​_reached()
      intget​_severity​_count(uvm_severity severity)
      voidset​_severity​_count(uvm_severity severity, int count)
      voidincr​_severity​_count(uvm_severity severity)
      voidreset​_severity​_counts()
      intget​_id​_count(string id)
      voidset​_id​_count(string id, int count)
      voidincr​_id​_count(string id)
      voidset​_message​_database(uvm_tr_database database)
      uvm_tr_databaseget​_message​_database()
      voidget​_severity​_set(uvm_severity[] q)
      voidget​_id​_set(string[] q)
      voidf​_display(UVM_FILE file, string str)
      voidprocess​_report​_message(uvm_report_message report_message)
      voidexecute​_report​_message(uvm_report_message report_message, string composed_message)
      stringcompose​_report​_message(uvm_report_message report_message, string report_object_name)
      voidreport​_summarize(UVM_FILE file)
      voidprocess​_report(uvm_severity severity, string name, string id, string message, uvm_action action, UVM_FILE file, string filename, int line, string composed_message, int verbosity_level, uvm_report_object client)
      stringcompose​_message(uvm_severity severity, string name, string id, string message, string filename, int line)

    Class uvm​_report​_handler

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      intm​_max​_verbosity​_level
      uvm_id_verbosities_arrayid​_verbosities

      id verbosity settings : default and severity

      uvm_id_verbosities_array[]severity​_id​_verbosities
      uvm_id_actions_arrayid​_actions

      actions

      uvm_action[]severity​_actions
      uvm_id_actions_array[]severity​_id​_actions
      uvm_sev_override_arraysev​_overrides

      severity overrides

      uvm_sev_override_array[]sev​_id​_overrides
      UVM_FILEdefault​_file​_handle

      file handles : default, severity, action, (severity,id)

      uvm_id_file_arrayid​_file​_handles
      UVM_FILE[]severity​_file​_handles
      uvm_id_file_array[]severity​_id​_file​_handles
      stringtype​_name
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voiddo​_print(uvm_printer printer)
      voidprocess​_report​_message(uvm_report_message report_message)
      stringformat​_action(uvm_action action)
      voidinitialize()
      UVM_FILEget​_severity​_id​_file(uvm_severity severity, string id)
      voidset​_verbosity​_level(int verbosity_level)
      intget​_verbosity​_level(uvm_severity severity, string id)
      uvm_actionget​_action(uvm_severity severity, string id)
      UVM_FILEget​_file​_handle(uvm_severity severity, string id)
      voidset​_severity​_action(uvm_severity severity, uvm_action action)
      voidset​_id​_action(string id, uvm_action action)
      voidset​_severity​_id​_action(uvm_severity severity, string id, uvm_action action)
      voidset​_id​_verbosity(string id, int verbosity)
      voidset​_severity​_id​_verbosity(uvm_severity severity, string id, int verbosity)
      voidset​_default​_file(UVM_FILE file)
      voidset​_severity​_file(uvm_severity severity, UVM_FILE file)
      voidset​_id​_file(string id, UVM_FILE file)
      voidset​_severity​_id​_file(uvm_severity severity, string id, UVM_FILE file)
      voidset​_severity​_override(uvm_severity cur_severity, uvm_severity new_severity)
      voidset​_severity​_id​_override(uvm_severity cur_severity, string id, uvm_severity new_severity)
      voidreport(uvm_severity severity, string name, string id, string message, int verbosity_level, string filename, int line, uvm_report_object client)
      bitrun​_hooks(uvm_report_object client, uvm_severity severity, string id, string message, int verbosity, string filename, int line)
      voiddump​_state()

    Class uvm​_report​_object

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      uvm_report_handlerm​_rh
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      intget​_report​_verbosity​_level(uvm_severity severity, string id)
      intget​_report​_max​_verbosity​_level()
      voidset​_report​_verbosity​_level(int verbosity_level)
      voidset​_report​_id​_verbosity(string id, int verbosity)

      Function: set_report_id_verbosity

      voidset​_report​_severity​_id​_verbosity(uvm_severity severity, string id, int verbosity)
      intget​_report​_action(uvm_severity severity, string id)
      voidset​_report​_severity​_action(uvm_severity severity, uvm_action action)

      Function: set_report_severity_action

      voidset​_report​_id​_action(string id, uvm_action action)

      Function: set_report_id_action

      voidset​_report​_severity​_id​_action(uvm_severity severity, string id, uvm_action action)
      intget​_report​_file​_handle(uvm_severity severity, string id)
      voidset​_report​_default​_file(UVM_FILE file)
      voidset​_report​_id​_file(string id, UVM_FILE file)
      voidset​_report​_severity​_file(uvm_severity severity, UVM_FILE file)

      Function: set_report_severity_file

      voidset​_report​_severity​_id​_file(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_severity​_override(uvm_severity cur_severity, uvm_severity new_severity)

      Function: set_report_severity_override

      voidset​_report​_severity​_id​_override(uvm_severity cur_severity, string id, uvm_severity new_severity)

      Function: set_report_severity_id_override

      These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~.

      voidset​_report​_handler(uvm_report_handler handler)
      uvm_report_handlerget​_report​_handler()
      voidreset​_report​_handler()
      bitreport​_info​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_error​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_warning​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_fatal​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_hook(string id, string message, int verbosity, string filename, int line)
      voidreport​_header(UVM_FILE file)
      voidreport​_summarize(UVM_FILE file)
      voiddie()
      voidset​_report​_max​_quit​_count(int max_count)
      uvm_report_serverget​_report​_server()
      voiddump​_report​_state()
      uvm_report_objectm​_get​_report​_object()

    Virtual class uvm​_transaction

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      Method Summary
      TypeMethodDescription
      uvm_transactionnew(string name, uvm_component initiator)
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      voiddo​_print(uvm_printer printer)
      voiddo​_record(uvm_recorder recorder)
      voiddo​_copy(uvm_object rhs)
      integerm​_begin​_tr(time begin_time, integer parent_handle)

    Class uvm​_phase

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      bitm​_register​_cb​_uvm​_phase​_cb
      intmax​_ready​_to​_end​_iter
      uvm_phase_typem​_phase​_type
      uvm_phasem​_parent

      our 'schedule' node or points 'up' one level

      uvm_phasem​_imp

      phase imp to call when we execute this node

      uvm_phase_statem​_state
      intm​_run​_count

      num times this phase has executed

      anonymousm​_phase​_proc
      intm​_num​_procs​_not​_yet​_returned
      bit[]m​_predecessors
      bit[]m​_successors
      uvm_phasem​_end​_node
      bit[]m​_executing​_phases
      uvm_phase[]m​_sync

      schedule instance to which we are synced

      uvm_objectionphase​_done

      phase done objection

      intm​_ready​_to​_end​_count
      bitm​_jump​_bkwd
      bitm​_jump​_fwd
      uvm_phasem​_jump​_phase
      bitm​_premature​_end
      anonymousm​_phase​_hopper
      bitm​_phase​_trace
      bitm​_use​_ovm​_run​_semantic
      Method Summary
      TypeMethodDescription
      uvm_phasenew(string name, uvm_phase_type phase_type, uvm_phase parent)
      uvm_phase_typeget​_phase​_type()
      uvm_phase_stateget​_state()
      intget​_run​_count()
      uvm_phasefind​_by​_name(string name, bit stay_in_scope)
      uvm_phasefind(uvm_phase phase, bit stay_in_scope)
      bitis(uvm_phase phase)
      bitis​_before(uvm_phase phase)
      bitis​_after(uvm_phase phase)
      voidexec​_func(uvm_component comp, uvm_phase phase)
      voidexec​_task(uvm_component comp, uvm_phase phase)
      voidadd(uvm_phase phase, uvm_phase with_phase, uvm_phase after_phase, uvm_phase before_phase)
      uvm_phaseget​_parent()
      stringget​_full​_name()
      uvm_phaseget​_schedule(bit hier)
      stringget​_schedule​_name(bit hier)
      uvm_domainget​_domain()
      uvm_phaseget​_imp()
      stringget​_domain​_name()
      voidget​_adjacent​_predecessor​_nodes(uvm_phase[] pred)
      voidget​_adjacent​_successor​_nodes(uvm_phase[] succ)
      voidm​_report​_null​_objection(uvm_object obj, string description, int count, string action)
      uvm_objectionget​_objection()

      Function: get_objection

      Return the <uvm_objection> that gates the termination of the phase.

      voidraise​_objection(uvm_object obj, string description, int count)
      voiddrop​_objection(uvm_object obj, string description, int count)
      intget​_objection​_count(uvm_object obj)
      voidsync(uvm_domain target, uvm_phase phase, uvm_phase with_phase)
      voidunsync(uvm_domain target, uvm_phase phase, uvm_phase with_phase)
      voidwait​_for​_state(uvm_phase_state state, uvm_wait_op op)
      voidjump(uvm_phase phase)
      voidset​_jump​_phase(uvm_phase phase)
      voidend​_prematurely()
      voidjump​_all(uvm_phase phase)
      uvm_phaseget​_jump​_target()
      uvm_phasem​_find​_predecessor(uvm_phase phase, bit stay_in_scope, uvm_phase orig_phase)
      uvm_phasem​_find​_successor(uvm_phase phase, bit stay_in_scope, uvm_phase orig_phase)
      uvm_phasem​_find​_predecessor​_by​_name(string name, bit stay_in_scope, uvm_phase orig_phase)
      uvm_phasem​_find​_successor​_by​_name(string name, bit stay_in_scope, uvm_phase orig_phase)
      voidm​_print​_successors()
      voidtraverse(uvm_component comp, uvm_phase phase, uvm_phase_state state)
      voidexecute(uvm_component comp, uvm_phase phase)
      uvm_phaseget​_begin​_node()
      uvm_phaseget​_end​_node()
      intget​_ready​_to​_end​_count()
      voidget​_predecessors​_for​_successors(bit[] pred_of_succ)
      voidm​_wait​_for​_pred()
      voidclear(uvm_phase_state state)
      voidclear​_successors(uvm_phase_state state, uvm_phase end_state)
      voidm​_run​_phases()
      voidexecute​_phase()
      voidm​_terminate​_phase()
      voidm​_print​_termination​_state()
      voidwait​_for​_self​_and​_siblings​_to​_drop()
      voidkill()
      voidkill​_successors()
      stringconvert2string()
      stringm​_aa2string(bit[] aa)
      bitis​_domain()
      voidm​_get​_transitive​_children(uvm_phase[] phases)

    Class uvm​_phase​_state​_change

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_phasem​_phase
      uvm_phase_statem​_prev​_state
      uvm_phasem​_jump​_to
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      uvm_phase_stateget​_state()
      uvm_phase_stateget​_prev​_state()
      uvm_phasejump​_to()

      Function: jump_to()

      If the current state is ~UVM_PHASE_ENDED~ or ~UVM_PHASE_JUMPING~ because of a phase jump, returns the phase that is the target of jump. Returns ~null~ otherwise.

    Class uvm​_phase​_cb

    • Extends: uvm​_callback

    • Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new Constructor

      voidphase​_state​_change(uvm_phase phase, uvm_phase_state_change change)

    Class uvm​_domain

    • Extends: uvm​_phase

    • Fields Summary
      TypeNameDescription
      uvm_domainm​_common​_domain
      uvm_domainm​_uvm​_domain

      run-time phases

      uvm_domain[]m​_domains
      uvm_phasem​_uvm​_schedule
      Method Summary
      TypeMethodDescription
      voidget​_domains(uvm_domain[] domains)
      uvm_phaseget​_uvm​_schedule()
      uvm_domainget​_common​_domain()
      voidadd​_uvm​_phases(uvm_phase schedule)
      uvm_domainget​_uvm​_domain()
      logicnew(string name)

      Function: new

      Create a new instance of a phase domain.

      voidjump(uvm_phase phase)

      Function: jump

      jumps all active phases of this domain to to-phase if there is a path between active-phase and to-phase

      voidjump​_all(uvm_phase phase)

    Virtual class uvm​_bottomup​_phase

    • Extends: uvm​_phase

    • Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new

      Create a new instance of a bottom-up phase.

      voidtraverse(uvm_component comp, uvm_phase phase, uvm_phase_state state)
      voidexecute(uvm_component comp, uvm_phase phase)

    Virtual class uvm​_topdown​_phase

    • Extends: uvm​_phase

    • Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new

      Create a new instance of a top-down phase

      voidtraverse(uvm_component comp, uvm_phase phase, uvm_phase_state state)
      voidexecute(uvm_component comp, uvm_phase phase)

    Virtual class uvm​_task​_phase

    • Extends: uvm​_phase

    • Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new

      Create a new instance of a task-based phase

      voidtraverse(uvm_component comp, uvm_phase phase, uvm_phase_state state)
      voidm​_traverse(uvm_component comp, uvm_phase phase, uvm_phase_state state)
      voidexecute(uvm_component comp, uvm_phase phase)

    Class uvm​_build​_phase

    • Extends: uvm​_topdown​_phase

    • Fields Summary
      TypeNameDescription
      uvm_build_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_func(uvm_component comp, uvm_phase phase)
      uvm_build_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_connect​_phase

    • Extends: uvm​_bottomup​_phase

    • Fields Summary
      TypeNameDescription
      uvm_connect_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_func(uvm_component comp, uvm_phase phase)
      uvm_connect_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_end​_of​_elaboration​_phase

    • Extends: uvm​_bottomup​_phase

    • Fields Summary
      TypeNameDescription
      uvm_end_of_elaboration_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_func(uvm_component comp, uvm_phase phase)
      uvm_end_of_elaboration_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_start​_of​_simulation​_phase

    • Extends: uvm​_bottomup​_phase

    • Fields Summary
      TypeNameDescription
      uvm_start_of_simulation_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_func(uvm_component comp, uvm_phase phase)
      uvm_start_of_simulation_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_run​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_run_phase

      Stimulate the DUT.

      This <uvm_task_phase> calls the <uvm_component::run_phase> virtual method. This phase runs in parallel to the runtime phases, <uvm_pre_reset_phase> through <uvm_post_shutdown_phase>. All components in the testbench are synchronized with respect to the run phase regardless of the phase domain they belong to.

      Upon Entry:

      • Indicates that power has been applied.

      • There should not have been any active clock edges before entry into this phase (e.g. x->1 transitions via initial blocks).

      • Current simulation time is still equal to 0 but some "delta cycles" may have occurred.

      Typical Uses:

      • Components implement behavior that is exhibited for the entire run-time, across the various run-time phases.

      • Backward compatibility with OVM.

      Exit Criteria:

      • The DUT no longer needs to be simulated, and

      • The <uvm_post_shutdown_phase> is ready to end

      The run phase terminates in one of two ways.

      1. All run_phase objections are dropped:

      When all objections on the run_phase objection have been dropped, the phase ends and all of its threads are killed. If no component raises a run_phase objection immediately upon entering the phase, the phase ends immediately.

      1. Timeout:

      The phase ends if the timeout expires before all objections are dropped. By default, the timeout is set to 9200 seconds. You may override this via <uvm_root::set_timeout>.

      If a timeout occurs in your simulation, or if simulation never ends despite completion of your test stimulus, then it usually indicates that a component continues to object to the end of a phase.

      Fields Summary
      TypeNameDescription
      uvm_run_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_run_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_extract​_phase

    • Extends: uvm​_bottomup​_phase

    • Description

      Class: uvm_extract_phase

      Extract data from different points of the verification environment.

      <uvm_bottomup_phase> that calls the <uvm_component::extract_phase> method.

      Upon Entry:

      • The DUT no longer needs to be simulated.

      • Simulation time will no longer advance.

      Typical Uses:

      • Extract any remaining data and final state information from scoreboard and testbench components

      • Probe the DUT (via zero-time hierarchical references and/or backdoor accesses) for final state information.

      • Compute statistics and summaries.

      • Display final state information

      • Close files.

      Exit Criteria:

      • All data has been collected and summarized.

      Fields Summary
      TypeNameDescription
      uvm_extract_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_func(uvm_component comp, uvm_phase phase)
      uvm_extract_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_check​_phase

    • Extends: uvm​_bottomup​_phase

    • Description

      Class: uvm_check_phase

      Check for any unexpected conditions in the verification environment.

      <uvm_bottomup_phase> that calls the <uvm_component::check_phase> method.

      Upon Entry:

      • All data has been collected.

      Typical Uses:

      • Check that no unaccounted-for data remain.

      Exit Criteria:

      • Test is known to have passed or failed.

      Fields Summary
      TypeNameDescription
      uvm_check_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_func(uvm_component comp, uvm_phase phase)
      uvm_check_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_report​_phase

    • Extends: uvm​_bottomup​_phase

    • Description

      Class: uvm_report_phase

      Report results of the test.

      <uvm_bottomup_phase> that calls the <uvm_component::report_phase> method.

      Upon Entry:

      • Test is known to have passed or failed.

      Typical Uses:

      • Report test results.

      • Write results to file.

      Exit Criteria:

      • End of test.

      Fields Summary
      TypeNameDescription
      uvm_report_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_func(uvm_component comp, uvm_phase phase)
      uvm_report_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_final​_phase

    • Extends: uvm​_topdown​_phase

    • Fields Summary
      TypeNameDescription
      uvm_final_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_func(uvm_component comp, uvm_phase phase)
      uvm_final_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_pre​_reset​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_pre_reset_phase

      Before reset is asserted.

      <uvm_task_phase> that calls the <uvm_component::pre_reset_phase> method. This phase starts at the same time as the <uvm_run_phase> unless a user defined phase is inserted in front of this phase.

      Upon Entry:

      • Indicates that power has been applied but not necessarily valid or stable.

      • There should not have been any active clock edges before entry into this phase.

      Typical Uses:

      • Wait for power good.

      • Components connected to virtual interfaces should initialize their output to X's or Z's.

      • Initialize the clock signals to a valid value

      • Assign reset signals to X (power-on reset).

      • Wait for reset signal to be asserted if not driven by the verification environment.

      Exit Criteria:

      • Reset signal, if driven by the verification environment, is ready to be asserted.

      • Reset signal, if not driven by the verification environment, is asserted.

      Fields Summary
      TypeNameDescription
      uvm_pre_reset_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_pre_reset_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_reset​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_reset_phase

      Reset is asserted.

      <uvm_task_phase> that calls the <uvm_component::reset_phase> method.

      Upon Entry:

      • Indicates that the hardware reset signal is ready to be asserted.

      Typical Uses:

      • Assert reset signals.

      • Components connected to virtual interfaces should drive their output to their specified reset or idle value.

      • Components and environments should initialize their state variables.

      • Clock generators start generating active edges.

      • De-assert the reset signal(s) just before exit.

      • Wait for the reset signal(s) to be de-asserted.

      Exit Criteria:

      • Reset signal has just been de-asserted.

      • Main or base clock is working and stable.

      • At least one active clock edge has occurred.

      • Output signals and state variables have been initialized.

      Fields Summary
      TypeNameDescription
      uvm_reset_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_reset_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_post​_reset​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_post_reset_phase

      After reset is de-asserted.

      <uvm_task_phase> that calls the <uvm_component::post_reset_phase> method.

      Upon Entry:

      • Indicates that the DUT reset signal has been de-asserted.

      Typical Uses:

      • Components should start behavior appropriate for reset being inactive. For example, components may start to transmit idle transactions or interface training and rate negotiation. This behavior typically continues beyond the end of this phase.

      Exit Criteria:

      • The testbench and the DUT are in a known, active state.

      Fields Summary
      TypeNameDescription
      uvm_post_reset_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_post_reset_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_pre​_configure​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_pre_configure_phase

      Before the DUT is configured by the SW.

      <uvm_task_phase> that calls the <uvm_component::pre_configure_phase> method.

      Upon Entry:

      • Indicates that the DUT has been completed reset and is ready to be configured.

      Typical Uses:

      • Procedurally modify the DUT configuration information as described in the environment (and that will be eventually uploaded into the DUT).

      • Wait for components required for DUT configuration to complete training and rate negotiation.

      Exit Criteria:

      • DUT configuration information is defined.

      Fields Summary
      TypeNameDescription
      uvm_pre_configure_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_pre_configure_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_configure​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_configure_phase

      The SW configures the DUT.

      <uvm_task_phase> that calls the <uvm_component::configure_phase> method.

      Upon Entry:

      • Indicates that the DUT is ready to be configured.

      Typical Uses:

      • Components required for DUT configuration execute transactions normally.

      • Set signals and program the DUT and memories (e.g. read/write operations and sequences) to match the desired configuration for the test and environment.

      Exit Criteria:

      • The DUT has been configured and is ready to operate normally.

      Fields Summary
      TypeNameDescription
      uvm_configure_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_configure_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_post​_configure​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_post_configure_phase

      After the SW has configured the DUT.

      <uvm_task_phase> that calls the <uvm_component::post_configure_phase> method.

      Upon Entry:

      • Indicates that the configuration information has been fully uploaded.

      Typical Uses:

      • Wait for configuration information to fully propagate and take effect.

      • Wait for components to complete training and rate negotiation.

      • Enable the DUT.

      • Sample DUT configuration coverage.

      Exit Criteria:

      • The DUT has been fully configured and enabled and is ready to start operating normally.

      Fields Summary
      TypeNameDescription
      uvm_post_configure_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_post_configure_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_pre​_main​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_pre_main_phase

      Before the primary test stimulus starts.

      <uvm_task_phase> that calls the <uvm_component::pre_main_phase> method.

      Upon Entry:

      • Indicates that the DUT has been fully configured.

      Typical Uses:

      • Wait for components to complete training and rate negotiation.

      Exit Criteria:

      • All components have completed training and rate negotiation.

      • All components are ready to generate and/or observe normal stimulus.

      Fields Summary
      TypeNameDescription
      uvm_pre_main_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_pre_main_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_main​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_main_phase

      Primary test stimulus.

      <uvm_task_phase> that calls the <uvm_component::main_phase> method.

      Upon Entry:

      • The stimulus associated with the test objectives is ready to be applied.

      Typical Uses:

      • Components execute transactions normally.

      • Data stimulus sequences are started.

      • Wait for a time-out or certain amount of time, or completion of stimulus sequences.

      Exit Criteria:

      • Enough stimulus has been applied to meet the primary stimulus objective of the test.

      Fields Summary
      TypeNameDescription
      uvm_main_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_main_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_post​_main​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_post_main_phase

      After enough of the primary test stimulus.

      <uvm_task_phase> that calls the <uvm_component::post_main_phase> method.

      Upon Entry:

      • The primary stimulus objective of the test has been met.

      Typical Uses:

      • Included for symmetry.

      Exit Criteria:

      • None.

      Fields Summary
      TypeNameDescription
      uvm_post_main_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_post_main_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_pre​_shutdown​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_pre_shutdown_phase

      Before things settle down.

      <uvm_task_phase> that calls the <uvm_component::pre_shutdown_phase> method.

      Upon Entry:

      • None.

      Typical Uses:

      • Included for symmetry.

      Exit Criteria:

      • None.

      Fields Summary
      TypeNameDescription
      uvm_pre_shutdown_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_pre_shutdown_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_shutdown​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_shutdown_phase

      Letting things settle down.

      <uvm_task_phase> that calls the <uvm_component::shutdown_phase> method.

      Upon Entry:

      • None.

      Typical Uses:

      • Wait for all data to be drained out of the DUT.

      • Extract data still buffered in the DUT, usually through read/write operations or sequences.

      Exit Criteria:

      • All data has been drained or extracted from the DUT.

      • All interfaces are idle.

      Fields Summary
      TypeNameDescription
      uvm_shutdown_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_shutdown_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Class uvm​_post​_shutdown​_phase

    • Extends: uvm​_task​_phase

    • Description

      Class: uvm_post_shutdown_phase

      After things have settled down.

      <uvm_task_phase> that calls the <uvm_component::post_shutdown_phase> method. The end of this phase is synchronized to the end of the <uvm_run_phase> phase unless a user defined phase is added after this phase.

      Upon Entry:

      • No more "data" stimulus is applied to the DUT.

      Typical Uses:

      • Perform final checks that require run-time access to the DUT (e.g. read accounting registers or dump the content of memories).

      Exit Criteria:

      • All run-time checks have been satisfied.

      • The <uvm_run_phase> phase is ready to end.

      Fields Summary
      TypeNameDescription
      uvm_post_shutdown_phasem​_inst
      stringtype​_name
      Method Summary
      TypeMethodDescription
      voidexec​_task(uvm_component comp, uvm_phase phase)
      uvm_post_shutdown_phaseget()
      logicnew(string name)
      stringget​_type​_name()

    Virtual class uvm​_component

    • Extends: uvm​_report​_object

    • Fields Summary
      TypeNameDescription
      intenable​_stop​_interrupt
      bitm​_config​_deprecated​_warned
      bitm​_config​_set
      bitprint​_config​_matches
      bitprint​_enabled
      uvm_tr_databasetr​_database

      Variable: tr_database

      Specifies the <uvm_tr_database> object to use for <begin_tr> and other methods in the .
      Default is <uvm_coreservice_t::get_default_tr_database>.

      uvm_domainm​_domain

      set_domain stores our domain handle

      uvm_phase[]m​_phase​_imps

      functors to override ovm_root defaults

      uvm_phasem​_current​_phase

      the most recently executed phase

      anonymousm​_phase​_process
      bitm​_build​_done
      intm​_phasing​_active
      uvm_componentm​_parent
      uvm_component[]m​_children
      uvm_component[]m​_children​_by​_handle
      uvm_tr_streamm​_main​_stream
      unknown[]m​_streams
      uvm_recorder[]m​_tr​_h
      stringm​_name
      stringtype​_name
      uvm_event_poolevent​_pool
      intrecording​_detail
      m_verbosity_setting[]m​_verbosity​_settings
      m_verbosity_setting[]m​_time​_settings
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_action
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_sev
      Method Summary
      TypeMethodDescription
      uvm_componentnew(string name, uvm_component parent)
      uvm_componentget​_parent()
      stringget​_full​_name()
      voidget​_children(uvm_component[] children)
      uvm_componentget​_child(string name)
      intget​_next​_child(string name)
      intget​_first​_child(string name)
      intget​_num​_children()
      inthas​_child(string name)
      voidset​_name(string name)
      uvm_componentlookup(string name)
      intget​_depth()
      voidbuild​_phase(uvm_phase phase)
      voidbuild()
      voidconnect​_phase(uvm_phase phase)
      voidconnect()
      voidend​_of​_elaboration​_phase(uvm_phase phase)
      voidend​_of​_elaboration()
      voidstart​_of​_simulation​_phase(uvm_phase phase)
      voidstart​_of​_simulation()
      voidrun​_phase(uvm_phase phase)
      voidrun()
      voidpre​_reset​_phase(uvm_phase phase)
      voidreset​_phase(uvm_phase phase)
      voidpost​_reset​_phase(uvm_phase phase)
      voidpre​_configure​_phase(uvm_phase phase)
      voidconfigure​_phase(uvm_phase phase)
      voidpost​_configure​_phase(uvm_phase phase)
      voidpre​_main​_phase(uvm_phase phase)
      voidmain​_phase(uvm_phase phase)
      voidpost​_main​_phase(uvm_phase phase)
      voidpre​_shutdown​_phase(uvm_phase phase)
      voidshutdown​_phase(uvm_phase phase)
      voidpost​_shutdown​_phase(uvm_phase phase)
      voidextract​_phase(uvm_phase phase)
      voidextract()
      voidcheck​_phase(uvm_phase phase)
      voidcheck()
      voidreport​_phase(uvm_phase phase)
      voidreport()
      voidfinal​_phase(uvm_phase phase)
      voidphase​_started(uvm_phase phase)
      voidphase​_ready​_to​_end(uvm_phase phase)
      voidphase​_ended(uvm_phase phase)
      voidset​_domain(uvm_domain domain, int hier)
      uvm_domainget​_domain()
      voiddefine​_domain(uvm_domain domain)
      voidset​_phase​_imp(uvm_phase phase, uvm_phase imp, int hier)
      voidsuspend()
      voidresume()
      stringstatus()
      voidkill()
      voiddo​_kill​_all()
      voidstop​_phase(uvm_phase phase)
      voidstop(string ph_name)
      voidresolve​_bindings()
      stringmassage​_scope(string scope)
      voidset​_config​_int(string inst_name, string field_name, uvm_bitstream_t value)
      voidset​_config​_string(string inst_name, string field_name, string value)
      voidset​_config​_object(string inst_name, string field_name, uvm_object value, bit clone)
      bitget​_config​_int(string field_name, uvm_bitstream_t value)
      bitget​_config​_string(string field_name, string value)
      bitget​_config​_object(string field_name, uvm_object value, bit clone)
      voidcheck​_config​_usage(bit recurse)
      voidapply​_config​_settings(bit verbose)
      voidprint​_config​_settings(string field, uvm_component comp, bit recurse)
      voidprint​_config(bit recurse, bit audit)
      voidprint​_config​_with​_audit(bit recurse)
      voidraised(uvm_objection objection, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      uvm_componentcreate​_component(string requested_type_name, string name)
      uvm_objectcreate​_object(string requested_type_name, string name)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override​_by​_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type)
      voidset​_type​_override(string original_type_name, string override_type_name, bit replace)
      voidset​_inst​_override(string relative_inst_path, string original_type_name, string override_type_name)
      voidprint​_override​_info(string requested_type_name, string name)
      voidset​_report​_id​_verbosity​_hier(string id, int verbosity)
      voidset​_report​_severity​_id​_verbosity​_hier(uvm_severity severity, string id, int verbosity)
      voidset​_report​_severity​_action​_hier(uvm_severity severity, uvm_action action)
      voidset​_report​_id​_action​_hier(string id, uvm_action action)
      voidset​_report​_severity​_id​_action​_hier(uvm_severity severity, string id, uvm_action action)
      voidset​_report​_default​_file​_hier(UVM_FILE file)
      voidset​_report​_severity​_file​_hier(uvm_severity severity, UVM_FILE file)
      voidset​_report​_id​_file​_hier(string id, UVM_FILE file)
      voidset​_report​_severity​_id​_file​_hier(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_verbosity​_level​_hier(int verbosity)
      voidpre​_abort()
      voidaccept​_tr(uvm_transaction tr, time accept_time)
      voiddo​_accept​_tr(uvm_transaction tr)
      integerbegin​_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle)
      integerbegin​_child​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voiddo​_begin​_tr(uvm_transaction tr, string stream_name, integer tr_handle)
      voidend​_tr(uvm_transaction tr, time end_time, bit free_handle)
      voiddo​_end​_tr(uvm_transaction tr, integer tr_handle)
      integerrecord​_error​_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active)
      integerrecord​_event​_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active)
      uvm_tr_streamget​_tr​_stream(string name, string stream_type_name)
      voidfree​_tr​_stream(uvm_tr_stream stream)
      uvm_tr_databasem​_get​_tr​_database()
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      bitm​_add​_child(uvm_component child)
      voidm​_set​_full​_name()
      voiddo​_resolve​_bindings()
      voiddo​_flush()
      voidflush()
      voidm​_extract​_name(string name, string leaf, string remainder)
      uvm_objectcreate(string name)
      uvm_objectclone()
      integerm​_begin​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      stringget​_type​_name()
      voiddo​_print(uvm_printer printer)
      voidm​_set​_cl​_msg​_args()
      voidm​_set​_cl​_verb()
      voidm​_set​_cl​_action()
      voidm​_set​_cl​_sev()
      voidm​_apply​_verbosity​_settings(uvm_phase phase)
      voidm​_do​_pre​_abort()

    Class uvm​_root

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      uvm_cmdline_processorclp
      bitfinish​_on​_completion
      uvm_component[]top​_levels
      bitenable​_print​_topology
      timephase​_timeout
      uvm_rootm​_inst
      bitm​_phase​_all​_done
      bitm​_relnotes​_done
      Method Summary
      TypeMethodDescription
      uvm_rootget()
      stringget​_type​_name()
      voidrun​_test(string test_name)
      voiddie()
      voidset​_timeout(time timeout, bit overridable)
      uvm_componentfind(string comp_match)
      voidfind​_all(string comp_match, uvm_component[] comps, uvm_component comp)
      voidprint​_topology(uvm_printer printer)
      voidm​_find​_all​_recurse(string comp_match, uvm_component[] comps, uvm_component comp)
      uvm_rootnew()
      bitm​_add​_child(uvm_component child)
      voidbuild​_phase(uvm_phase phase)
      voidm​_do​_verbosity​_settings()
      voidm​_do​_timeout​_settings()
      voidm​_do​_factory​_settings()
      voidm​_process​_inst​_override(string ovr)
      voidm​_process​_type​_override(string ovr)
      voidm​_do​_config​_settings()
      voidm​_do​_max​_quit​_settings()
      voidm​_do​_dump​_args()
      voidm​_process​_config(string cfg, bit is_int)
      voidm​_process​_default​_sequence(string cfg)
      voidm​_check​_verbosity()
      voidreport​_header(UVM_FILE file)
      voidrun​_phase(uvm_phase phase)
      voidphase​_started(uvm_phase phase)

      phase_started

      At end of elab phase we need to do tlm binding resolution.

      uvm_rootm​_uvm​_get​_root()
      voidstop​_request()

      backward compat only call global_stop_request() or uvm_test_done.stop_request() instead

      voidend​_of​_elaboration​_phase(uvm_phase phase)

    Class uvm​_config​_object​_wrapper

      Description

      Undocumented struct for storing clone bit along w/ object on set_config_object(...) calls

      Fields Summary
      TypeNameDescription
      uvm_objectobj
      bitclone

    Class uvm​_objection​_events

      Fields Summary
      TypeNameDescription
      intwaiters
      eventraised
      eventdropped
      eventall​_dropped

    Class uvm​_objection

    • Extends: uvm​_report​_object

    • Fields Summary
      TypeNameDescription
      bitm​_register​_cb​_uvm​_objection​_callback
      bitm​_trace​_mode
      int[]m​_source​_count
      int[]m​_total​_count
      time[]m​_drain​_time
      uvm_objection_events[]m​_events
      bitm​_top​_all​_dropped
      uvm_rootm​_top
      uvm_objection[]m​_objections
      uvm_objection_context_object[]m​_context​_pool
      unknown[]m​_drain​_proc
      uvm_objection_context_object[]m​_scheduled​_list
      uvm_objection_context_object[]m​_scheduled​_contexts
      uvm_objection_context_object[]m​_forked​_list
      uvm_objection_context_object[]m​_forked​_contexts
      bitm​_prop​_mode
      bitm​_cleared

      for checking obj count<0

      Method Summary
      TypeMethodDescription
      logicnew(string name)
      bittrace​_mode(int mode)
      voidm​_report(uvm_object obj, uvm_object source_obj, string description, int count, string action)
      uvm_objectm​_get​_parent(uvm_object obj)
      voidm​_propagate(uvm_object obj, uvm_object source_obj, string description, int count, bit raise, int in_top_thread)
      voidset​_propagate​_mode(bit prop_mode)

      Function: set_propagate_mode Sets the propagation mode for this objection.

      By default, objections support hierarchical propagation for components. For example, if we have the following basic component tree:

      | uvm_top.parent.child

      Any objections raised by 'child' would get propagated down to parent, and then to uvm_test_top. Resulting in the following counts and totals:

      | | count | total | | uvm_top.parent.child | 1 | 1 | | uvm_top.parent | 0 | 1 | | uvm_top | 0 | 1 | |

      While propagations such as these can be useful, if they are unused by the testbench then they are simply an unnecessary performance hit. If the testbench is not going to use this functionality, then the performance can be improved by setting the propagation mode to 0.

      When propagation mode is set to 0, all intermediate callbacks between the ~source~ and ~top~ will be skipped. This would result in the following counts and totals for the above objection:

      | | count | total | | uvm_top.parent.child | 1 | 1 | | uvm_top.parent | 0 | 0 | | uvm_top | 0 | 1 | |

      Since the propagation mode changes the behavior of the objection, it can only be safely changed if there are no objections ~raised~ or ~draining~. Any attempts to change the mode while objections are ~raised~ or ~draining~ will result in an error.

      bitget​_propagate​_mode()

      Function: get_propagate_mode Returns the propagation mode for this objection.

      voidraise​_objection(uvm_object obj, string description, int count)
      voidm​_raise(uvm_object obj, uvm_object source_obj, string description, int count)
      voiddrop​_objection(uvm_object obj, string description, int count)
      voidm​_drop(uvm_object obj, uvm_object source_obj, string description, int count, int in_top_thread)
      voidclear(uvm_object obj)
      voidm​_execute​_scheduled​_forks()
      voidm​_forked​_drain(uvm_object obj, uvm_object source_obj, string description, int count, int in_top_thread)
      voidm​_init​_objections()
      voidset​_drain​_time(uvm_object obj, time drain)

      AE: set_drain_time(drain,obj=null)?

      voidraised(uvm_object obj, uvm_object source_obj, string description, int count)
      voiddropped(uvm_object obj, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_object obj, uvm_object source_obj, string description, int count)
      voidget​_objectors(uvm_object[] list)
      voidwait​_for(uvm_objection_event objt_event, uvm_object obj)

      Task: wait_for

      Waits for the raised, dropped, or all_dropped ~event~ to occur in the given ~obj~. The task returns after all corresponding callbacks for that event have been executed.

      voidwait​_for​_total​_count(uvm_object obj, int count)
      intget​_objection​_count(uvm_object obj)
      intget​_objection​_total(uvm_object obj)
      timeget​_drain​_time(uvm_object obj)
      stringm​_display​_objections(uvm_object obj, bit show_header)
      stringconvert2string()
      voiddisplay​_objections(uvm_object obj, bit show_header)
      type_idget​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      voiddo​_copy(uvm_object rhs)

    Class uvm​_test​_done​_objection

    • Extends: uvm​_objection

    • Fields Summary
      TypeNameDescription
      uvm_test_done_objectionm​_inst
      bitm​_forced
      bitm​_executing​_stop​_processes
      intm​_n​_stop​_threads
      timestop​_timeout
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidqualify(uvm_object obj, bit is_raise, string description)
      voidm​_do​_stop​_all(uvm_component comp)
      voidstop​_request()
      voidm​_stop​_request()
      voidall​_dropped(uvm_object obj, uvm_object source_obj, string description, int count)
      voidraise​_objection(uvm_object obj, string description, int count)
      voiddrop​_objection(uvm_object obj, string description, int count)
      voidforce​_stop(uvm_object obj)
      type_idget​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      uvm_test_done_objectionget()

    Class uvm​_objection​_context​_object

      Description

      Have a pool of context objects to use

      Fields Summary
      TypeNameDescription
      uvm_objectobj
      uvm_objectsource​_obj
      stringdescription
      intcount
      uvm_objectionobjection
      Method Summary
      TypeMethodDescription
      voidclear()

      Clears the values stored within the object, preventing memory leaks from reused objects

    Class uvm​_objection​_callback

    • Extends: uvm​_callback

    • Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidraised(uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count)

    Class uvm​_heartbeat

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      uvm_objectionm​_objection
      uvm_heartbeat_callbackm​_cb
      uvm_componentm​_cntxt
      uvm_heartbeat_modesm​_mode
      uvm_component[]m​_hblist
      uvm_eventm​_event
      bitm​_started
      eventm​_stop​_event
      bitm​_added
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component cntxt, uvm_objection objection)
      uvm_heartbeat_modesset​_mode(uvm_heartbeat_modes mode)
      voidset​_heartbeat(uvm_event e, uvm_component[] comps)
      voidadd(uvm_component comp)
      voidremove(uvm_component comp)
      voidstart(uvm_event e)
      voidstop()
      voidm​_start​_hb​_process()
      voidm​_enable​_cb()
      voidm​_disable​_cb()
      voidm​_hb​_process()

    Class uvm​_heartbeat​_callback

    • Extends: uvm​_objection​_callback

    • Fields Summary
      TypeNameDescription
      int[]cnt
      time[]last​_trigger
      uvm_objecttarget
      uvm_coreservice_tcs
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_object target)
      voidraised(uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object obj, uvm_object source_obj, string description, int count)
      voidreset​_counts()
      intobjects​_triggered()

    Class uvm​_enum​_wrapper

      Fields Summary
      TypeNameDescription
      T[]map
      Method Summary
      TypeMethodDescription
      bitfrom​_name(string name, T value)
      voidm​_init​_map()
      logicnew()

    Class uvm​_cmd​_line​_verb

      Fields Summary
      TypeNameDescription
      stringcomp​_path
      stringid
      uvm_verbosityverb
      intexec​_time

    Class uvm​_cmdline​_processor

    • Extends: uvm​_report​_object

    • Fields Summary
      TypeNameDescription
      uvm_cmdline_processorm​_inst
      string[]m​_argv
      string[]m​_plus​_argv
      string[]m​_uvm​_argv
      Method Summary
      TypeMethodDescription
      uvm_cmdline_processorget​_inst()
      voidget​_args(string[] args)
      voidget​_plusargs(string[] args)
      voidget​_uvm​_args(string[] args)
      intget​_arg​_matches(string match, string[] args)
      intget​_arg​_value(string match, string value)
      intget​_arg​_values(string match, string[] values)
      stringget​_tool​_name()
      stringget​_tool​_version()
      logicnew(string name)
      bitm​_convert​_verb(string verb_str, uvm_verbosity verb_enum)

    Virtual class uvm​_visitor

    • Extends: uvm​_object

    • Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidbegin​_v()
      voidend​_v()
      voidvisit(NODE node)

    Virtual class uvm​_structure​_proxy

    • Extends: uvm​_object

    • Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidget​_immediate​_children(STRUCTURE s, STRUCTURE[] children)

    Virtual class uvm​_visitor​_adapter

    • Extends: uvm​_object

    • Method Summary
      TypeMethodDescription
      voidaccept(STRUCTURE s, VISITOR v, uvm_structure_proxy p, bit invoke_begin_end)
      logicnew(string name)

    Class uvm​_top​_down​_visitor​_adapter

      Fields Summary
      TypeNameDescription
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidaccept(STRUCTURE s, VISITOR v, uvm_structure_proxy p, bit invoke_begin_end)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()

    Class uvm​_bottom​_up​_visitor​_adapter

      Fields Summary
      TypeNameDescription
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidaccept(STRUCTURE s, VISITOR v, uvm_structure_proxy p, bit invoke_begin_end)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()

    Class uvm​_by​_level​_visitor​_adapter

      Fields Summary
      TypeNameDescription
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidaccept(STRUCTURE s, VISITOR v, uvm_structure_proxy p, bit invoke_begin_end)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()

    Class uvm​_component​_proxy

      Fields Summary
      TypeNameDescription
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      Method Summary
      TypeMethodDescription
      voidget​_immediate​_children(uvm_component s, uvm_component[] children)
      logicnew(string name)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()

    Class uvm​_component​_name​_check​_visitor

      Fields Summary
      TypeNameDescription
      uvm_root​_root
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      Method Summary
      TypeMethodDescription
      stringget​_name​_constraint()
      voidvisit(uvm_component node)
      logicnew(string name)
      voidbegin​_v()
      voidend​_v()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()

    Virtual class uvm​_set​_get​_dap​_base

    • Extends: uvm​_object

    • Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new Constructor

      voidset(T value)
      bittry​_set(T value)
      Tget()
      bittry​_get(T value)

    Class uvm​_simple​_lock​_dap

      Description

      uvm_simple_lock_dap

      Fields Summary
      TypeNameDescription
      Tm​_value
      bitm​_locked
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new Constructor

      voidset(T value)
      bittry​_set(T value)
      Tget()
      bittry​_get(T value)
      voidlock()

      Function: lock Locks the data value

      The data value cannot be updated via or <try_set> while locked.

      voidunlock()

      Function: unlock Unlocks the data value

      bitis​_locked()

      Function: is_locked Returns the state of the lock.

      Returns: 1 - The value is locked 0 - The value is unlocked

      voiddo​_copy(uvm_object rhs)
      voiddo​_pack(uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      stringconvert2string()
      voiddo​_print(uvm_printer printer)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      stringget​_type​_name()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()

    Class uvm​_get​_to​_lock​_dap

      Description

      uvm_get_to_lock_dap

      Fields Summary
      TypeNameDescription
      Tm​_value
      bitm​_locked
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new Constructor

      voidset(T value)
      bittry​_set(T value)
      Tget()
      bittry​_get(T value)
      voiddo​_copy(uvm_object rhs)
      voiddo​_pack(uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      stringconvert2string()
      voiddo​_print(uvm_printer printer)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      stringget​_type​_name()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()

    Class uvm​_set​_before​_get​_dap

      Description

      uvm_set_before_get_dap

      Fields Summary
      TypeNameDescription
      Tm​_value
      bitm​_set
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new Constructor

      voidset(T value)
      bittry​_set(T value)
      Tget()
      bittry​_get(T value)
      voiddo​_copy(uvm_object rhs)
      voiddo​_pack(uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      stringconvert2string()
      voiddo​_print(uvm_printer printer)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      stringget​_type​_name()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()

    Virtual class uvm​_tlm​_if​_base

      Method Summary
      TypeMethodDescription
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)

    Virtual class uvm​_sqr​_if​_base

      Method Summary
      TypeMethodDescription
      voidget​_next​_item(T1 t)
      voidtry​_next​_item(T1 t)
      voiditem​_done(T2 t)
      voidwait​_for​_sequences()
      bithas​_do​_available()
      voidget(T1 t)
      voidpeek(T1 t)
      voidput(T2 t)
      voidput​_response(T2 t)
      voiddisable​_auto​_item​_recording()
      bitis​_auto​_item​_recording​_enabled()

    Virtual class uvm​_port​_component​_base

    • Extends: uvm​_component

    • Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      voidbuild​_phase(uvm_phase phase)
      voiddo​_task​_phase(uvm_phase phase)

    Class uvm​_port​_component

    • Extends: uvm​_port​_component​_base

    • Fields Summary
      TypeNameDescription
      PORTm​_port
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, PORT port)
      stringget​_type​_name()
      voidresolve​_bindings()
      PORTget​_port()
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitis​_port()
      bitis​_export()
      bitis​_imp()

    Virtual class uvm​_port​_base

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      this_typem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, uvm_port_type_e port_type, int min_size, int max_size)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      stringget​_type​_name()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_put​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidput(T t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_put​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      bittry​_put(T t)
      bitcan​_put()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_put​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidput(T t)
      bittry​_put(T t)
      bitcan​_put()
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_get​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidget(T t)
      voidput(T1 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_get​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      bittry​_get(T t)
      bitcan​_get()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_get​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidget(T t)
      bittry​_get(T t)
      bitcan​_get()
      voidput(T1 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_peek​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidpeek(T t)
      voidput(T1 t)
      voidget(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_peek​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_peek​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidpeek(T t)
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_get​_peek​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidget(T t)
      voidpeek(T t)
      voidput(T1 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_get​_peek​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      bittry​_get(T t)
      bitcan​_get()
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_get​_peek​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidget(T t)
      voidpeek(T t)
      bittry​_get(T t)
      bitcan​_get()
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      bittry​_put(T1 t)
      bitcan​_put()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_master​_imp

      Fields Summary
      TypeNameDescription
      this_req_typem​_req​_imp
      this_rsp_typem​_rsp​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp)
      stringget​_type​_name()
      voidput(REQ t)
      voidget(RSP t)
      voidpeek(RSP t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_master​_imp

      Fields Summary
      TypeNameDescription
      this_req_typem​_req​_imp
      this_rsp_typem​_rsp​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp)
      stringget​_type​_name()
      bittry​_put(REQ t)
      bitcan​_put()
      bittry​_get(RSP t)
      bitcan​_get()
      bittry​_peek(RSP t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_master​_imp

      Fields Summary
      TypeNameDescription
      this_req_typem​_req​_imp
      this_rsp_typem​_rsp​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp)
      stringget​_type​_name()
      voidput(REQ t)
      bittry​_put(REQ t)
      bitcan​_put()
      voidget(RSP t)
      voidpeek(RSP t)
      bittry​_get(RSP t)
      bitcan​_get()
      bittry​_peek(RSP t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_slave​_imp

      Fields Summary
      TypeNameDescription
      this_req_typem​_req​_imp
      this_rsp_typem​_rsp​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp)
      stringget​_type​_name()
      voidput(RSP t)
      voidget(REQ t)
      voidpeek(REQ t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_slave​_imp

      Fields Summary
      TypeNameDescription
      this_req_typem​_req​_imp
      this_rsp_typem​_rsp​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp)
      stringget​_type​_name()
      bittry​_put(RSP t)
      bitcan​_put()
      bittry​_get(REQ t)
      bitcan​_get()
      bittry​_peek(REQ t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_slave​_imp

      Fields Summary
      TypeNameDescription
      this_req_typem​_req​_imp
      this_rsp_typem​_rsp​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, this_imp_type imp, this_req_type req_imp, this_rsp_type rsp_imp)
      stringget​_type​_name()
      voidput(RSP t)
      bittry​_put(RSP t)
      bitcan​_put()
      voidget(REQ t)
      voidpeek(REQ t)
      bittry​_get(REQ t)
      bitcan​_get()
      bittry​_peek(REQ t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_transport​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidtransport(REQ req, RSP rsp)
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_transport​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      bitnb​_transport(REQ req, RSP rsp)
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_transport​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidtransport(REQ req, RSP rsp)
      bitnb​_transport(REQ req, RSP rsp)
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_put​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(T t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_put​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_put(T t)
      bitcan​_put()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_put​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(T t)
      bittry​_put(T t)
      bitcan​_put()
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_get​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidget(T t)
      voidput(T1 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_get​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_get(T t)
      bitcan​_get()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_get​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidget(T t)
      bittry​_get(T t)
      bitcan​_get()
      voidput(T1 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_peek​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidpeek(T t)
      voidput(T1 t)
      voidget(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_peek​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_peek​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidpeek(T t)
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_get​_peek​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidget(T t)
      voidpeek(T t)
      voidput(T1 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_get​_peek​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_get(T t)
      bitcan​_get()
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_get​_peek​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidget(T t)
      voidpeek(T t)
      bittry​_get(T t)
      bitcan​_get()
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      bittry​_put(T1 t)
      bitcan​_put()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_master​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(REQ t)
      voidget(RSP t)
      voidpeek(RSP t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_master​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_put(REQ t)
      bitcan​_put()
      bittry​_get(RSP t)
      bitcan​_get()
      bittry​_peek(RSP t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_master​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(REQ t)
      bittry​_put(REQ t)
      bitcan​_put()
      voidget(RSP t)
      voidpeek(RSP t)
      bittry​_get(RSP t)
      bitcan​_get()
      bittry​_peek(RSP t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_slave​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(RSP t)
      voidget(REQ t)
      voidpeek(REQ t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_slave​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_put(RSP t)
      bitcan​_put()
      bittry​_get(REQ t)
      bitcan​_get()
      bittry​_peek(REQ t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_slave​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(RSP t)
      bittry​_put(RSP t)
      bitcan​_put()
      voidget(REQ t)
      voidpeek(REQ t)
      bittry​_get(REQ t)
      bitcan​_get()
      bittry​_peek(REQ t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_transport​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidtransport(REQ req, RSP rsp)
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_transport​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bitnb​_transport(REQ req, RSP rsp)
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_transport​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidtransport(REQ req, RSP rsp)
      bitnb​_transport(REQ req, RSP rsp)
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_put​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(T t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_put​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_put(T t)
      bitcan​_put()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_put​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(T t)
      bittry​_put(T t)
      bitcan​_put()
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_get​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidget(T t)
      voidput(T1 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_get​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_get(T t)
      bitcan​_get()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_get​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidget(T t)
      bittry​_get(T t)
      bitcan​_get()
      voidput(T1 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_peek​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidpeek(T t)
      voidput(T1 t)
      voidget(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_peek​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_peek​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidpeek(T t)
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_get​_peek​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidget(T t)
      voidpeek(T t)
      voidput(T1 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_get​_peek​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_get(T t)
      bitcan​_get()
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_get​_peek​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidget(T t)
      voidpeek(T t)
      bittry​_get(T t)
      bitcan​_get()
      bittry​_peek(T t)
      bitcan​_peek()
      voidput(T1 t)
      bittry​_put(T1 t)
      bitcan​_put()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_master​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(REQ t)
      voidget(RSP t)
      voidpeek(RSP t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_master​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_put(REQ t)
      bitcan​_put()
      bittry​_get(RSP t)
      bitcan​_get()
      bittry​_peek(RSP t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_master​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(REQ t)
      bittry​_put(REQ t)
      bitcan​_put()
      voidget(RSP t)
      voidpeek(RSP t)
      bittry​_get(RSP t)
      bitcan​_get()
      bittry​_peek(RSP t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_slave​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(RSP t)
      voidget(REQ t)
      voidpeek(REQ t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_slave​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bittry​_put(RSP t)
      bitcan​_put()
      bittry​_get(REQ t)
      bitcan​_get()
      bittry​_peek(REQ t)
      bitcan​_peek()
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_slave​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidput(RSP t)
      bittry​_put(RSP t)
      bitcan​_put()
      voidget(REQ t)
      voidpeek(REQ t)
      bittry​_get(REQ t)
      bitcan​_get()
      bittry​_peek(REQ t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_blocking​_transport​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidtransport(REQ req, RSP rsp)
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      bitnb​_transport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_nonblocking​_transport​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      bitnb​_transport(REQ req, RSP rsp)
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_transport​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidtransport(REQ req, RSP rsp)
      bitnb​_transport(REQ req, RSP rsp)
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidwrite(T1 t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_analysis​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()
      voidwrite(T t)

      Method: write Send specified value to all connected interface

      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_analysis​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidwrite(T t)
      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_analysis​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)

      Function: new Instantiate the export.

      stringget​_type​_name()
      voidwrite(T t)

      analysis port differs from other ports in that it broadcasts to all connected interfaces. Ports only send to the interface at the index specified in a call to set_if (0 by default).

      voidput(T1 t)
      voidget(T2 t)
      voidpeek(T2 t)
      bittry​_put(T1 t)
      bitcan​_put()
      bittry​_get(T2 t)
      bitcan​_get()
      bittry​_peek(T2 t)
      bitcan​_peek()
      voidtransport(T1 req, T2 rsp)
      bitnb​_transport(T1 req, T2 rsp)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_event

      Fields Summary
      TypeNameDescription
      eventtrigger

    Virtual class uvm​_tlm​_fifo​_base

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      uvm_put_impput​_export
      uvm_get_peek_impget​_peek​_export
      uvm_analysis_portput​_ap
      uvm_analysis_portget​_ap
      uvm_put_impblocking​_put​_export
      uvm_put_impnonblocking​_put​_export
      uvm_get_peek_impblocking​_get​_export
      uvm_get_peek_impnonblocking​_get​_export
      uvm_get_peek_impget​_export
      uvm_get_peek_impblocking​_peek​_export
      uvm_get_peek_impnonblocking​_peek​_export
      uvm_get_peek_imppeek​_export
      uvm_get_peek_impblocking​_get​_peek​_export
      uvm_get_peek_impnonblocking​_get​_peek​_export
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidbuild​_phase(uvm_phase phase)

      turn off auto config

      voidflush()
      intsize()
      voidput(T t)
      voidget(T t)
      voidpeek(T t)
      bittry​_put(T t)
      bittry​_get(T t)
      bittry​_peek(T t)
      bitcan​_put()
      bitcan​_get()
      bitcan​_peek()
      uvm_tlm_eventok​_to​_put()
      uvm_tlm_eventok​_to​_get()
      uvm_tlm_eventok​_to​_peek()
      bitis​_empty()
      bitis​_full()
      intused()

    Class uvm​_tlm​_fifo

      Fields Summary
      TypeNameDescription
      stringtype​_name
      anonymousm
      intm​_size
      intm​_pending​_blocked​_gets
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_report_handlerm​_rh
      intenable​_stop​_interrupt
      bitm​_config​_deprecated​_warned
      bitm​_config​_set
      bitprint​_config​_matches
      bitprint​_enabled
      uvm_tr_databasetr​_database

      Variable: tr_database

      Specifies the <uvm_tr_database> object to use for <begin_tr> and other methods in the .
      Default is <uvm_coreservice_t::get_default_tr_database>.

      uvm_domainm​_domain

      set_domain stores our domain handle

      uvm_phase[]m​_phase​_imps

      functors to override ovm_root defaults

      uvm_phasem​_current​_phase

      the most recently executed phase

      unknownm​_phase​_process
      bitm​_build​_done
      intm​_phasing​_active
      uvm_componentm​_parent
      uvm_component[]m​_children
      uvm_component[]m​_children​_by​_handle
      uvm_tr_streamm​_main​_stream
      unknown[]m​_streams
      uvm_recorder[]m​_tr​_h
      stringm​_name
      uvm_event_poolevent​_pool
      intrecording​_detail
      m_verbosity_setting[]m​_verbosity​_settings
      m_verbosity_setting[]m​_time​_settings
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_action
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_sev
      uvm_put_impput​_export
      uvm_get_peek_impget​_peek​_export
      uvm_analysis_portput​_ap
      uvm_analysis_portget​_ap
      uvm_put_impblocking​_put​_export
      uvm_put_impnonblocking​_put​_export
      uvm_get_peek_impblocking​_get​_export
      uvm_get_peek_impnonblocking​_get​_export
      uvm_get_peek_impget​_export
      uvm_get_peek_impblocking​_peek​_export
      uvm_get_peek_impnonblocking​_peek​_export
      uvm_get_peek_imppeek​_export
      uvm_get_peek_impblocking​_get​_peek​_export
      uvm_get_peek_impnonblocking​_get​_peek​_export
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int size)
      stringget​_type​_name()
      intsize()
      intused()
      bitis​_empty()
      bitis​_full()
      voidput(T t)
      voidget(T t)
      voidpeek(T t)
      bittry​_get(T t)
      bittry​_peek(T t)
      bittry​_put(T t)
      bitcan​_put()
      bitcan​_get()
      bitcan​_peek()
      voidflush()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      intget​_report​_verbosity​_level(uvm_severity severity, string id)
      intget​_report​_max​_verbosity​_level()
      voidset​_report​_verbosity​_level(int verbosity_level)
      voidset​_report​_id​_verbosity(string id, int verbosity)

      Function: set_report_id_verbosity

      voidset​_report​_severity​_id​_verbosity(uvm_severity severity, string id, int verbosity)
      intget​_report​_action(uvm_severity severity, string id)
      voidset​_report​_severity​_action(uvm_severity severity, uvm_action action)

      Function: set_report_severity_action

      voidset​_report​_id​_action(string id, uvm_action action)

      Function: set_report_id_action

      voidset​_report​_severity​_id​_action(uvm_severity severity, string id, uvm_action action)
      intget​_report​_file​_handle(uvm_severity severity, string id)
      voidset​_report​_default​_file(UVM_FILE file)
      voidset​_report​_id​_file(string id, UVM_FILE file)
      voidset​_report​_severity​_file(uvm_severity severity, UVM_FILE file)

      Function: set_report_severity_file

      voidset​_report​_severity​_id​_file(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_severity​_override(uvm_severity cur_severity, uvm_severity new_severity)

      Function: set_report_severity_override

      voidset​_report​_severity​_id​_override(uvm_severity cur_severity, string id, uvm_severity new_severity)

      Function: set_report_severity_id_override

      These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~.

      voidset​_report​_handler(uvm_report_handler handler)
      uvm_report_handlerget​_report​_handler()
      voidreset​_report​_handler()
      bitreport​_info​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_error​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_warning​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_fatal​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_hook(string id, string message, int verbosity, string filename, int line)
      voidreport​_header(UVM_FILE file)
      voidreport​_summarize(UVM_FILE file)
      voiddie()
      voidset​_report​_max​_quit​_count(int max_count)
      uvm_report_serverget​_report​_server()
      voiddump​_report​_state()
      uvm_componentget​_parent()
      voidget​_children(uvm_component[] children)
      uvm_componentget​_child(string name)
      intget​_next​_child(string name)
      intget​_first​_child(string name)
      intget​_num​_children()
      inthas​_child(string name)
      uvm_componentlookup(string name)
      intget​_depth()
      voidbuild​_phase(uvm_phase phase)

      turn off auto config

      voidbuild()
      voidconnect​_phase(uvm_phase phase)
      voidconnect()
      voidend​_of​_elaboration​_phase(uvm_phase phase)
      voidend​_of​_elaboration()
      voidstart​_of​_simulation​_phase(uvm_phase phase)
      voidstart​_of​_simulation()
      voidrun​_phase(uvm_phase phase)
      voidrun()
      voidpre​_reset​_phase(uvm_phase phase)
      voidreset​_phase(uvm_phase phase)
      voidpost​_reset​_phase(uvm_phase phase)
      voidpre​_configure​_phase(uvm_phase phase)
      voidconfigure​_phase(uvm_phase phase)
      voidpost​_configure​_phase(uvm_phase phase)
      voidpre​_main​_phase(uvm_phase phase)
      voidmain​_phase(uvm_phase phase)
      voidpost​_main​_phase(uvm_phase phase)
      voidpre​_shutdown​_phase(uvm_phase phase)
      voidshutdown​_phase(uvm_phase phase)
      voidpost​_shutdown​_phase(uvm_phase phase)
      voidextract​_phase(uvm_phase phase)
      voidextract()
      voidcheck​_phase(uvm_phase phase)
      voidcheck()
      voidreport​_phase(uvm_phase phase)
      voidreport()
      voidfinal​_phase(uvm_phase phase)
      voidphase​_started(uvm_phase phase)
      voidphase​_ready​_to​_end(uvm_phase phase)
      voidphase​_ended(uvm_phase phase)
      voidset​_domain(uvm_domain domain, int hier)
      uvm_domainget​_domain()
      voiddefine​_domain(uvm_domain domain)
      voidset​_phase​_imp(uvm_phase phase, uvm_phase imp, int hier)
      voidsuspend()
      voidresume()
      stringstatus()
      voidkill()
      voiddo​_kill​_all()
      voidstop​_phase(uvm_phase phase)
      voidstop(string ph_name)
      voidresolve​_bindings()
      stringmassage​_scope(string scope)
      voidset​_config​_int(string inst_name, string field_name, uvm_bitstream_t value)
      voidset​_config​_string(string inst_name, string field_name, string value)
      voidset​_config​_object(string inst_name, string field_name, uvm_object value, bit clone)
      bitget​_config​_int(string field_name, uvm_bitstream_t value)
      bitget​_config​_string(string field_name, string value)
      bitget​_config​_object(string field_name, uvm_object value, bit clone)
      voidcheck​_config​_usage(bit recurse)
      voidapply​_config​_settings(bit verbose)
      voidprint​_config​_settings(string field, uvm_component comp, bit recurse)
      voidprint​_config(bit recurse, bit audit)
      voidprint​_config​_with​_audit(bit recurse)
      voidraised(uvm_objection objection, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      uvm_componentcreate​_component(string requested_type_name, string name)
      uvm_objectcreate​_object(string requested_type_name, string name)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override​_by​_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type)
      voidset​_type​_override(string original_type_name, string override_type_name, bit replace)
      voidset​_inst​_override(string relative_inst_path, string original_type_name, string override_type_name)
      voidprint​_override​_info(string requested_type_name, string name)
      voidset​_report​_id​_verbosity​_hier(string id, int verbosity)
      voidset​_report​_severity​_id​_verbosity​_hier(uvm_severity severity, string id, int verbosity)
      voidset​_report​_severity​_action​_hier(uvm_severity severity, uvm_action action)
      voidset​_report​_id​_action​_hier(string id, uvm_action action)
      voidset​_report​_severity​_id​_action​_hier(uvm_severity severity, string id, uvm_action action)
      voidset​_report​_default​_file​_hier(UVM_FILE file)
      voidset​_report​_severity​_file​_hier(uvm_severity severity, UVM_FILE file)
      voidset​_report​_id​_file​_hier(string id, UVM_FILE file)
      voidset​_report​_severity​_id​_file​_hier(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_verbosity​_level​_hier(int verbosity)
      voidpre​_abort()
      voidaccept​_tr(uvm_transaction tr, time accept_time)
      voiddo​_accept​_tr(uvm_transaction tr)
      integerbegin​_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle)
      integerbegin​_child​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voiddo​_begin​_tr(uvm_transaction tr, string stream_name, integer tr_handle)
      voidend​_tr(uvm_transaction tr, time end_time, bit free_handle)
      voiddo​_end​_tr(uvm_transaction tr, integer tr_handle)
      integerrecord​_error​_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active)
      integerrecord​_event​_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active)
      uvm_tr_streamget​_tr​_stream(string name, string stream_type_name)
      voidfree​_tr​_stream(uvm_tr_stream stream)
      uvm_tr_databasem​_get​_tr​_database()
      bitm​_add​_child(uvm_component child)
      voidm​_set​_full​_name()
      voiddo​_resolve​_bindings()
      voiddo​_flush()
      voidm​_extract​_name(string name, string leaf, string remainder)
      integerm​_begin​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voidm​_set​_cl​_msg​_args()
      voidm​_set​_cl​_verb()
      voidm​_set​_cl​_action()
      voidm​_set​_cl​_sev()
      voidm​_apply​_verbosity​_settings(uvm_phase phase)
      voidm​_do​_pre​_abort()
      uvm_tlm_eventok​_to​_put()
      uvm_tlm_eventok​_to​_get()
      uvm_tlm_eventok​_to​_peek()

    Class uvm​_tlm​_analysis​_fifo

      Fields Summary
      TypeNameDescription
      uvm_analysis_impanalysis​_export
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_report_handlerm​_rh
      intenable​_stop​_interrupt
      bitm​_config​_deprecated​_warned
      bitm​_config​_set
      bitprint​_config​_matches
      bitprint​_enabled
      uvm_tr_databasetr​_database

      Variable: tr_database

      Specifies the <uvm_tr_database> object to use for <begin_tr> and other methods in the .
      Default is <uvm_coreservice_t::get_default_tr_database>.

      uvm_domainm​_domain

      set_domain stores our domain handle

      uvm_phase[]m​_phase​_imps

      functors to override ovm_root defaults

      uvm_phasem​_current​_phase

      the most recently executed phase

      unknownm​_phase​_process
      bitm​_build​_done
      intm​_phasing​_active
      uvm_componentm​_parent
      uvm_component[]m​_children
      uvm_component[]m​_children​_by​_handle
      uvm_tr_streamm​_main​_stream
      unknown[]m​_streams
      uvm_recorder[]m​_tr​_h
      stringm​_name
      uvm_event_poolevent​_pool
      intrecording​_detail
      m_verbosity_setting[]m​_verbosity​_settings
      m_verbosity_setting[]m​_time​_settings
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_action
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_sev
      uvm_put_impput​_export
      uvm_get_peek_impget​_peek​_export
      uvm_analysis_portput​_ap
      uvm_analysis_portget​_ap
      uvm_put_impblocking​_put​_export
      uvm_put_impnonblocking​_put​_export
      uvm_get_peek_impblocking​_get​_export
      uvm_get_peek_impnonblocking​_get​_export
      uvm_get_peek_impget​_export
      uvm_get_peek_impblocking​_peek​_export
      uvm_get_peek_impnonblocking​_peek​_export
      uvm_get_peek_imppeek​_export
      uvm_get_peek_impblocking​_get​_peek​_export
      uvm_get_peek_impnonblocking​_get​_peek​_export
      anonymousm
      intm​_size
      intm​_pending​_blocked​_gets
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()
      voidwrite(T t)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      intget​_report​_verbosity​_level(uvm_severity severity, string id)
      intget​_report​_max​_verbosity​_level()
      voidset​_report​_verbosity​_level(int verbosity_level)
      voidset​_report​_id​_verbosity(string id, int verbosity)

      Function: set_report_id_verbosity

      voidset​_report​_severity​_id​_verbosity(uvm_severity severity, string id, int verbosity)
      intget​_report​_action(uvm_severity severity, string id)
      voidset​_report​_severity​_action(uvm_severity severity, uvm_action action)

      Function: set_report_severity_action

      voidset​_report​_id​_action(string id, uvm_action action)

      Function: set_report_id_action

      voidset​_report​_severity​_id​_action(uvm_severity severity, string id, uvm_action action)
      intget​_report​_file​_handle(uvm_severity severity, string id)
      voidset​_report​_default​_file(UVM_FILE file)
      voidset​_report​_id​_file(string id, UVM_FILE file)
      voidset​_report​_severity​_file(uvm_severity severity, UVM_FILE file)

      Function: set_report_severity_file

      voidset​_report​_severity​_id​_file(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_severity​_override(uvm_severity cur_severity, uvm_severity new_severity)

      Function: set_report_severity_override

      voidset​_report​_severity​_id​_override(uvm_severity cur_severity, string id, uvm_severity new_severity)

      Function: set_report_severity_id_override

      These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~.

      voidset​_report​_handler(uvm_report_handler handler)
      uvm_report_handlerget​_report​_handler()
      voidreset​_report​_handler()
      bitreport​_info​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_error​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_warning​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_fatal​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_hook(string id, string message, int verbosity, string filename, int line)
      voidreport​_header(UVM_FILE file)
      voidreport​_summarize(UVM_FILE file)
      voiddie()
      voidset​_report​_max​_quit​_count(int max_count)
      uvm_report_serverget​_report​_server()
      voiddump​_report​_state()
      uvm_componentget​_parent()
      voidget​_children(uvm_component[] children)
      uvm_componentget​_child(string name)
      intget​_next​_child(string name)
      intget​_first​_child(string name)
      intget​_num​_children()
      inthas​_child(string name)
      uvm_componentlookup(string name)
      intget​_depth()
      voidbuild​_phase(uvm_phase phase)

      turn off auto config

      voidbuild()
      voidconnect​_phase(uvm_phase phase)
      voidconnect()
      voidend​_of​_elaboration​_phase(uvm_phase phase)
      voidend​_of​_elaboration()
      voidstart​_of​_simulation​_phase(uvm_phase phase)
      voidstart​_of​_simulation()
      voidrun​_phase(uvm_phase phase)
      voidrun()
      voidpre​_reset​_phase(uvm_phase phase)
      voidreset​_phase(uvm_phase phase)
      voidpost​_reset​_phase(uvm_phase phase)
      voidpre​_configure​_phase(uvm_phase phase)
      voidconfigure​_phase(uvm_phase phase)
      voidpost​_configure​_phase(uvm_phase phase)
      voidpre​_main​_phase(uvm_phase phase)
      voidmain​_phase(uvm_phase phase)
      voidpost​_main​_phase(uvm_phase phase)
      voidpre​_shutdown​_phase(uvm_phase phase)
      voidshutdown​_phase(uvm_phase phase)
      voidpost​_shutdown​_phase(uvm_phase phase)
      voidextract​_phase(uvm_phase phase)
      voidextract()
      voidcheck​_phase(uvm_phase phase)
      voidcheck()
      voidreport​_phase(uvm_phase phase)
      voidreport()
      voidfinal​_phase(uvm_phase phase)
      voidphase​_started(uvm_phase phase)
      voidphase​_ready​_to​_end(uvm_phase phase)
      voidphase​_ended(uvm_phase phase)
      voidset​_domain(uvm_domain domain, int hier)
      uvm_domainget​_domain()
      voiddefine​_domain(uvm_domain domain)
      voidset​_phase​_imp(uvm_phase phase, uvm_phase imp, int hier)
      voidsuspend()
      voidresume()
      stringstatus()
      voidkill()
      voiddo​_kill​_all()
      voidstop​_phase(uvm_phase phase)
      voidstop(string ph_name)
      voidresolve​_bindings()
      stringmassage​_scope(string scope)
      voidset​_config​_int(string inst_name, string field_name, uvm_bitstream_t value)
      voidset​_config​_string(string inst_name, string field_name, string value)
      voidset​_config​_object(string inst_name, string field_name, uvm_object value, bit clone)
      bitget​_config​_int(string field_name, uvm_bitstream_t value)
      bitget​_config​_string(string field_name, string value)
      bitget​_config​_object(string field_name, uvm_object value, bit clone)
      voidcheck​_config​_usage(bit recurse)
      voidapply​_config​_settings(bit verbose)
      voidprint​_config​_settings(string field, uvm_component comp, bit recurse)
      voidprint​_config(bit recurse, bit audit)
      voidprint​_config​_with​_audit(bit recurse)
      voidraised(uvm_objection objection, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      uvm_componentcreate​_component(string requested_type_name, string name)
      uvm_objectcreate​_object(string requested_type_name, string name)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override​_by​_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type)
      voidset​_type​_override(string original_type_name, string override_type_name, bit replace)
      voidset​_inst​_override(string relative_inst_path, string original_type_name, string override_type_name)
      voidprint​_override​_info(string requested_type_name, string name)
      voidset​_report​_id​_verbosity​_hier(string id, int verbosity)
      voidset​_report​_severity​_id​_verbosity​_hier(uvm_severity severity, string id, int verbosity)
      voidset​_report​_severity​_action​_hier(uvm_severity severity, uvm_action action)
      voidset​_report​_id​_action​_hier(string id, uvm_action action)
      voidset​_report​_severity​_id​_action​_hier(uvm_severity severity, string id, uvm_action action)
      voidset​_report​_default​_file​_hier(UVM_FILE file)
      voidset​_report​_severity​_file​_hier(uvm_severity severity, UVM_FILE file)
      voidset​_report​_id​_file​_hier(string id, UVM_FILE file)
      voidset​_report​_severity​_id​_file​_hier(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_verbosity​_level​_hier(int verbosity)
      voidpre​_abort()
      voidaccept​_tr(uvm_transaction tr, time accept_time)
      voiddo​_accept​_tr(uvm_transaction tr)
      integerbegin​_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle)
      integerbegin​_child​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voiddo​_begin​_tr(uvm_transaction tr, string stream_name, integer tr_handle)
      voidend​_tr(uvm_transaction tr, time end_time, bit free_handle)
      voiddo​_end​_tr(uvm_transaction tr, integer tr_handle)
      integerrecord​_error​_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active)
      integerrecord​_event​_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active)
      uvm_tr_streamget​_tr​_stream(string name, string stream_type_name)
      voidfree​_tr​_stream(uvm_tr_stream stream)
      uvm_tr_databasem​_get​_tr​_database()
      bitm​_add​_child(uvm_component child)
      voidm​_set​_full​_name()
      voiddo​_resolve​_bindings()
      voiddo​_flush()
      voidflush()
      voidm​_extract​_name(string name, string leaf, string remainder)
      integerm​_begin​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voidm​_set​_cl​_msg​_args()
      voidm​_set​_cl​_verb()
      voidm​_set​_cl​_action()
      voidm​_set​_cl​_sev()
      voidm​_apply​_verbosity​_settings(uvm_phase phase)
      voidm​_do​_pre​_abort()
      intsize()
      voidput(T t)
      voidget(T t)
      voidpeek(T t)
      bittry​_put(T t)
      bittry​_get(T t)
      bittry​_peek(T t)
      bitcan​_put()
      bitcan​_get()
      bitcan​_peek()
      uvm_tlm_eventok​_to​_put()
      uvm_tlm_eventok​_to​_get()
      uvm_tlm_eventok​_to​_peek()
      bitis​_empty()
      bitis​_full()
      intused()

    Class uvm​_tlm​_req​_rsp​_channel

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_put_exportput​_request​_export
      uvm_get_peek_exportget​_peek​_response​_export
      uvm_get_peek_exportget​_peek​_request​_export
      uvm_put_exportput​_response​_export
      uvm_analysis_portrequest​_ap
      uvm_analysis_portresponse​_ap
      uvm_master_impmaster​_export
      uvm_slave_impslave​_export
      uvm_put_exportblocking​_put​_request​_export

      port aliases for backward compatibility

      uvm_put_exportnonblocking​_put​_request​_export

      port aliases for backward compatibility

      uvm_get_peek_exportget​_request​_export
      uvm_get_peek_exportblocking​_get​_request​_export
      uvm_get_peek_exportnonblocking​_get​_request​_export
      uvm_get_peek_exportpeek​_request​_export
      uvm_get_peek_exportblocking​_peek​_request​_export
      uvm_get_peek_exportnonblocking​_peek​_request​_export
      uvm_get_peek_exportblocking​_get​_peek​_request​_export
      uvm_get_peek_exportnonblocking​_get​_peek​_request​_export
      uvm_put_exportblocking​_put​_response​_export
      uvm_put_exportnonblocking​_put​_response​_export
      uvm_get_peek_exportget​_response​_export
      uvm_get_peek_exportblocking​_get​_response​_export
      uvm_get_peek_exportnonblocking​_get​_response​_export
      uvm_get_peek_exportpeek​_response​_export
      uvm_get_peek_exportblocking​_peek​_response​_export
      uvm_get_peek_exportnonblocking​_peek​_response​_export
      uvm_get_peek_exportblocking​_get​_peek​_response​_export
      uvm_get_peek_exportnonblocking​_get​_peek​_response​_export
      uvm_master_impblocking​_master​_export
      uvm_master_impnonblocking​_master​_export
      uvm_slave_impblocking​_slave​_export
      uvm_slave_impnonblocking​_slave​_export
      uvm_tlm_fifom​_request​_fifo
      uvm_tlm_fifom​_response​_fifo
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int request_fifo_size, int response_fifo_size)
      voidconnect​_phase(uvm_phase phase)
      voidcreate​_aliased​_exports()
      stringget​_type​_name()
      uvm_objectcreate(string name)

    Class uvm​_tlm​_transport​_channel

      Fields Summary
      TypeNameDescription
      uvm_transport_imptransport​_export
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_report_handlerm​_rh
      intenable​_stop​_interrupt
      bitm​_config​_deprecated​_warned
      bitm​_config​_set
      bitprint​_config​_matches
      bitprint​_enabled
      uvm_tr_databasetr​_database

      Variable: tr_database

      Specifies the <uvm_tr_database> object to use for <begin_tr> and other methods in the .
      Default is <uvm_coreservice_t::get_default_tr_database>.

      uvm_domainm​_domain

      set_domain stores our domain handle

      uvm_phase[]m​_phase​_imps

      functors to override ovm_root defaults

      uvm_phasem​_current​_phase

      the most recently executed phase

      unknownm​_phase​_process
      bitm​_build​_done
      intm​_phasing​_active
      uvm_componentm​_parent
      uvm_component[]m​_children
      uvm_component[]m​_children​_by​_handle
      uvm_tr_streamm​_main​_stream
      unknown[]m​_streams
      uvm_recorder[]m​_tr​_h
      stringm​_name
      stringtype​_name
      uvm_event_poolevent​_pool
      intrecording​_detail
      m_verbosity_setting[]m​_verbosity​_settings
      m_verbosity_setting[]m​_time​_settings
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_action
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_sev
      uvm_put_exportput​_request​_export
      uvm_get_peek_exportget​_peek​_response​_export
      uvm_get_peek_exportget​_peek​_request​_export
      uvm_put_exportput​_response​_export
      uvm_analysis_portrequest​_ap
      uvm_analysis_portresponse​_ap
      uvm_master_impmaster​_export
      uvm_slave_impslave​_export
      uvm_put_exportblocking​_put​_request​_export

      port aliases for backward compatibility

      uvm_put_exportnonblocking​_put​_request​_export

      port aliases for backward compatibility

      uvm_get_peek_exportget​_request​_export
      uvm_get_peek_exportblocking​_get​_request​_export
      uvm_get_peek_exportnonblocking​_get​_request​_export
      uvm_get_peek_exportpeek​_request​_export
      uvm_get_peek_exportblocking​_peek​_request​_export
      uvm_get_peek_exportnonblocking​_peek​_request​_export
      uvm_get_peek_exportblocking​_get​_peek​_request​_export
      uvm_get_peek_exportnonblocking​_get​_peek​_request​_export
      uvm_put_exportblocking​_put​_response​_export
      uvm_put_exportnonblocking​_put​_response​_export
      uvm_get_peek_exportget​_response​_export
      uvm_get_peek_exportblocking​_get​_response​_export
      uvm_get_peek_exportnonblocking​_get​_response​_export
      uvm_get_peek_exportpeek​_response​_export
      uvm_get_peek_exportblocking​_peek​_response​_export
      uvm_get_peek_exportnonblocking​_peek​_response​_export
      uvm_get_peek_exportblocking​_get​_peek​_response​_export
      uvm_get_peek_exportnonblocking​_get​_peek​_response​_export
      uvm_master_impblocking​_master​_export
      uvm_master_impnonblocking​_master​_export
      uvm_slave_impblocking​_slave​_export
      uvm_slave_impnonblocking​_slave​_export
      uvm_tlm_fifom​_request​_fifo
      uvm_tlm_fifom​_response​_fifo
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidtransport(REQ request, RSP response)
      bitnb​_transport(REQ req, RSP rsp)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      intget​_report​_verbosity​_level(uvm_severity severity, string id)
      intget​_report​_max​_verbosity​_level()
      voidset​_report​_verbosity​_level(int verbosity_level)
      voidset​_report​_id​_verbosity(string id, int verbosity)

      Function: set_report_id_verbosity

      voidset​_report​_severity​_id​_verbosity(uvm_severity severity, string id, int verbosity)
      intget​_report​_action(uvm_severity severity, string id)
      voidset​_report​_severity​_action(uvm_severity severity, uvm_action action)

      Function: set_report_severity_action

      voidset​_report​_id​_action(string id, uvm_action action)

      Function: set_report_id_action

      voidset​_report​_severity​_id​_action(uvm_severity severity, string id, uvm_action action)
      intget​_report​_file​_handle(uvm_severity severity, string id)
      voidset​_report​_default​_file(UVM_FILE file)
      voidset​_report​_id​_file(string id, UVM_FILE file)
      voidset​_report​_severity​_file(uvm_severity severity, UVM_FILE file)

      Function: set_report_severity_file

      voidset​_report​_severity​_id​_file(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_severity​_override(uvm_severity cur_severity, uvm_severity new_severity)

      Function: set_report_severity_override

      voidset​_report​_severity​_id​_override(uvm_severity cur_severity, string id, uvm_severity new_severity)

      Function: set_report_severity_id_override

      These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~.

      voidset​_report​_handler(uvm_report_handler handler)
      uvm_report_handlerget​_report​_handler()
      voidreset​_report​_handler()
      bitreport​_info​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_error​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_warning​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_fatal​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_hook(string id, string message, int verbosity, string filename, int line)
      voidreport​_header(UVM_FILE file)
      voidreport​_summarize(UVM_FILE file)
      voiddie()
      voidset​_report​_max​_quit​_count(int max_count)
      uvm_report_serverget​_report​_server()
      voiddump​_report​_state()
      uvm_componentget​_parent()
      voidget​_children(uvm_component[] children)
      uvm_componentget​_child(string name)
      intget​_next​_child(string name)
      intget​_first​_child(string name)
      intget​_num​_children()
      inthas​_child(string name)
      uvm_componentlookup(string name)
      intget​_depth()
      voidbuild​_phase(uvm_phase phase)
      voidbuild()
      voidconnect​_phase(uvm_phase phase)
      voidconnect()
      voidend​_of​_elaboration​_phase(uvm_phase phase)
      voidend​_of​_elaboration()
      voidstart​_of​_simulation​_phase(uvm_phase phase)
      voidstart​_of​_simulation()
      voidrun​_phase(uvm_phase phase)
      voidrun()
      voidpre​_reset​_phase(uvm_phase phase)
      voidreset​_phase(uvm_phase phase)
      voidpost​_reset​_phase(uvm_phase phase)
      voidpre​_configure​_phase(uvm_phase phase)
      voidconfigure​_phase(uvm_phase phase)
      voidpost​_configure​_phase(uvm_phase phase)
      voidpre​_main​_phase(uvm_phase phase)
      voidmain​_phase(uvm_phase phase)
      voidpost​_main​_phase(uvm_phase phase)
      voidpre​_shutdown​_phase(uvm_phase phase)
      voidshutdown​_phase(uvm_phase phase)
      voidpost​_shutdown​_phase(uvm_phase phase)
      voidextract​_phase(uvm_phase phase)
      voidextract()
      voidcheck​_phase(uvm_phase phase)
      voidcheck()
      voidreport​_phase(uvm_phase phase)
      voidreport()
      voidfinal​_phase(uvm_phase phase)
      voidphase​_started(uvm_phase phase)
      voidphase​_ready​_to​_end(uvm_phase phase)
      voidphase​_ended(uvm_phase phase)
      voidset​_domain(uvm_domain domain, int hier)
      uvm_domainget​_domain()
      voiddefine​_domain(uvm_domain domain)
      voidset​_phase​_imp(uvm_phase phase, uvm_phase imp, int hier)
      voidsuspend()
      voidresume()
      stringstatus()
      voidkill()
      voiddo​_kill​_all()
      voidstop​_phase(uvm_phase phase)
      voidstop(string ph_name)
      voidresolve​_bindings()
      stringmassage​_scope(string scope)
      voidset​_config​_int(string inst_name, string field_name, uvm_bitstream_t value)
      voidset​_config​_string(string inst_name, string field_name, string value)
      voidset​_config​_object(string inst_name, string field_name, uvm_object value, bit clone)
      bitget​_config​_int(string field_name, uvm_bitstream_t value)
      bitget​_config​_string(string field_name, string value)
      bitget​_config​_object(string field_name, uvm_object value, bit clone)
      voidcheck​_config​_usage(bit recurse)
      voidapply​_config​_settings(bit verbose)
      voidprint​_config​_settings(string field, uvm_component comp, bit recurse)
      voidprint​_config(bit recurse, bit audit)
      voidprint​_config​_with​_audit(bit recurse)
      voidraised(uvm_objection objection, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      uvm_componentcreate​_component(string requested_type_name, string name)
      uvm_objectcreate​_object(string requested_type_name, string name)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override​_by​_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type)
      voidset​_type​_override(string original_type_name, string override_type_name, bit replace)
      voidset​_inst​_override(string relative_inst_path, string original_type_name, string override_type_name)
      voidprint​_override​_info(string requested_type_name, string name)
      voidset​_report​_id​_verbosity​_hier(string id, int verbosity)
      voidset​_report​_severity​_id​_verbosity​_hier(uvm_severity severity, string id, int verbosity)
      voidset​_report​_severity​_action​_hier(uvm_severity severity, uvm_action action)
      voidset​_report​_id​_action​_hier(string id, uvm_action action)
      voidset​_report​_severity​_id​_action​_hier(uvm_severity severity, string id, uvm_action action)
      voidset​_report​_default​_file​_hier(UVM_FILE file)
      voidset​_report​_severity​_file​_hier(uvm_severity severity, UVM_FILE file)
      voidset​_report​_id​_file​_hier(string id, UVM_FILE file)
      voidset​_report​_severity​_id​_file​_hier(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_verbosity​_level​_hier(int verbosity)
      voidpre​_abort()
      voidaccept​_tr(uvm_transaction tr, time accept_time)
      voiddo​_accept​_tr(uvm_transaction tr)
      integerbegin​_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle)
      integerbegin​_child​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voiddo​_begin​_tr(uvm_transaction tr, string stream_name, integer tr_handle)
      voidend​_tr(uvm_transaction tr, time end_time, bit free_handle)
      voiddo​_end​_tr(uvm_transaction tr, integer tr_handle)
      integerrecord​_error​_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active)
      integerrecord​_event​_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active)
      uvm_tr_streamget​_tr​_stream(string name, string stream_type_name)
      voidfree​_tr​_stream(uvm_tr_stream stream)
      uvm_tr_databasem​_get​_tr​_database()
      bitm​_add​_child(uvm_component child)
      voidm​_set​_full​_name()
      voiddo​_resolve​_bindings()
      voiddo​_flush()
      voidflush()
      voidm​_extract​_name(string name, string leaf, string remainder)
      integerm​_begin​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voidm​_set​_cl​_msg​_args()
      voidm​_set​_cl​_verb()
      voidm​_set​_cl​_action()
      voidm​_set​_cl​_sev()
      voidm​_apply​_verbosity​_settings(uvm_phase phase)
      voidm​_do​_pre​_abort()
      voidcreate​_aliased​_exports()

    Class uvm​_seq​_item​_pull​_port

      Fields Summary
      TypeNameDescription
      bitprint​_enabled
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voiddisable​_auto​_item​_recording()
      bitis​_auto​_item​_recording​_enabled()
      voidget​_next​_item(REQ t)
      voidtry​_next​_item(REQ t)
      voiditem​_done(RSP t)
      voidwait​_for​_sequences()
      bithas​_do​_available()
      voidput​_response(RSP t)
      voidget(REQ t)
      voidpeek(REQ t)
      voidput(RSP t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_seq​_item​_pull​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voiddisable​_auto​_item​_recording()
      bitis​_auto​_item​_recording​_enabled()
      voidget​_next​_item(REQ t)
      voidtry​_next​_item(REQ t)
      voiditem​_done(RSP t)
      voidwait​_for​_sequences()
      bithas​_do​_available()
      voidput​_response(RSP t)
      voidget(REQ t)
      voidpeek(REQ t)
      voidput(RSP t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_seq​_item​_pull​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voiddisable​_auto​_item​_recording()
      bitis​_auto​_item​_recording​_enabled()
      voidget​_next​_item(REQ t)
      voidtry​_next​_item(REQ t)
      voiditem​_done(RSP t)
      voidwait​_for​_sequences()
      bithas​_do​_available()
      voidput​_response(RSP t)
      voidget(REQ t)
      voidpeek(REQ t)
      voidput(RSP t)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_class​_pair

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      T1first
      T2second
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name, T1 f, T2 s)
      stringget​_type​_name()
      stringconvert2string()
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_copy(uvm_object rhs)

    Class uvm​_built​_in​_pair

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      T1first
      T2second
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      stringget​_type​_name()
      stringconvert2string()
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_copy(uvm_object rhs)

    Class uvm​_built​_in​_comp

      Method Summary
      TypeMethodDescription
      bitcomp(T a, T b)

    Class uvm​_built​_in​_converter

      Method Summary
      TypeMethodDescription
      stringconvert2string(T t)

    Class uvm​_built​_in​_clone

      Method Summary
      TypeMethodDescription
      Tclone(T from)

    Class uvm​_class​_comp

      Method Summary
      TypeMethodDescription
      bitcomp(T a, T b)

    Class uvm​_class​_converter

      Method Summary
      TypeMethodDescription
      stringconvert2string(T t)

    Class uvm​_class​_clone

      Method Summary
      TypeMethodDescription
      uvm_objectclone(T from)

    Class uvm​_in​_order​_comparator

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_analysis_exportbefore​_export
      uvm_analysis_exportafter​_export
      uvm_analysis_portpair​_ap
      uvm_tlm_analysis_fifom​_before​_fifo
      uvm_tlm_analysis_fifom​_after​_fifo
      intm​_matches
      intm​_mismatches
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()
      voidconnect​_phase(uvm_phase phase)
      voidrun​_phase(uvm_phase phase)
      voidflush()

    Class uvm​_in​_order​_built​_in​_comparator

      Fields Summary
      TypeNameDescription
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_report_handlerm​_rh
      intenable​_stop​_interrupt
      bitm​_config​_deprecated​_warned
      bitm​_config​_set
      bitprint​_config​_matches
      bitprint​_enabled
      uvm_tr_databasetr​_database

      Variable: tr_database

      Specifies the <uvm_tr_database> object to use for <begin_tr> and other methods in the .
      Default is <uvm_coreservice_t::get_default_tr_database>.

      uvm_domainm​_domain

      set_domain stores our domain handle

      uvm_phase[]m​_phase​_imps

      functors to override ovm_root defaults

      uvm_phasem​_current​_phase

      the most recently executed phase

      unknownm​_phase​_process
      bitm​_build​_done
      intm​_phasing​_active
      uvm_componentm​_parent
      uvm_component[]m​_children
      uvm_component[]m​_children​_by​_handle
      uvm_tr_streamm​_main​_stream
      unknown[]m​_streams
      uvm_recorder[]m​_tr​_h
      stringm​_name
      uvm_event_poolevent​_pool
      intrecording​_detail
      m_verbosity_setting[]m​_verbosity​_settings
      m_verbosity_setting[]m​_time​_settings
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_action
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_sev
      uvm_analysis_exportbefore​_export
      uvm_analysis_exportafter​_export
      uvm_analysis_portpair​_ap
      uvm_tlm_analysis_fifom​_before​_fifo
      uvm_tlm_analysis_fifom​_after​_fifo
      intm​_matches
      intm​_mismatches
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      intget​_report​_verbosity​_level(uvm_severity severity, string id)
      intget​_report​_max​_verbosity​_level()
      voidset​_report​_verbosity​_level(int verbosity_level)
      voidset​_report​_id​_verbosity(string id, int verbosity)

      Function: set_report_id_verbosity

      voidset​_report​_severity​_id​_verbosity(uvm_severity severity, string id, int verbosity)
      intget​_report​_action(uvm_severity severity, string id)
      voidset​_report​_severity​_action(uvm_severity severity, uvm_action action)

      Function: set_report_severity_action

      voidset​_report​_id​_action(string id, uvm_action action)

      Function: set_report_id_action

      voidset​_report​_severity​_id​_action(uvm_severity severity, string id, uvm_action action)
      intget​_report​_file​_handle(uvm_severity severity, string id)
      voidset​_report​_default​_file(UVM_FILE file)
      voidset​_report​_id​_file(string id, UVM_FILE file)
      voidset​_report​_severity​_file(uvm_severity severity, UVM_FILE file)

      Function: set_report_severity_file

      voidset​_report​_severity​_id​_file(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_severity​_override(uvm_severity cur_severity, uvm_severity new_severity)

      Function: set_report_severity_override

      voidset​_report​_severity​_id​_override(uvm_severity cur_severity, string id, uvm_severity new_severity)

      Function: set_report_severity_id_override

      These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~.

      voidset​_report​_handler(uvm_report_handler handler)
      uvm_report_handlerget​_report​_handler()
      voidreset​_report​_handler()
      bitreport​_info​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_error​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_warning​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_fatal​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_hook(string id, string message, int verbosity, string filename, int line)
      voidreport​_header(UVM_FILE file)
      voidreport​_summarize(UVM_FILE file)
      voiddie()
      voidset​_report​_max​_quit​_count(int max_count)
      uvm_report_serverget​_report​_server()
      voiddump​_report​_state()
      uvm_componentget​_parent()
      voidget​_children(uvm_component[] children)
      uvm_componentget​_child(string name)
      intget​_next​_child(string name)
      intget​_first​_child(string name)
      intget​_num​_children()
      inthas​_child(string name)
      uvm_componentlookup(string name)
      intget​_depth()
      voidbuild​_phase(uvm_phase phase)
      voidbuild()
      voidconnect​_phase(uvm_phase phase)
      voidconnect()
      voidend​_of​_elaboration​_phase(uvm_phase phase)
      voidend​_of​_elaboration()
      voidstart​_of​_simulation​_phase(uvm_phase phase)
      voidstart​_of​_simulation()
      voidrun​_phase(uvm_phase phase)
      voidrun()
      voidpre​_reset​_phase(uvm_phase phase)
      voidreset​_phase(uvm_phase phase)
      voidpost​_reset​_phase(uvm_phase phase)
      voidpre​_configure​_phase(uvm_phase phase)
      voidconfigure​_phase(uvm_phase phase)
      voidpost​_configure​_phase(uvm_phase phase)
      voidpre​_main​_phase(uvm_phase phase)
      voidmain​_phase(uvm_phase phase)
      voidpost​_main​_phase(uvm_phase phase)
      voidpre​_shutdown​_phase(uvm_phase phase)
      voidshutdown​_phase(uvm_phase phase)
      voidpost​_shutdown​_phase(uvm_phase phase)
      voidextract​_phase(uvm_phase phase)
      voidextract()
      voidcheck​_phase(uvm_phase phase)
      voidcheck()
      voidreport​_phase(uvm_phase phase)
      voidreport()
      voidfinal​_phase(uvm_phase phase)
      voidphase​_started(uvm_phase phase)
      voidphase​_ready​_to​_end(uvm_phase phase)
      voidphase​_ended(uvm_phase phase)
      voidset​_domain(uvm_domain domain, int hier)
      uvm_domainget​_domain()
      voiddefine​_domain(uvm_domain domain)
      voidset​_phase​_imp(uvm_phase phase, uvm_phase imp, int hier)
      voidsuspend()
      voidresume()
      stringstatus()
      voidkill()
      voiddo​_kill​_all()
      voidstop​_phase(uvm_phase phase)
      voidstop(string ph_name)
      voidresolve​_bindings()
      stringmassage​_scope(string scope)
      voidset​_config​_int(string inst_name, string field_name, uvm_bitstream_t value)
      voidset​_config​_string(string inst_name, string field_name, string value)
      voidset​_config​_object(string inst_name, string field_name, uvm_object value, bit clone)
      bitget​_config​_int(string field_name, uvm_bitstream_t value)
      bitget​_config​_string(string field_name, string value)
      bitget​_config​_object(string field_name, uvm_object value, bit clone)
      voidcheck​_config​_usage(bit recurse)
      voidapply​_config​_settings(bit verbose)
      voidprint​_config​_settings(string field, uvm_component comp, bit recurse)
      voidprint​_config(bit recurse, bit audit)
      voidprint​_config​_with​_audit(bit recurse)
      voidraised(uvm_objection objection, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      uvm_componentcreate​_component(string requested_type_name, string name)
      uvm_objectcreate​_object(string requested_type_name, string name)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override​_by​_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type)
      voidset​_type​_override(string original_type_name, string override_type_name, bit replace)
      voidset​_inst​_override(string relative_inst_path, string original_type_name, string override_type_name)
      voidprint​_override​_info(string requested_type_name, string name)
      voidset​_report​_id​_verbosity​_hier(string id, int verbosity)
      voidset​_report​_severity​_id​_verbosity​_hier(uvm_severity severity, string id, int verbosity)
      voidset​_report​_severity​_action​_hier(uvm_severity severity, uvm_action action)
      voidset​_report​_id​_action​_hier(string id, uvm_action action)
      voidset​_report​_severity​_id​_action​_hier(uvm_severity severity, string id, uvm_action action)
      voidset​_report​_default​_file​_hier(UVM_FILE file)
      voidset​_report​_severity​_file​_hier(uvm_severity severity, UVM_FILE file)
      voidset​_report​_id​_file​_hier(string id, UVM_FILE file)
      voidset​_report​_severity​_id​_file​_hier(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_verbosity​_level​_hier(int verbosity)
      voidpre​_abort()
      voidaccept​_tr(uvm_transaction tr, time accept_time)
      voiddo​_accept​_tr(uvm_transaction tr)
      integerbegin​_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle)
      integerbegin​_child​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voiddo​_begin​_tr(uvm_transaction tr, string stream_name, integer tr_handle)
      voidend​_tr(uvm_transaction tr, time end_time, bit free_handle)
      voiddo​_end​_tr(uvm_transaction tr, integer tr_handle)
      integerrecord​_error​_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active)
      integerrecord​_event​_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active)
      uvm_tr_streamget​_tr​_stream(string name, string stream_type_name)
      voidfree​_tr​_stream(uvm_tr_stream stream)
      uvm_tr_databasem​_get​_tr​_database()
      bitm​_add​_child(uvm_component child)
      voidm​_set​_full​_name()
      voiddo​_resolve​_bindings()
      voiddo​_flush()
      voidflush()
      voidm​_extract​_name(string name, string leaf, string remainder)
      integerm​_begin​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voidm​_set​_cl​_msg​_args()
      voidm​_set​_cl​_verb()
      voidm​_set​_cl​_action()
      voidm​_set​_cl​_sev()
      voidm​_apply​_verbosity​_settings(uvm_phase phase)
      voidm​_do​_pre​_abort()

    Class uvm​_in​_order​_class​_comparator

      Fields Summary
      TypeNameDescription
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_report_handlerm​_rh
      intenable​_stop​_interrupt
      bitm​_config​_deprecated​_warned
      bitm​_config​_set
      bitprint​_config​_matches
      bitprint​_enabled
      uvm_tr_databasetr​_database

      Variable: tr_database

      Specifies the <uvm_tr_database> object to use for <begin_tr> and other methods in the .
      Default is <uvm_coreservice_t::get_default_tr_database>.

      uvm_domainm​_domain

      set_domain stores our domain handle

      uvm_phase[]m​_phase​_imps

      functors to override ovm_root defaults

      uvm_phasem​_current​_phase

      the most recently executed phase

      unknownm​_phase​_process
      bitm​_build​_done
      intm​_phasing​_active
      uvm_componentm​_parent
      uvm_component[]m​_children
      uvm_component[]m​_children​_by​_handle
      uvm_tr_streamm​_main​_stream
      unknown[]m​_streams
      uvm_recorder[]m​_tr​_h
      stringm​_name
      uvm_event_poolevent​_pool
      intrecording​_detail
      m_verbosity_setting[]m​_verbosity​_settings
      m_verbosity_setting[]m​_time​_settings
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_action
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_sev
      uvm_analysis_exportbefore​_export
      uvm_analysis_exportafter​_export
      uvm_analysis_portpair​_ap
      uvm_tlm_analysis_fifom​_before​_fifo
      uvm_tlm_analysis_fifom​_after​_fifo
      intm​_matches
      intm​_mismatches
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      intget​_report​_verbosity​_level(uvm_severity severity, string id)
      intget​_report​_max​_verbosity​_level()
      voidset​_report​_verbosity​_level(int verbosity_level)
      voidset​_report​_id​_verbosity(string id, int verbosity)

      Function: set_report_id_verbosity

      voidset​_report​_severity​_id​_verbosity(uvm_severity severity, string id, int verbosity)
      intget​_report​_action(uvm_severity severity, string id)
      voidset​_report​_severity​_action(uvm_severity severity, uvm_action action)

      Function: set_report_severity_action

      voidset​_report​_id​_action(string id, uvm_action action)

      Function: set_report_id_action

      voidset​_report​_severity​_id​_action(uvm_severity severity, string id, uvm_action action)
      intget​_report​_file​_handle(uvm_severity severity, string id)
      voidset​_report​_default​_file(UVM_FILE file)
      voidset​_report​_id​_file(string id, UVM_FILE file)
      voidset​_report​_severity​_file(uvm_severity severity, UVM_FILE file)

      Function: set_report_severity_file

      voidset​_report​_severity​_id​_file(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_severity​_override(uvm_severity cur_severity, uvm_severity new_severity)

      Function: set_report_severity_override

      voidset​_report​_severity​_id​_override(uvm_severity cur_severity, string id, uvm_severity new_severity)

      Function: set_report_severity_id_override

      These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~.

      voidset​_report​_handler(uvm_report_handler handler)
      uvm_report_handlerget​_report​_handler()
      voidreset​_report​_handler()
      bitreport​_info​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_error​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_warning​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_fatal​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_hook(string id, string message, int verbosity, string filename, int line)
      voidreport​_header(UVM_FILE file)
      voidreport​_summarize(UVM_FILE file)
      voiddie()
      voidset​_report​_max​_quit​_count(int max_count)
      uvm_report_serverget​_report​_server()
      voiddump​_report​_state()
      uvm_componentget​_parent()
      voidget​_children(uvm_component[] children)
      uvm_componentget​_child(string name)
      intget​_next​_child(string name)
      intget​_first​_child(string name)
      intget​_num​_children()
      inthas​_child(string name)
      uvm_componentlookup(string name)
      intget​_depth()
      voidbuild​_phase(uvm_phase phase)
      voidbuild()
      voidconnect​_phase(uvm_phase phase)
      voidconnect()
      voidend​_of​_elaboration​_phase(uvm_phase phase)
      voidend​_of​_elaboration()
      voidstart​_of​_simulation​_phase(uvm_phase phase)
      voidstart​_of​_simulation()
      voidrun​_phase(uvm_phase phase)
      voidrun()
      voidpre​_reset​_phase(uvm_phase phase)
      voidreset​_phase(uvm_phase phase)
      voidpost​_reset​_phase(uvm_phase phase)
      voidpre​_configure​_phase(uvm_phase phase)
      voidconfigure​_phase(uvm_phase phase)
      voidpost​_configure​_phase(uvm_phase phase)
      voidpre​_main​_phase(uvm_phase phase)
      voidmain​_phase(uvm_phase phase)
      voidpost​_main​_phase(uvm_phase phase)
      voidpre​_shutdown​_phase(uvm_phase phase)
      voidshutdown​_phase(uvm_phase phase)
      voidpost​_shutdown​_phase(uvm_phase phase)
      voidextract​_phase(uvm_phase phase)
      voidextract()
      voidcheck​_phase(uvm_phase phase)
      voidcheck()
      voidreport​_phase(uvm_phase phase)
      voidreport()
      voidfinal​_phase(uvm_phase phase)
      voidphase​_started(uvm_phase phase)
      voidphase​_ready​_to​_end(uvm_phase phase)
      voidphase​_ended(uvm_phase phase)
      voidset​_domain(uvm_domain domain, int hier)
      uvm_domainget​_domain()
      voiddefine​_domain(uvm_domain domain)
      voidset​_phase​_imp(uvm_phase phase, uvm_phase imp, int hier)
      voidsuspend()
      voidresume()
      stringstatus()
      voidkill()
      voiddo​_kill​_all()
      voidstop​_phase(uvm_phase phase)
      voidstop(string ph_name)
      voidresolve​_bindings()
      stringmassage​_scope(string scope)
      voidset​_config​_int(string inst_name, string field_name, uvm_bitstream_t value)
      voidset​_config​_string(string inst_name, string field_name, string value)
      voidset​_config​_object(string inst_name, string field_name, uvm_object value, bit clone)
      bitget​_config​_int(string field_name, uvm_bitstream_t value)
      bitget​_config​_string(string field_name, string value)
      bitget​_config​_object(string field_name, uvm_object value, bit clone)
      voidcheck​_config​_usage(bit recurse)
      voidapply​_config​_settings(bit verbose)
      voidprint​_config​_settings(string field, uvm_component comp, bit recurse)
      voidprint​_config(bit recurse, bit audit)
      voidprint​_config​_with​_audit(bit recurse)
      voidraised(uvm_objection objection, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      uvm_componentcreate​_component(string requested_type_name, string name)
      uvm_objectcreate​_object(string requested_type_name, string name)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override​_by​_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type)
      voidset​_type​_override(string original_type_name, string override_type_name, bit replace)
      voidset​_inst​_override(string relative_inst_path, string original_type_name, string override_type_name)
      voidprint​_override​_info(string requested_type_name, string name)
      voidset​_report​_id​_verbosity​_hier(string id, int verbosity)
      voidset​_report​_severity​_id​_verbosity​_hier(uvm_severity severity, string id, int verbosity)
      voidset​_report​_severity​_action​_hier(uvm_severity severity, uvm_action action)
      voidset​_report​_id​_action​_hier(string id, uvm_action action)
      voidset​_report​_severity​_id​_action​_hier(uvm_severity severity, string id, uvm_action action)
      voidset​_report​_default​_file​_hier(UVM_FILE file)
      voidset​_report​_severity​_file​_hier(uvm_severity severity, UVM_FILE file)
      voidset​_report​_id​_file​_hier(string id, UVM_FILE file)
      voidset​_report​_severity​_id​_file​_hier(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_verbosity​_level​_hier(int verbosity)
      voidpre​_abort()
      voidaccept​_tr(uvm_transaction tr, time accept_time)
      voiddo​_accept​_tr(uvm_transaction tr)
      integerbegin​_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle)
      integerbegin​_child​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voiddo​_begin​_tr(uvm_transaction tr, string stream_name, integer tr_handle)
      voidend​_tr(uvm_transaction tr, time end_time, bit free_handle)
      voiddo​_end​_tr(uvm_transaction tr, integer tr_handle)
      integerrecord​_error​_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active)
      integerrecord​_event​_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active)
      uvm_tr_streamget​_tr​_stream(string name, string stream_type_name)
      voidfree​_tr​_stream(uvm_tr_stream stream)
      uvm_tr_databasem​_get​_tr​_database()
      bitm​_add​_child(uvm_component child)
      voidm​_set​_full​_name()
      voiddo​_resolve​_bindings()
      voiddo​_flush()
      voidflush()
      voidm​_extract​_name(string name, string leaf, string remainder)
      integerm​_begin​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voidm​_set​_cl​_msg​_args()
      voidm​_set​_cl​_verb()
      voidm​_set​_cl​_action()
      voidm​_set​_cl​_sev()
      voidm​_apply​_verbosity​_settings(uvm_phase phase)
      voidm​_do​_pre​_abort()

    Class uvm​_algorithmic​_comparator

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_analysis_impbefore​_export
      uvm_analysis_exportafter​_export
      uvm_in_order_class_comparatorcomp
      TRANSFORMERm​_transformer
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      logicnew(string name, uvm_component parent, TRANSFORMER transformer)
      stringget​_type​_name()
      voidconnect​_phase(uvm_phase phase)
      voidwrite(BEFORE b)

    Class uvm​_random​_stimulus

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_blocking_put_portblocking​_put​_port
      bitm​_stop
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      logicnew(string name, uvm_component parent)
      voidgenerate​_stimulus(T t, int max_count)
      voidstop​_stimulus​_generation()
      stringget​_type​_name()

    Virtual class uvm​_subscriber

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      uvm_analysis_impanalysis​_export
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidwrite(T t)

    Virtual class uvm​_monitor

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()

    Class uvm​_driver

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      uvm_seq_item_pull_portseq​_item​_port
      uvm_seq_item_pull_portseq​_item​_prod​_if

      alias

      uvm_analysis_portrsp​_port
      REQreq
      RSPrsp
      stringtype​_name
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)

      new

      stringget​_type​_name()

    Class uvm​_push​_driver

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      uvm_blocking_put_impreq​_export
      uvm_analysis_portrsp​_port
      REQreq
      RSPrsp
      stringtype​_name
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidcheck​_port​_connections()
      voidend​_of​_elaboration​_phase(uvm_phase phase)
      voidput(REQ item)
      stringget​_type​_name()

    Virtual class uvm​_scoreboard

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()

    Virtual class uvm​_agent

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      uvm_active_passive_enumis​_active
      stringtype​_name
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidbuild​_phase(uvm_phase phase)
      stringget​_type​_name()
      uvm_active_passive_enumget​_is​_active()

    Virtual class uvm​_env

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()

    Virtual class uvm​_test

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()

    Class uvm​_sequence​_item

    • Extends: uvm​_transaction

    • Fields Summary
      TypeNameDescription
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      stringget​_type​_name()
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_full​_name()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      voiddo​_print(uvm_printer printer)

    Class uvm​_sequence​_process​_wrapper

      Description

      Utility class for tracking default_sequences

      Fields Summary
      TypeNameDescription
      unknownpid
      uvm_sequence_baseseq

    Class uvm​_sequencer​_base

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      uvm_sequence_request[]arb​_sequence​_q
      bit[]arb​_completed
      uvm_sequence_base[]lock​_list
      uvm_sequence_base[]reg​_sequences
      intm​_sequencer​_id
      intm​_lock​_arb​_size

      used for waiting processes

      intm​_arb​_size

      used for waiting processes

      intm​_wait​_for​_item​_sequence​_id
      intm​_wait​_for​_item​_transaction​_id
      intm​_wait​_relevant​_count
      intm​_max​_zero​_time​_wait​_relevant​_count
      timem​_last​_wait​_relevant​_time
      uvm_sequencer_arb_modem​_arbitration
      intg​_request​_id
      intg​_sequence​_id
      intg​_sequencer​_id
      uvm_sequence_process_wrapper[]m​_default​_sequences
      intm​_is​_relevant​_completed
      bitm​_auto​_item​_recording
      intcount
      intm​_random​_count
      intm​_exhaustive​_count
      intm​_simple​_count
      intmax​_random​_count
      intmax​_random​_depth
      stringdefault​_sequence
      bitm​_default​_seq​_set
      string[]sequences
      int[]sequence​_ids
      intseq​_kind
      Method Summary
      TypeMethodDescription
      uvm_sequencer_basenew(string name, uvm_component parent)
      bitis​_child(uvm_sequence_base parent, uvm_sequence_base child)
      integeruser​_priority​_arbitration(integer[] avail_sequences)
      voidexecute​_item(uvm_sequence_item item)
      voidstart​_phase​_sequence(uvm_phase phase)
      voidstop​_phase​_sequence(uvm_phase phase)
      voidwait​_for​_grant(uvm_sequence_base sequence_ptr, int item_priority, bit lock_request)
      voidwait​_for​_item​_done(uvm_sequence_base sequence_ptr, int transaction_id)
      bitis​_blocked(uvm_sequence_base sequence_ptr)
      bithas​_lock(uvm_sequence_base sequence_ptr)
      voidlock(uvm_sequence_base sequence_ptr)
      voidgrab(uvm_sequence_base sequence_ptr)
      voidunlock(uvm_sequence_base sequence_ptr)
      voidungrab(uvm_sequence_base sequence_ptr)
      voidstop​_sequences()
      bitis​_grabbed()
      uvm_sequence_basecurrent​_grabber()
      bithas​_do​_available()
      voidset​_arbitration(UVM_SEQ_ARB_TYPE val)
      UVM_SEQ_ARB_TYPEget​_arbitration()
      voidwait​_for​_sequences()
      voidsend​_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize)
      voidset​_max​_zero​_time​_wait​_relevant​_count(int new_val)
      voidgrant​_queued​_locks()
      voidm​_select​_sequence()
      intm​_choose​_next​_request()
      voidm​_wait​_for​_arbitration​_completed(int request_id)
      voidm​_set​_arbitration​_completed(int request_id)
      voidm​_lock​_req(uvm_sequence_base sequence_ptr, bit lock)
      voidm​_unlock​_req(uvm_sequence_base sequence_ptr)
      voidremove​_sequence​_from​_queues(uvm_sequence_base sequence_ptr)
      voidm​_sequence​_exiting(uvm_sequence_base sequence_ptr)
      voidkill​_sequence(uvm_sequence_base sequence_ptr)
      voidanalysis​_write(uvm_sequence_item t)
      voidbuild()
      voidbuild​_phase(uvm_phase phase)
      voiddo​_print(uvm_printer printer)
      intm​_register​_sequence(uvm_sequence_base sequence_ptr)
      voidm​_unregister​_sequence(int sequence_id)
      uvm_sequence_basem​_find​_sequence(int sequence_id)
      voidm​_update​_lists()
      stringconvert2string()
      intm​_find​_number​_driver​_connections()
      voidm​_wait​_arb​_not​_equal()
      voidm​_wait​_for​_available​_sequence()
      intm​_get​_seq​_item​_priority(uvm_sequence_request seq_q_entry)
      voiddisable​_auto​_item​_recording()
      bitis​_auto​_item​_recording​_enabled()
      voidadd​_sequence(string type_name)
      voidremove​_sequence(string type_name)
      voidset​_sequences​_queue(string[] sequencer_sequence_lib)
      voidstart​_default​_sequence()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      intnum​_sequences()
      voidm​_add​_builtin​_seqs(bit add_simple)
      voidrun​_phase(uvm_phase phase)

    Class uvm​_sequence​_request

      Fields Summary
      TypeNameDescription
      bitgrant
      intsequence​_id
      intrequest​_id
      intitem​_priority
      unknownprocess​_id
      seq_req_trequest
      uvm_sequence_basesequence​_ptr

    Class uvm​_sequencer​_analysis​_fifo

      Fields Summary
      TypeNameDescription
      uvm_analysis_impanalysis​_export
      uvm_sequencer_basesequencer​_ptr
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_report_handlerm​_rh
      intenable​_stop​_interrupt
      bitm​_config​_deprecated​_warned
      bitm​_config​_set
      bitprint​_config​_matches
      bitprint​_enabled
      uvm_tr_databasetr​_database

      Variable: tr_database

      Specifies the <uvm_tr_database> object to use for <begin_tr> and other methods in the .
      Default is <uvm_coreservice_t::get_default_tr_database>.

      uvm_domainm​_domain

      set_domain stores our domain handle

      uvm_phase[]m​_phase​_imps

      functors to override ovm_root defaults

      uvm_phasem​_current​_phase

      the most recently executed phase

      unknownm​_phase​_process
      bitm​_build​_done
      intm​_phasing​_active
      uvm_componentm​_parent
      uvm_component[]m​_children
      uvm_component[]m​_children​_by​_handle
      uvm_tr_streamm​_main​_stream
      unknown[]m​_streams
      uvm_recorder[]m​_tr​_h
      stringm​_name
      stringtype​_name
      uvm_event_poolevent​_pool
      intrecording​_detail
      m_verbosity_setting[]m​_verbosity​_settings
      m_verbosity_setting[]m​_time​_settings
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_action
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_sev
      uvm_put_impput​_export
      uvm_get_peek_impget​_peek​_export
      uvm_analysis_portput​_ap
      uvm_analysis_portget​_ap
      uvm_put_impblocking​_put​_export
      uvm_put_impnonblocking​_put​_export
      uvm_get_peek_impblocking​_get​_export
      uvm_get_peek_impnonblocking​_get​_export
      uvm_get_peek_impget​_export
      uvm_get_peek_impblocking​_peek​_export
      uvm_get_peek_impnonblocking​_peek​_export
      uvm_get_peek_imppeek​_export
      uvm_get_peek_impblocking​_get​_peek​_export
      uvm_get_peek_impnonblocking​_get​_peek​_export
      anonymousm
      intm​_size
      intm​_pending​_blocked​_gets
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidwrite(RSP t)

      void

      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      intget​_report​_verbosity​_level(uvm_severity severity, string id)
      intget​_report​_max​_verbosity​_level()
      voidset​_report​_verbosity​_level(int verbosity_level)
      voidset​_report​_id​_verbosity(string id, int verbosity)

      Function: set_report_id_verbosity

      voidset​_report​_severity​_id​_verbosity(uvm_severity severity, string id, int verbosity)
      intget​_report​_action(uvm_severity severity, string id)
      voidset​_report​_severity​_action(uvm_severity severity, uvm_action action)

      Function: set_report_severity_action

      voidset​_report​_id​_action(string id, uvm_action action)

      Function: set_report_id_action

      voidset​_report​_severity​_id​_action(uvm_severity severity, string id, uvm_action action)
      intget​_report​_file​_handle(uvm_severity severity, string id)
      voidset​_report​_default​_file(UVM_FILE file)
      voidset​_report​_id​_file(string id, UVM_FILE file)
      voidset​_report​_severity​_file(uvm_severity severity, UVM_FILE file)

      Function: set_report_severity_file

      voidset​_report​_severity​_id​_file(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_severity​_override(uvm_severity cur_severity, uvm_severity new_severity)

      Function: set_report_severity_override

      voidset​_report​_severity​_id​_override(uvm_severity cur_severity, string id, uvm_severity new_severity)

      Function: set_report_severity_id_override

      These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~.

      voidset​_report​_handler(uvm_report_handler handler)
      uvm_report_handlerget​_report​_handler()
      voidreset​_report​_handler()
      bitreport​_info​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_error​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_warning​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_fatal​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_hook(string id, string message, int verbosity, string filename, int line)
      voidreport​_header(UVM_FILE file)
      voidreport​_summarize(UVM_FILE file)
      voiddie()
      voidset​_report​_max​_quit​_count(int max_count)
      uvm_report_serverget​_report​_server()
      voiddump​_report​_state()
      uvm_componentget​_parent()
      voidget​_children(uvm_component[] children)
      uvm_componentget​_child(string name)
      intget​_next​_child(string name)
      intget​_first​_child(string name)
      intget​_num​_children()
      inthas​_child(string name)
      uvm_componentlookup(string name)
      intget​_depth()
      voidbuild​_phase(uvm_phase phase)

      turn off auto config

      voidbuild()
      voidconnect​_phase(uvm_phase phase)
      voidconnect()
      voidend​_of​_elaboration​_phase(uvm_phase phase)
      voidend​_of​_elaboration()
      voidstart​_of​_simulation​_phase(uvm_phase phase)
      voidstart​_of​_simulation()
      voidrun​_phase(uvm_phase phase)
      voidrun()
      voidpre​_reset​_phase(uvm_phase phase)
      voidreset​_phase(uvm_phase phase)
      voidpost​_reset​_phase(uvm_phase phase)
      voidpre​_configure​_phase(uvm_phase phase)
      voidconfigure​_phase(uvm_phase phase)
      voidpost​_configure​_phase(uvm_phase phase)
      voidpre​_main​_phase(uvm_phase phase)
      voidmain​_phase(uvm_phase phase)
      voidpost​_main​_phase(uvm_phase phase)
      voidpre​_shutdown​_phase(uvm_phase phase)
      voidshutdown​_phase(uvm_phase phase)
      voidpost​_shutdown​_phase(uvm_phase phase)
      voidextract​_phase(uvm_phase phase)
      voidextract()
      voidcheck​_phase(uvm_phase phase)
      voidcheck()
      voidreport​_phase(uvm_phase phase)
      voidreport()
      voidfinal​_phase(uvm_phase phase)
      voidphase​_started(uvm_phase phase)
      voidphase​_ready​_to​_end(uvm_phase phase)
      voidphase​_ended(uvm_phase phase)
      voidset​_domain(uvm_domain domain, int hier)
      uvm_domainget​_domain()
      voiddefine​_domain(uvm_domain domain)
      voidset​_phase​_imp(uvm_phase phase, uvm_phase imp, int hier)
      voidsuspend()
      voidresume()
      stringstatus()
      voidkill()
      voiddo​_kill​_all()
      voidstop​_phase(uvm_phase phase)
      voidstop(string ph_name)
      voidresolve​_bindings()
      stringmassage​_scope(string scope)
      voidset​_config​_int(string inst_name, string field_name, uvm_bitstream_t value)
      voidset​_config​_string(string inst_name, string field_name, string value)
      voidset​_config​_object(string inst_name, string field_name, uvm_object value, bit clone)
      bitget​_config​_int(string field_name, uvm_bitstream_t value)
      bitget​_config​_string(string field_name, string value)
      bitget​_config​_object(string field_name, uvm_object value, bit clone)
      voidcheck​_config​_usage(bit recurse)
      voidapply​_config​_settings(bit verbose)
      voidprint​_config​_settings(string field, uvm_component comp, bit recurse)
      voidprint​_config(bit recurse, bit audit)
      voidprint​_config​_with​_audit(bit recurse)
      voidraised(uvm_objection objection, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      uvm_componentcreate​_component(string requested_type_name, string name)
      uvm_objectcreate​_object(string requested_type_name, string name)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override​_by​_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type)
      voidset​_type​_override(string original_type_name, string override_type_name, bit replace)
      voidset​_inst​_override(string relative_inst_path, string original_type_name, string override_type_name)
      voidprint​_override​_info(string requested_type_name, string name)
      voidset​_report​_id​_verbosity​_hier(string id, int verbosity)
      voidset​_report​_severity​_id​_verbosity​_hier(uvm_severity severity, string id, int verbosity)
      voidset​_report​_severity​_action​_hier(uvm_severity severity, uvm_action action)
      voidset​_report​_id​_action​_hier(string id, uvm_action action)
      voidset​_report​_severity​_id​_action​_hier(uvm_severity severity, string id, uvm_action action)
      voidset​_report​_default​_file​_hier(UVM_FILE file)
      voidset​_report​_severity​_file​_hier(uvm_severity severity, UVM_FILE file)
      voidset​_report​_id​_file​_hier(string id, UVM_FILE file)
      voidset​_report​_severity​_id​_file​_hier(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_verbosity​_level​_hier(int verbosity)
      voidpre​_abort()
      voidaccept​_tr(uvm_transaction tr, time accept_time)
      voiddo​_accept​_tr(uvm_transaction tr)
      integerbegin​_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle)
      integerbegin​_child​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voiddo​_begin​_tr(uvm_transaction tr, string stream_name, integer tr_handle)
      voidend​_tr(uvm_transaction tr, time end_time, bit free_handle)
      voiddo​_end​_tr(uvm_transaction tr, integer tr_handle)
      integerrecord​_error​_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active)
      integerrecord​_event​_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active)
      uvm_tr_streamget​_tr​_stream(string name, string stream_type_name)
      voidfree​_tr​_stream(uvm_tr_stream stream)
      uvm_tr_databasem​_get​_tr​_database()
      bitm​_add​_child(uvm_component child)
      voidm​_set​_full​_name()
      voiddo​_resolve​_bindings()
      voiddo​_flush()
      voidflush()
      voidm​_extract​_name(string name, string leaf, string remainder)
      integerm​_begin​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voidm​_set​_cl​_msg​_args()
      voidm​_set​_cl​_verb()
      voidm​_set​_cl​_action()
      voidm​_set​_cl​_sev()
      voidm​_apply​_verbosity​_settings(uvm_phase phase)
      voidm​_do​_pre​_abort()
      intsize()
      voidput(T t)
      voidget(T t)
      voidpeek(T t)
      bittry​_put(T t)
      bittry​_get(T t)
      bittry​_peek(T t)
      bitcan​_put()
      bitcan​_get()
      bitcan​_peek()
      uvm_tlm_eventok​_to​_put()
      uvm_tlm_eventok​_to​_get()
      uvm_tlm_eventok​_to​_peek()
      bitis​_empty()
      bitis​_full()
      intused()

    Class uvm​_sequencer​_param​_base

    • Extends: uvm​_sequencer​_base

    • Fields Summary
      TypeNameDescription
      REQ[]m​_last​_req​_buffer
      RSP[]m​_last​_rsp​_buffer
      intm​_num​_last​_reqs
      intnum​_last​_items
      intm​_num​_last​_rsps
      intm​_num​_reqs​_sent
      intm​_num​_rsps​_received
      uvm_sequencer_analysis_fifosqr​_rsp​_analysis​_fifo
      uvm_analysis_exportrsp​_export
      uvm_tlm_fifom​_req​_fifo
      Method Summary
      TypeMethodDescription
      uvm_sequencer_param_basenew(string name, uvm_component parent)
      voidsend​_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize)
      REQget​_current​_item()

      Function: get_current_item

      Returns the request_item currently being executed by the sequencer. If the sequencer is not currently executing an item, this method will return ~null~.

      The sequencer is executing an item from the time that get_next_item or peek is called until the time that get or item_done is called.

      Note that a driver that only calls get() will never show a current item, since the item is completed at the same time as it is requested.

      intget​_num​_reqs​_sent()
      voidset​_num​_last​_reqs(int max)
      intget​_num​_last​_reqs()
      REQlast​_req(int n)

      Function: last_req

      Returns the last request item by default. If n is not 0, then it will get the n�th before last request item. If n is greater than the last request buffer size, the function will return ~null~.

      intget​_num​_rsps​_received()
      voidset​_num​_last​_rsps(int max)
      intget​_num​_last​_rsps()
      RSPlast​_rsp(int n)

      Function: last_rsp

      Returns the last response item by default. If n is not 0, then it will get the nth-before-last response item. If n is greater than the last response buffer size, the function will return ~null~.

      voidm​_last​_rsp​_push​_front(RSP item)
      voidput​_response(RSP t)
      voidbuild​_phase(uvm_phase phase)
      voidconnect​_phase(uvm_phase phase)
      voiddo​_print(uvm_printer printer)
      voidanalysis​_write(uvm_sequence_item t)
      voidm​_last​_req​_push​_front(REQ item)

    Class uvm​_sequencer

      Fields Summary
      TypeNameDescription
      bitsequence​_item​_requested
      bitget​_next​_item​_called
      uvm_seq_item_pull_impseq​_item​_export
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_report_handlerm​_rh
      intenable​_stop​_interrupt
      bitm​_config​_deprecated​_warned
      bitm​_config​_set
      bitprint​_config​_matches
      bitprint​_enabled
      uvm_tr_databasetr​_database

      Variable: tr_database

      Specifies the <uvm_tr_database> object to use for <begin_tr> and other methods in the .
      Default is <uvm_coreservice_t::get_default_tr_database>.

      uvm_domainm​_domain

      set_domain stores our domain handle

      uvm_phase[]m​_phase​_imps

      functors to override ovm_root defaults

      uvm_phasem​_current​_phase

      the most recently executed phase

      unknownm​_phase​_process
      bitm​_build​_done
      intm​_phasing​_active
      uvm_componentm​_parent
      uvm_component[]m​_children
      uvm_component[]m​_children​_by​_handle
      uvm_tr_streamm​_main​_stream
      unknown[]m​_streams
      uvm_recorder[]m​_tr​_h
      stringm​_name
      stringtype​_name
      uvm_event_poolevent​_pool
      intrecording​_detail
      m_verbosity_setting[]m​_verbosity​_settings
      m_verbosity_setting[]m​_time​_settings
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_action
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_sev
      uvm_sequence_request[]arb​_sequence​_q
      bit[]arb​_completed
      uvm_sequence_base[]lock​_list
      uvm_sequence_base[]reg​_sequences
      intm​_sequencer​_id
      intm​_lock​_arb​_size

      used for waiting processes

      intm​_arb​_size

      used for waiting processes

      intm​_wait​_for​_item​_sequence​_id
      intm​_wait​_for​_item​_transaction​_id
      intm​_wait​_relevant​_count
      intm​_max​_zero​_time​_wait​_relevant​_count
      timem​_last​_wait​_relevant​_time
      uvm_sequencer_arb_modem​_arbitration
      intg​_request​_id
      intg​_sequence​_id
      intg​_sequencer​_id
      uvm_sequence_process_wrapper[]m​_default​_sequences
      intm​_is​_relevant​_completed
      bitm​_auto​_item​_recording
      intcount
      intm​_random​_count
      intm​_exhaustive​_count
      intm​_simple​_count
      intmax​_random​_count
      intmax​_random​_depth
      stringdefault​_sequence
      bitm​_default​_seq​_set
      string[]sequences
      int[]sequence​_ids
      intseq​_kind
      REQ[]m​_last​_req​_buffer
      RSP[]m​_last​_rsp​_buffer
      intm​_num​_last​_reqs
      intnum​_last​_items
      intm​_num​_last​_rsps
      intm​_num​_reqs​_sent
      intm​_num​_rsps​_received
      uvm_sequencer_analysis_fifosqr​_rsp​_analysis​_fifo
      uvm_analysis_exportrsp​_export
      uvm_tlm_fifom​_req​_fifo
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_sequencernew(string name, uvm_component parent)
      voidstop​_sequences()
      stringget​_type​_name()
      voidget​_next​_item(REQ t)
      voidtry​_next​_item(REQ t)
      voiditem​_done(RSP item)
      voidput(RSP t)
      voidget(REQ t)
      voidpeek(REQ t)
      voiditem​_done​_trigger(RSP item)
      RSPitem​_done​_get​_trigger​_data()
      intm​_find​_number​_driver​_connections()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      intget​_report​_verbosity​_level(uvm_severity severity, string id)
      intget​_report​_max​_verbosity​_level()
      voidset​_report​_verbosity​_level(int verbosity_level)
      voidset​_report​_id​_verbosity(string id, int verbosity)

      Function: set_report_id_verbosity

      voidset​_report​_severity​_id​_verbosity(uvm_severity severity, string id, int verbosity)
      intget​_report​_action(uvm_severity severity, string id)
      voidset​_report​_severity​_action(uvm_severity severity, uvm_action action)

      Function: set_report_severity_action

      voidset​_report​_id​_action(string id, uvm_action action)

      Function: set_report_id_action

      voidset​_report​_severity​_id​_action(uvm_severity severity, string id, uvm_action action)
      intget​_report​_file​_handle(uvm_severity severity, string id)
      voidset​_report​_default​_file(UVM_FILE file)
      voidset​_report​_id​_file(string id, UVM_FILE file)
      voidset​_report​_severity​_file(uvm_severity severity, UVM_FILE file)

      Function: set_report_severity_file

      voidset​_report​_severity​_id​_file(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_severity​_override(uvm_severity cur_severity, uvm_severity new_severity)

      Function: set_report_severity_override

      voidset​_report​_severity​_id​_override(uvm_severity cur_severity, string id, uvm_severity new_severity)

      Function: set_report_severity_id_override

      These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~.

      voidset​_report​_handler(uvm_report_handler handler)
      uvm_report_handlerget​_report​_handler()
      voidreset​_report​_handler()
      bitreport​_info​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_error​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_warning​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_fatal​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_hook(string id, string message, int verbosity, string filename, int line)
      voidreport​_header(UVM_FILE file)
      voidreport​_summarize(UVM_FILE file)
      voiddie()
      voidset​_report​_max​_quit​_count(int max_count)
      uvm_report_serverget​_report​_server()
      voiddump​_report​_state()
      uvm_componentget​_parent()
      voidget​_children(uvm_component[] children)
      uvm_componentget​_child(string name)
      intget​_next​_child(string name)
      intget​_first​_child(string name)
      intget​_num​_children()
      inthas​_child(string name)
      uvm_componentlookup(string name)
      intget​_depth()
      voidbuild​_phase(uvm_phase phase)
      voidbuild()
      voidconnect​_phase(uvm_phase phase)
      voidconnect()
      voidend​_of​_elaboration​_phase(uvm_phase phase)
      voidend​_of​_elaboration()
      voidstart​_of​_simulation​_phase(uvm_phase phase)
      voidstart​_of​_simulation()
      voidrun​_phase(uvm_phase phase)
      voidrun()
      voidpre​_reset​_phase(uvm_phase phase)
      voidreset​_phase(uvm_phase phase)
      voidpost​_reset​_phase(uvm_phase phase)
      voidpre​_configure​_phase(uvm_phase phase)
      voidconfigure​_phase(uvm_phase phase)
      voidpost​_configure​_phase(uvm_phase phase)
      voidpre​_main​_phase(uvm_phase phase)
      voidmain​_phase(uvm_phase phase)
      voidpost​_main​_phase(uvm_phase phase)
      voidpre​_shutdown​_phase(uvm_phase phase)
      voidshutdown​_phase(uvm_phase phase)
      voidpost​_shutdown​_phase(uvm_phase phase)
      voidextract​_phase(uvm_phase phase)
      voidextract()
      voidcheck​_phase(uvm_phase phase)
      voidcheck()
      voidreport​_phase(uvm_phase phase)
      voidreport()
      voidfinal​_phase(uvm_phase phase)
      voidphase​_started(uvm_phase phase)
      voidphase​_ready​_to​_end(uvm_phase phase)
      voidphase​_ended(uvm_phase phase)
      voidset​_domain(uvm_domain domain, int hier)
      uvm_domainget​_domain()
      voiddefine​_domain(uvm_domain domain)
      voidset​_phase​_imp(uvm_phase phase, uvm_phase imp, int hier)
      voidsuspend()
      voidresume()
      stringstatus()
      voidkill()
      voiddo​_kill​_all()
      voidstop​_phase(uvm_phase phase)
      voidstop(string ph_name)
      voidresolve​_bindings()
      stringmassage​_scope(string scope)
      voidset​_config​_int(string inst_name, string field_name, uvm_bitstream_t value)
      voidset​_config​_string(string inst_name, string field_name, string value)
      voidset​_config​_object(string inst_name, string field_name, uvm_object value, bit clone)
      bitget​_config​_int(string field_name, uvm_bitstream_t value)
      bitget​_config​_string(string field_name, string value)
      bitget​_config​_object(string field_name, uvm_object value, bit clone)
      voidcheck​_config​_usage(bit recurse)
      voidapply​_config​_settings(bit verbose)
      voidprint​_config​_settings(string field, uvm_component comp, bit recurse)
      voidprint​_config(bit recurse, bit audit)
      voidprint​_config​_with​_audit(bit recurse)
      voidraised(uvm_objection objection, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      uvm_componentcreate​_component(string requested_type_name, string name)
      uvm_objectcreate​_object(string requested_type_name, string name)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override​_by​_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type)
      voidset​_type​_override(string original_type_name, string override_type_name, bit replace)
      voidset​_inst​_override(string relative_inst_path, string original_type_name, string override_type_name)
      voidprint​_override​_info(string requested_type_name, string name)
      voidset​_report​_id​_verbosity​_hier(string id, int verbosity)
      voidset​_report​_severity​_id​_verbosity​_hier(uvm_severity severity, string id, int verbosity)
      voidset​_report​_severity​_action​_hier(uvm_severity severity, uvm_action action)
      voidset​_report​_id​_action​_hier(string id, uvm_action action)
      voidset​_report​_severity​_id​_action​_hier(uvm_severity severity, string id, uvm_action action)
      voidset​_report​_default​_file​_hier(UVM_FILE file)
      voidset​_report​_severity​_file​_hier(uvm_severity severity, UVM_FILE file)
      voidset​_report​_id​_file​_hier(string id, UVM_FILE file)
      voidset​_report​_severity​_id​_file​_hier(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_verbosity​_level​_hier(int verbosity)
      voidpre​_abort()
      voidaccept​_tr(uvm_transaction tr, time accept_time)
      voiddo​_accept​_tr(uvm_transaction tr)
      integerbegin​_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle)
      integerbegin​_child​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voiddo​_begin​_tr(uvm_transaction tr, string stream_name, integer tr_handle)
      voidend​_tr(uvm_transaction tr, time end_time, bit free_handle)
      voiddo​_end​_tr(uvm_transaction tr, integer tr_handle)
      integerrecord​_error​_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active)
      integerrecord​_event​_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active)
      uvm_tr_streamget​_tr​_stream(string name, string stream_type_name)
      voidfree​_tr​_stream(uvm_tr_stream stream)
      uvm_tr_databasem​_get​_tr​_database()
      bitm​_add​_child(uvm_component child)
      voidm​_set​_full​_name()
      voiddo​_resolve​_bindings()
      voiddo​_flush()
      voidflush()
      voidm​_extract​_name(string name, string leaf, string remainder)
      integerm​_begin​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voidm​_set​_cl​_msg​_args()
      voidm​_set​_cl​_verb()
      voidm​_set​_cl​_action()
      voidm​_set​_cl​_sev()
      voidm​_apply​_verbosity​_settings(uvm_phase phase)
      voidm​_do​_pre​_abort()
      bitis​_child(uvm_sequence_base parent, uvm_sequence_base child)
      integeruser​_priority​_arbitration(integer[] avail_sequences)
      voidexecute​_item(uvm_sequence_item item)
      voidstart​_phase​_sequence(uvm_phase phase)
      voidstop​_phase​_sequence(uvm_phase phase)
      voidwait​_for​_grant(uvm_sequence_base sequence_ptr, int item_priority, bit lock_request)
      voidwait​_for​_item​_done(uvm_sequence_base sequence_ptr, int transaction_id)
      bitis​_blocked(uvm_sequence_base sequence_ptr)
      bithas​_lock(uvm_sequence_base sequence_ptr)
      voidlock(uvm_sequence_base sequence_ptr)
      voidgrab(uvm_sequence_base sequence_ptr)
      voidunlock(uvm_sequence_base sequence_ptr)
      voidungrab(uvm_sequence_base sequence_ptr)
      bitis​_grabbed()
      uvm_sequence_basecurrent​_grabber()
      bithas​_do​_available()
      voidset​_arbitration(UVM_SEQ_ARB_TYPE val)
      UVM_SEQ_ARB_TYPEget​_arbitration()
      voidwait​_for​_sequences()
      voidsend​_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize)
      voidset​_max​_zero​_time​_wait​_relevant​_count(int new_val)
      voidgrant​_queued​_locks()
      voidm​_select​_sequence()
      intm​_choose​_next​_request()
      voidm​_wait​_for​_arbitration​_completed(int request_id)
      voidm​_set​_arbitration​_completed(int request_id)
      voidm​_lock​_req(uvm_sequence_base sequence_ptr, bit lock)
      voidm​_unlock​_req(uvm_sequence_base sequence_ptr)
      voidremove​_sequence​_from​_queues(uvm_sequence_base sequence_ptr)
      voidm​_sequence​_exiting(uvm_sequence_base sequence_ptr)
      voidkill​_sequence(uvm_sequence_base sequence_ptr)
      voidanalysis​_write(uvm_sequence_item t)
      intm​_register​_sequence(uvm_sequence_base sequence_ptr)
      voidm​_unregister​_sequence(int sequence_id)
      uvm_sequence_basem​_find​_sequence(int sequence_id)
      voidm​_update​_lists()
      voidm​_wait​_arb​_not​_equal()
      voidm​_wait​_for​_available​_sequence()
      intm​_get​_seq​_item​_priority(uvm_sequence_request seq_q_entry)
      voiddisable​_auto​_item​_recording()
      bitis​_auto​_item​_recording​_enabled()
      voidadd​_sequence(string type_name)
      voidremove​_sequence(string type_name)
      voidset​_sequences​_queue(string[] sequencer_sequence_lib)
      voidstart​_default​_sequence()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      intnum​_sequences()
      voidm​_add​_builtin​_seqs(bit add_simple)
      REQget​_current​_item()

      Function: get_current_item

      Returns the request_item currently being executed by the sequencer. If the sequencer is not currently executing an item, this method will return ~null~.

      The sequencer is executing an item from the time that get_next_item or peek is called until the time that get or item_done is called.

      Note that a driver that only calls get() will never show a current item, since the item is completed at the same time as it is requested.

      intget​_num​_reqs​_sent()
      voidset​_num​_last​_reqs(int max)
      intget​_num​_last​_reqs()
      REQlast​_req(int n)

      Function: last_req

      Returns the last request item by default. If n is not 0, then it will get the n�th before last request item. If n is greater than the last request buffer size, the function will return ~null~.

      intget​_num​_rsps​_received()
      voidset​_num​_last​_rsps(int max)
      intget​_num​_last​_rsps()
      RSPlast​_rsp(int n)

      Function: last_rsp

      Returns the last response item by default. If n is not 0, then it will get the nth-before-last response item. If n is greater than the last response buffer size, the function will return ~null~.

      voidm​_last​_rsp​_push​_front(RSP item)
      voidput​_response(RSP t)
      voidm​_last​_req​_push​_front(REQ item)

    Class uvm​_push​_sequencer

      Fields Summary
      TypeNameDescription
      uvm_blocking_put_portreq​_port

      Port: req_port

      The push sequencer requires access to a blocking put interface. A continuous stream of sequence items are sent out this port, based on the list of available sequences loaded into this sequencer.

      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_report_handlerm​_rh
      intenable​_stop​_interrupt
      bitm​_config​_deprecated​_warned
      bitm​_config​_set
      bitprint​_config​_matches
      bitprint​_enabled
      uvm_tr_databasetr​_database

      Variable: tr_database

      Specifies the <uvm_tr_database> object to use for <begin_tr> and other methods in the .
      Default is <uvm_coreservice_t::get_default_tr_database>.

      uvm_domainm​_domain

      set_domain stores our domain handle

      uvm_phase[]m​_phase​_imps

      functors to override ovm_root defaults

      uvm_phasem​_current​_phase

      the most recently executed phase

      unknownm​_phase​_process
      bitm​_build​_done
      intm​_phasing​_active
      uvm_componentm​_parent
      uvm_component[]m​_children
      uvm_component[]m​_children​_by​_handle
      uvm_tr_streamm​_main​_stream
      unknown[]m​_streams
      uvm_recorder[]m​_tr​_h
      stringm​_name
      stringtype​_name
      uvm_event_poolevent​_pool
      intrecording​_detail
      m_verbosity_setting[]m​_verbosity​_settings
      m_verbosity_setting[]m​_time​_settings
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_action
      uvm_cmdline_parsed_arg_t[]m​_uvm​_applied​_cl​_sev
      uvm_sequence_request[]arb​_sequence​_q
      bit[]arb​_completed
      uvm_sequence_base[]lock​_list
      uvm_sequence_base[]reg​_sequences
      intm​_sequencer​_id
      intm​_lock​_arb​_size

      used for waiting processes

      intm​_arb​_size

      used for waiting processes

      intm​_wait​_for​_item​_sequence​_id
      intm​_wait​_for​_item​_transaction​_id
      intm​_wait​_relevant​_count
      intm​_max​_zero​_time​_wait​_relevant​_count
      timem​_last​_wait​_relevant​_time
      uvm_sequencer_arb_modem​_arbitration
      intg​_request​_id
      intg​_sequence​_id
      intg​_sequencer​_id
      uvm_sequence_process_wrapper[]m​_default​_sequences
      intm​_is​_relevant​_completed
      bitm​_auto​_item​_recording
      intcount
      intm​_random​_count
      intm​_exhaustive​_count
      intm​_simple​_count
      intmax​_random​_count
      intmax​_random​_depth
      stringdefault​_sequence
      bitm​_default​_seq​_set
      string[]sequences
      int[]sequence​_ids
      intseq​_kind
      REQ[]m​_last​_req​_buffer
      RSP[]m​_last​_rsp​_buffer
      intm​_num​_last​_reqs
      intnum​_last​_items
      intm​_num​_last​_rsps
      intm​_num​_reqs​_sent
      intm​_num​_rsps​_received
      uvm_sequencer_analysis_fifosqr​_rsp​_analysis​_fifo
      uvm_analysis_exportrsp​_export
      uvm_tlm_fifom​_req​_fifo
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)

      Function: new

      Standard component constructor that creates an instance of this class using the given ~name~ and ~parent~, if any.

      voidrun​_phase(uvm_phase phase)

      Task: run_phase

      The push sequencer continuously selects from its list of available sequences and sends the next item from the selected sequence out its <req_port> using req_port.put(item). Typically, the req_port would be connected to the req_export on an instance of a <uvm_push_driver #(REQ,RSP)>, which would be responsible for executing the item.

      intm​_find​_number​_driver​_connections()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_wrapperget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      intget​_report​_verbosity​_level(uvm_severity severity, string id)
      intget​_report​_max​_verbosity​_level()
      voidset​_report​_verbosity​_level(int verbosity_level)
      voidset​_report​_id​_verbosity(string id, int verbosity)

      Function: set_report_id_verbosity

      voidset​_report​_severity​_id​_verbosity(uvm_severity severity, string id, int verbosity)
      intget​_report​_action(uvm_severity severity, string id)
      voidset​_report​_severity​_action(uvm_severity severity, uvm_action action)

      Function: set_report_severity_action

      voidset​_report​_id​_action(string id, uvm_action action)

      Function: set_report_id_action

      voidset​_report​_severity​_id​_action(uvm_severity severity, string id, uvm_action action)
      intget​_report​_file​_handle(uvm_severity severity, string id)
      voidset​_report​_default​_file(UVM_FILE file)
      voidset​_report​_id​_file(string id, UVM_FILE file)
      voidset​_report​_severity​_file(uvm_severity severity, UVM_FILE file)

      Function: set_report_severity_file

      voidset​_report​_severity​_id​_file(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_severity​_override(uvm_severity cur_severity, uvm_severity new_severity)

      Function: set_report_severity_override

      voidset​_report​_severity​_id​_override(uvm_severity cur_severity, string id, uvm_severity new_severity)

      Function: set_report_severity_id_override

      These methods provide the ability to upgrade or downgrade a message in terms of severity given ~severity~ and ~id~. An upgrade or downgrade for a specific ~id~ takes precedence over an upgrade or downgrade associated with a ~severity~.

      voidset​_report​_handler(uvm_report_handler handler)
      uvm_report_handlerget​_report​_handler()
      voidreset​_report​_handler()
      bitreport​_info​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_error​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_warning​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_fatal​_hook(string id, string message, int verbosity, string filename, int line)
      bitreport​_hook(string id, string message, int verbosity, string filename, int line)
      voidreport​_header(UVM_FILE file)
      voidreport​_summarize(UVM_FILE file)
      voiddie()
      voidset​_report​_max​_quit​_count(int max_count)
      uvm_report_serverget​_report​_server()
      voiddump​_report​_state()
      uvm_componentget​_parent()
      voidget​_children(uvm_component[] children)
      uvm_componentget​_child(string name)
      intget​_next​_child(string name)
      intget​_first​_child(string name)
      intget​_num​_children()
      inthas​_child(string name)
      uvm_componentlookup(string name)
      intget​_depth()
      voidbuild​_phase(uvm_phase phase)
      voidbuild()
      voidconnect​_phase(uvm_phase phase)
      voidconnect()
      voidend​_of​_elaboration​_phase(uvm_phase phase)
      voidend​_of​_elaboration()
      voidstart​_of​_simulation​_phase(uvm_phase phase)
      voidstart​_of​_simulation()
      voidrun()
      voidpre​_reset​_phase(uvm_phase phase)
      voidreset​_phase(uvm_phase phase)
      voidpost​_reset​_phase(uvm_phase phase)
      voidpre​_configure​_phase(uvm_phase phase)
      voidconfigure​_phase(uvm_phase phase)
      voidpost​_configure​_phase(uvm_phase phase)
      voidpre​_main​_phase(uvm_phase phase)
      voidmain​_phase(uvm_phase phase)
      voidpost​_main​_phase(uvm_phase phase)
      voidpre​_shutdown​_phase(uvm_phase phase)
      voidshutdown​_phase(uvm_phase phase)
      voidpost​_shutdown​_phase(uvm_phase phase)
      voidextract​_phase(uvm_phase phase)
      voidextract()
      voidcheck​_phase(uvm_phase phase)
      voidcheck()
      voidreport​_phase(uvm_phase phase)
      voidreport()
      voidfinal​_phase(uvm_phase phase)
      voidphase​_started(uvm_phase phase)
      voidphase​_ready​_to​_end(uvm_phase phase)
      voidphase​_ended(uvm_phase phase)
      voidset​_domain(uvm_domain domain, int hier)
      uvm_domainget​_domain()
      voiddefine​_domain(uvm_domain domain)
      voidset​_phase​_imp(uvm_phase phase, uvm_phase imp, int hier)
      voidsuspend()
      voidresume()
      stringstatus()
      voidkill()
      voiddo​_kill​_all()
      voidstop​_phase(uvm_phase phase)
      voidstop(string ph_name)
      voidresolve​_bindings()
      stringmassage​_scope(string scope)
      voidset​_config​_int(string inst_name, string field_name, uvm_bitstream_t value)
      voidset​_config​_string(string inst_name, string field_name, string value)
      voidset​_config​_object(string inst_name, string field_name, uvm_object value, bit clone)
      bitget​_config​_int(string field_name, uvm_bitstream_t value)
      bitget​_config​_string(string field_name, string value)
      bitget​_config​_object(string field_name, uvm_object value, bit clone)
      voidcheck​_config​_usage(bit recurse)
      voidapply​_config​_settings(bit verbose)
      voidprint​_config​_settings(string field, uvm_component comp, bit recurse)
      voidprint​_config(bit recurse, bit audit)
      voidprint​_config​_with​_audit(bit recurse)
      voidraised(uvm_objection objection, uvm_object source_obj, string description, int count)
      voiddropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      voidall​_dropped(uvm_objection objection, uvm_object source_obj, string description, int count)
      uvm_componentcreate​_component(string requested_type_name, string name)
      uvm_objectcreate​_object(string requested_type_name, string name)
      voidset​_type​_override​_by​_type(uvm_object_wrapper original_type, uvm_object_wrapper override_type, bit replace)
      voidset​_inst​_override​_by​_type(string relative_inst_path, uvm_object_wrapper original_type, uvm_object_wrapper override_type)
      voidset​_type​_override(string original_type_name, string override_type_name, bit replace)
      voidset​_inst​_override(string relative_inst_path, string original_type_name, string override_type_name)
      voidprint​_override​_info(string requested_type_name, string name)
      voidset​_report​_id​_verbosity​_hier(string id, int verbosity)
      voidset​_report​_severity​_id​_verbosity​_hier(uvm_severity severity, string id, int verbosity)
      voidset​_report​_severity​_action​_hier(uvm_severity severity, uvm_action action)
      voidset​_report​_id​_action​_hier(string id, uvm_action action)
      voidset​_report​_severity​_id​_action​_hier(uvm_severity severity, string id, uvm_action action)
      voidset​_report​_default​_file​_hier(UVM_FILE file)
      voidset​_report​_severity​_file​_hier(uvm_severity severity, UVM_FILE file)
      voidset​_report​_id​_file​_hier(string id, UVM_FILE file)
      voidset​_report​_severity​_id​_file​_hier(uvm_severity severity, string id, UVM_FILE file)
      voidset​_report​_verbosity​_level​_hier(int verbosity)
      voidpre​_abort()
      voidaccept​_tr(uvm_transaction tr, time accept_time)
      voiddo​_accept​_tr(uvm_transaction tr)
      integerbegin​_tr(uvm_transaction tr, string stream_name, string label, string desc, time begin_time, integer parent_handle)
      integerbegin​_child​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voiddo​_begin​_tr(uvm_transaction tr, string stream_name, integer tr_handle)
      voidend​_tr(uvm_transaction tr, time end_time, bit free_handle)
      voiddo​_end​_tr(uvm_transaction tr, integer tr_handle)
      integerrecord​_error​_tr(string stream_name, uvm_object info, string label, string desc, time error_time, bit keep_active)
      integerrecord​_event​_tr(string stream_name, uvm_object info, string label, string desc, time event_time, bit keep_active)
      uvm_tr_streamget​_tr​_stream(string name, string stream_type_name)
      voidfree​_tr​_stream(uvm_tr_stream stream)
      uvm_tr_databasem​_get​_tr​_database()
      bitm​_add​_child(uvm_component child)
      voidm​_set​_full​_name()
      voiddo​_resolve​_bindings()
      voiddo​_flush()
      voidflush()
      voidm​_extract​_name(string name, string leaf, string remainder)
      integerm​_begin​_tr(uvm_transaction tr, integer parent_handle, string stream_name, string label, string desc, time begin_time)
      voidm​_set​_cl​_msg​_args()
      voidm​_set​_cl​_verb()
      voidm​_set​_cl​_action()
      voidm​_set​_cl​_sev()
      voidm​_apply​_verbosity​_settings(uvm_phase phase)
      voidm​_do​_pre​_abort()
      bitis​_child(uvm_sequence_base parent, uvm_sequence_base child)
      integeruser​_priority​_arbitration(integer[] avail_sequences)
      voidexecute​_item(uvm_sequence_item item)
      voidstart​_phase​_sequence(uvm_phase phase)
      voidstop​_phase​_sequence(uvm_phase phase)
      voidwait​_for​_grant(uvm_sequence_base sequence_ptr, int item_priority, bit lock_request)
      voidwait​_for​_item​_done(uvm_sequence_base sequence_ptr, int transaction_id)
      bitis​_blocked(uvm_sequence_base sequence_ptr)
      bithas​_lock(uvm_sequence_base sequence_ptr)
      voidlock(uvm_sequence_base sequence_ptr)
      voidgrab(uvm_sequence_base sequence_ptr)
      voidunlock(uvm_sequence_base sequence_ptr)
      voidungrab(uvm_sequence_base sequence_ptr)
      voidstop​_sequences()
      bitis​_grabbed()
      uvm_sequence_basecurrent​_grabber()
      bithas​_do​_available()
      voidset​_arbitration(UVM_SEQ_ARB_TYPE val)
      UVM_SEQ_ARB_TYPEget​_arbitration()
      voidwait​_for​_sequences()
      voidsend​_request(uvm_sequence_base sequence_ptr, uvm_sequence_item t, bit rerandomize)
      voidset​_max​_zero​_time​_wait​_relevant​_count(int new_val)
      voidgrant​_queued​_locks()
      voidm​_select​_sequence()
      intm​_choose​_next​_request()
      voidm​_wait​_for​_arbitration​_completed(int request_id)
      voidm​_set​_arbitration​_completed(int request_id)
      voidm​_lock​_req(uvm_sequence_base sequence_ptr, bit lock)
      voidm​_unlock​_req(uvm_sequence_base sequence_ptr)
      voidremove​_sequence​_from​_queues(uvm_sequence_base sequence_ptr)
      voidm​_sequence​_exiting(uvm_sequence_base sequence_ptr)
      voidkill​_sequence(uvm_sequence_base sequence_ptr)
      voidanalysis​_write(uvm_sequence_item t)
      intm​_register​_sequence(uvm_sequence_base sequence_ptr)
      voidm​_unregister​_sequence(int sequence_id)
      uvm_sequence_basem​_find​_sequence(int sequence_id)
      voidm​_update​_lists()
      voidm​_wait​_arb​_not​_equal()
      voidm​_wait​_for​_available​_sequence()
      intm​_get​_seq​_item​_priority(uvm_sequence_request seq_q_entry)
      voiddisable​_auto​_item​_recording()
      bitis​_auto​_item​_recording​_enabled()
      voidadd​_sequence(string type_name)
      voidremove​_sequence(string type_name)
      voidset​_sequences​_queue(string[] sequencer_sequence_lib)
      voidstart​_default​_sequence()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      intnum​_sequences()
      voidm​_add​_builtin​_seqs(bit add_simple)
      REQget​_current​_item()

      Function: get_current_item

      Returns the request_item currently being executed by the sequencer. If the sequencer is not currently executing an item, this method will return ~null~.

      The sequencer is executing an item from the time that get_next_item or peek is called until the time that get or item_done is called.

      Note that a driver that only calls get() will never show a current item, since the item is completed at the same time as it is requested.

      intget​_num​_reqs​_sent()
      voidset​_num​_last​_reqs(int max)
      intget​_num​_last​_reqs()
      REQlast​_req(int n)

      Function: last_req

      Returns the last request item by default. If n is not 0, then it will get the n�th before last request item. If n is greater than the last request buffer size, the function will return ~null~.

      intget​_num​_rsps​_received()
      voidset​_num​_last​_rsps(int max)
      intget​_num​_last​_rsps()
      RSPlast​_rsp(int n)

      Function: last_rsp

      Returns the last response item by default. If n is not 0, then it will get the nth-before-last response item. If n is greater than the last response buffer size, the function will return ~null~.

      voidm​_last​_rsp​_push​_front(RSP item)
      voidput​_response(RSP t)
      voidm​_last​_req​_push​_front(REQ item)

    Class uvm​_sequence​_base

    • Extends: uvm​_sequence​_item

    • Fields Summary
      TypeNameDescription
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      anonymousm​_sequence​_process
      bitm​_use​_response​_handler
      stringtype​_name
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new

      The constructor for uvm_sequence_base.

      bitis​_item()
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      integerget​_tr​_handle()
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidbody()
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)

    Virtual class uvm​_sequence

    • Extends: uvm​_sequence​_base

    • Fields Summary
      TypeNameDescription
      sequencer_tparam​_sequencer
      REQreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      RSPrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      REQget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voidput​_response(uvm_sequence_item response_item)
      voiddo​_print(uvm_printer printer)

      Function- do_print

    Class uvm​_sequence​_library

      Fields Summary
      TypeNameDescription
      uvm_sequence_lib_modeselection​_mode

      Variable: selection_mode

      Specifies the mode used to select sequences for execution

      If you do not have access to an instance of the library, use the configuration resource interface.

      The following example sets the ~config_seq_lib~ as the default sequence for the 'main' phase on the sequencer to be located at "env.agent.sequencer" and set the selection mode to <UVM_SEQ_LIB_RANDC>. If the settings are being done from within a component, the first argument must be ~this~ and the second argument a path relative to that component.

      | uvm_config_db #(uvm_object_wrapper)::set(null, | "env.agent.sequencer.main_phase", | "default_sequence", | main_seq_lib::get_type()); | | uvm_config_db #(uvm_sequence_lib_mode)::set(null, | "env.agent.sequencer.main_phase", | "default_sequence.selection_mode", | UVM_SEQ_LIB_RANDC);

      Alternatively, you may create an instance of the sequence library a priori, initialize all its parameters, randomize it, then set it to run as-is on the sequencer.

      | main_seq_lib my_seq_lib; | my_seq_lib = new("my_seq_lib"); | | my_seq_lib.selection_mode = UVM_SEQ_LIB_RANDC; | my_seq_lib.min_random_count = 500; | my_seq_lib.max_random_count = 1000; | void'(my_seq_lib.randomize()); | | uvm_config_db #(uvm_sequence_base)::set(null, | "env.agent.sequencer.main_phase", | "default_sequence", | my_seq_lib); |

      intmin​_random​_count

      Variable: min_random_count

      Sets the minimum number of items to execute. Use the configuration mechanism to set. See <selection_mode> for an example.

      intmax​_random​_count

      Variable: max_random_count

      Sets the maximum number of items to execute. Use the configuration mechanism to set. See <selection_mode> for an example.

      intsequences​_executed
      intsequence​_count
      intselect​_rand
      anonymousselect​_randc
      int[]seqs​_distrib
      uvm_object_wrapper[]sequences
      stringtype​_name
      uvm_object_wrapper[]m​_typewide​_sequences
      bitm​_abort
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      REQreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      RSPrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      Method Summary
      TypeMethodDescription
      uvm_sequence_librarynew(string name)
      stringget​_type​_name()
      intselect​_sequence(int max)
      voidadd​_typewide​_sequence(uvm_object_wrapper seq_type)
      voidadd​_typewide​_sequences(uvm_object_wrapper[] seq_types)
      voidadd​_sequence(uvm_object_wrapper seq_type)
      voidadd​_sequences(uvm_object_wrapper[] seq_types)
      voidremove​_sequence(uvm_object_wrapper seq_type)
      voidget​_sequences(uvm_object_wrapper[] seq_types)
      voidinit​_sequence​_library()
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      bitm​_static​_check(uvm_object_wrapper seq_type)
      bitm​_check(uvm_object_wrapper seq_type, this_type lib)
      bitm​_dyn​_check(uvm_object_wrapper seq_type)
      voidm​_get​_config()
      bitm​_add​_typewide​_sequence(uvm_object_wrapper seq_type)
      voidexecute(uvm_object_wrapper wrap)
      voidbody()
      voiddo​_print(uvm_printer printer)
      voidpre​_randomize()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      REQget​_current​_item()
      voidget​_response(RSP response, int transaction_id)

    Class uvm​_sequence​_library​_cfg

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_sequence_lib_modeselection​_mode
      intmin​_random​_count
      intmax​_random​_count
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name, uvm_sequence_lib_mode mode, int min, int max)

    Class uvm​_random​_sequence

      Fields Summary
      TypeNameDescription
      intl​_count
      intl​_exhaustive​_seq​_kind
      intmax​_kind
      intl​_kind
      bitm​_success
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      stringtype​_name
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_sequence_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      Method Summary
      TypeMethodDescription
      intget​_count()
      logicnew(string name)
      voidbody()
      voiddo​_copy(uvm_object rhs)

      Implement data functions

      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_print(uvm_printer printer)
      voiddo​_record(uvm_recorder recorder)

      void

      uvm_objectcreate(string name)
      stringget​_type​_name()
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_sequence_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)

    Class uvm​_exhaustive​_sequence

      Fields Summary
      TypeNameDescription
      intl​_count
      intl​_exhaustive​_seq​_kind
      intmax​_kind
      anonymousl​_kind
      bitm​_success
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      stringtype​_name
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_sequence_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidbody()
      voiddo​_copy(uvm_object rhs)

      Implement data functions

      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_print(uvm_printer printer)
      voiddo​_record(uvm_recorder recorder)

      void

      uvm_objectcreate(string name)
      stringget​_type​_name()
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_sequence_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)

    Class uvm​_simple​_sequence

      Fields Summary
      TypeNameDescription
      uvm_sequence_itemitem
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      stringtype​_name
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_sequence_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      Method Summary
      TypeMethodDescription
      logicnew(string name)

      new

      voidbody()

      body

      uvm_objectcreate(string name)
      stringget​_type​_name()
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_sequence_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)

    Class uvm​_tlm​_time

      Description

      CLASS: uvm_tlm_time Canonical time type that can be used in different timescales

      This time type is used to represent time values in a canonical form that can bridge initiators and targets located in different timescales and time precisions.

      For a detailed explanation of the purpose for this class, see .

      Fields Summary
      TypeNameDescription
      realm​_resolution

      ps by default

      realm​_res
      timem​_time

      Number of 'm_res' time units,

      stringm​_name
      Method Summary
      TypeMethodDescription
      voidset​_time​_resolution(real res)
      logicnew(string name, real res)

      Function: new Create a new canonical time value.

      The new value is initialized to 0. If a resolution is not specified, the default resolution, as specified by <set_time_resolution()>, is used.

      stringget​_name()

      Function: get_name Return the name of this instance

      voidreset()

      Function: reset Reset the value to 0

      realto​_m​_res(real t, time scaled, real secs)
      realget​_realtime(time scaled, real secs)

      Function: get_realtime Return the current canonical time value, scaled for the caller's timescale

      ~scaled~ must be a time literal value that corresponds to the number of seconds specified in ~secs~ (1ns by default). It must be a time literal value that is greater or equal to the current timescale.

      | #(delay.get_realtime(1ns)); | #(delay.get_realtime(1fs, 1.0e-15));

      voidincr(real t, time scaled, real secs)

      Function: incr Increment the time value by the specified number of scaled time unit

      ~t~ is a time value expressed in the scale and precision of the caller. ~scaled~ must be a time literal value that corresponds to the number of seconds specified in ~secs~ (1ns by default). It must be a time literal value that is greater or equal to the current timescale.

      | delay.incr(1.5ns, 1ns); | delay.incr(1.5ns, 1ps, 1.0e-12);

      voiddecr(real t, time scaled, real secs)

      Function: decr Decrement the time value by the specified number of scaled time unit

      ~t~ is a time value expressed in the scale and precision of the caller. ~scaled~ must be a time literal value that corresponds to the number of seconds specified in ~secs~ (1ns by default). It must be a time literal value that is greater or equal to the current timescale.

      | delay.decr(200ps, 1ns);

      realget​_abstime(real secs)

      Function: get_abstime Return the current canonical time value, in the number of specified time unit, regardless of the current timescale of the caller.

      ~secs~ is the number of seconds in the desired time unit e.g. 1e-9 for nanoseconds.

      | $write("%.3f ps\n", delay.get_abstime(1e-12));

      voidset​_abstime(real t, real secs)

      Function: set_abstime Set the current canonical time value, to the number of specified time unit, regardless of the current timescale of the caller.

      ~secs~ is the number of seconds in the time unit in the value ~t~ e.g. 1e-9 for nanoseconds.

      | delay.set_abstime(1.5, 1e-12));

    Class uvm​_tlm​_generic​_payload

    • Extends: uvm​_sequence​_item

    • Fields Summary
      TypeNameDescription
      anonymousm​_address
      uvm_tlm_command_em​_command
      anonymousm​_data
      intm​_length
      uvm_tlm_response_status_em​_response​_status
      bitm​_dmi

      Variable: m_dmi

      DMI mode is not yet supported in the UVM TLM2 subset. This variable is provided for completeness and interoperability with SystemC.

      anonymousm​_byte​_enable
      intm​_byte​_enable​_length
      intm​_streaming​_width
      uvm_tlm_extension_base[]m​_extensions
      anonymousm​_rand​_exts
      stringtype​_name
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      voiddo​_copy(uvm_object rhs)

      Function- do_copy

      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)

      Function- do_compare

      voiddo​_pack(uvm_packer packer)

      Function- do_pack

      We only pack m_length bytes of the m_data array, even if m_data is larger than m_length. Same treatment for the byte-enable array. We do not pack the extensions, if any, as we will be unable to unpack them.

      voiddo​_unpack(uvm_packer packer)

      Function- do_unpack

      We only reallocate m_data/m_byte_enable if the new size is greater than their current size. We do not unpack extensions because we do not know what object types to allocate before we unpack into them. Extensions must be handled by user code.

      voiddo​_record(uvm_recorder recorder)

      Function- do_record

      stringconvert2string()

      Function- convert2string

      uvm_tlm_command_eget​_command()
      voidset​_command(uvm_tlm_command_e command)
      bitis​_read()
      voidset​_read()
      bitis​_write()
      voidset​_write()
      voidset​_address(anonymous addr)
      bit[]get​_address()
      voidget​_data(byte[] p)
      voidset​_data(byte[] p)
      intget​_data​_length()
      voidset​_data​_length(int length)
      intget​_streaming​_width()
      voidset​_streaming​_width(int width)
      voidget​_byte​_enable(byte[] p)
      voidset​_byte​_enable(byte[] p)
      intget​_byte​_enable​_length()
      voidset​_byte​_enable​_length(int length)
      voidset​_dmi​_allowed(bit dmi)
      bitis​_dmi​_allowed()
      uvm_tlm_response_status_eget​_response​_status()
      voidset​_response​_status(uvm_tlm_response_status_e status)
      bitis​_response​_ok()
      bitis​_response​_error()
      stringget​_response​_string()
      uvm_tlm_extension_baseset​_extension(uvm_tlm_extension_base ext)
      intget​_num​_extensions()
      uvm_tlm_extension_baseget​_extension(uvm_tlm_extension_base ext_handle)
      voidclear​_extension(uvm_tlm_extension_base ext_handle)
      voidclear​_extensions()
      voidpre​_randomize()

      Function: pre_randomize() Prepare this class instance for randomization

      voidpost​_randomize()

      Function: post_randomize() Clean-up this class instance after randomization

    Virtual class uvm​_tlm​_extension​_base

    • Extends: uvm​_object

    • Description

      Class: uvm_tlm_extension_base

      The class uvm_tlm_extension_base is the non-parameterized base class for all generic payload extensions. It includes the utility do_copy() and create(). The pure virtual function get_type_handle() allows you to get a unique handle that represents the derived type. This is implemented in derived classes.

      This class is never used directly by users. The <uvm_tlm_extension> class is used instead.

      Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new

      uvm_tlm_extension_baseget​_type​_handle()
      stringget​_type​_handle​_name()
      voiddo​_copy(uvm_object rhs)
      uvm_objectcreate(string name)

    Class uvm​_tlm​_extension

    • Extends: uvm​_tlm​_extension​_base

    • Fields Summary
      TypeNameDescription
      this_typem​_my​_tlm​_ext​_type
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      this_typeID()
      uvm_tlm_extension_baseget​_type​_handle()
      stringget​_type​_handle​_name()
      uvm_objectcreate(string name)

    Class uvm​_tlm​_if

      Method Summary
      TypeMethodDescription
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)

    Class uvm​_tlm​_b​_transport​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      voidb​_transport(T t, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_transport​_fw​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_transport​_bw​_imp

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, IMP imp)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_b​_transport​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidb​_transport(T t, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_transport​_fw​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_transport​_bw​_port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_b​_transport​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidb​_transport(T t, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_transport​_fw​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_transport​_bw​_export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_b​_target​_socket​_base

      Description

      Class: uvm_tlm_b_target_socket_base

      IS-A forward imp; has no backward path except via the payload contents.

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_b​_initiator​_socket​_base

      Description

      Class: uvm_tlm_b_initiator_socket_base

      IS-A forward port; has no backward path except via the payload contents

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidb​_transport(T t, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_target​_socket​_base

      Description

      Class: uvm_tlm_nb_target_socket_base

      IS-A forward imp; HAS-A backward port

      Fields Summary
      TypeNameDescription
      uvm_tlm_nb_transport_bw_portbw​_port
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_initiator​_socket​_base

      Description

      Class: uvm_tlm_nb_initiator_socket_base

      IS-A forward port; HAS-A backward imp

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_passthrough​_initiator​_socket​_base

      Description

      Class: uvm_tlm_nb_passthrough_initiator_socket_base

      IS-A forward port; HAS-A backward export

      Fields Summary
      TypeNameDescription
      uvm_tlm_nb_transport_bw_exportbw​_export
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_passthrough​_target​_socket​_base

      Description

      Class: uvm_tlm_nb_passthrough_target_socket_base

      IS-A forward export; HAS-A backward port

      Fields Summary
      TypeNameDescription
      uvm_tlm_nb_transport_bw_portbw​_port
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_b​_passthrough​_initiator​_socket​_base

      Description

      Class: uvm_tlm_b_passthrough_initiator_socket_base

      IS-A forward port

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidb​_transport(T t, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_b​_passthrough​_target​_socket​_base

      Description

      Class: uvm_tlm_b_passthrough_target_socket_base

      IS-A forward export

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, int min_size, int max_size)
      stringget​_type​_name()
      voidb​_transport(T t, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voidconnect(this_type provider)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_b​_initiator​_socket

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)

      Function: new Construct a new instance of this socket

      voidconnect(uvm_port_base provider)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      stringget​_type​_name()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_b​_target​_socket

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, IMP imp)

      Function: new Construct a new instance of this socket ~imp~ is a reference to the class implementing the b_transport() method. If not specified, it is assume to be the same as ~parent~.

      voidconnect(uvm_port_base provider)
      voidb​_transport(T t, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      stringget​_type​_name()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_initiator​_socket

      Fields Summary
      TypeNameDescription
      uvm_tlm_nb_transport_bw_impbw​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, IMP imp)

      Function: new Construct a new instance of this socket ~imp~ is a reference to the class implementing the nb_transport_bw() method. If not specified, it is assume to be the same as ~parent~.

      voidconnect(uvm_port_base provider)

      Function: Connect

      Connect this socket to the specified <uvm_tlm_nb_target_socket>

      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      stringget​_type​_name()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_target​_socket

      Fields Summary
      TypeNameDescription
      IMPm​_imp
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      uvm_tlm_nb_transport_bw_portbw​_port
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent, IMP imp)

      Function: new Construct a new instance of this socket ~imp~ is a reference to the class implementing the nb_transport_fw() method. If not specified, it is assume to be the same as ~parent~.

      voidconnect(uvm_port_base provider)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      stringget​_type​_name()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_b​_passthrough​_initiator​_socket

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidconnect(uvm_port_base provider)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      stringget​_type​_name()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_b​_passthrough​_target​_socket

      Description

      Class: uvm_tlm_b_passthrough_target_socket

      IS-A forward export;

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidconnect(uvm_port_base provider)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      stringget​_type​_name()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_passthrough​_initiator​_socket

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      uvm_tlm_nb_transport_bw_exportbw​_export
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidconnect(uvm_port_base provider)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      stringget​_type​_name()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_tlm​_nb​_passthrough​_target​_socket

      Fields Summary
      TypeNameDescription
      intm​_if​_mask
      uvm_port_basem​_if

      REMOVE

      intm​_def​_index
      uvm_port_componentm​_comp
      this_type[]m​_provided​_by
      this_type[]m​_provided​_to
      uvm_port_type_em​_port​_type
      intm​_min​_size
      intm​_max​_size
      bitm​_resolved
      this_type[]m​_imp​_list
      uvm_tlm_nb_transport_bw_portbw​_port
      Method Summary
      TypeMethodDescription
      logicnew(string name, uvm_component parent)
      voidconnect(uvm_port_base provider)
      uvm_tlm_sync_enb​_transport​_fw(T t, P p, uvm_tlm_time delay)
      uvm_tlm_sync_enb​_transport​_bw(T t, P p, uvm_tlm_time delay)
      voidb​_transport(T t, uvm_tlm_time delay)
      stringget​_name()
      stringget​_full​_name()
      uvm_componentget​_parent()
      uvm_port_component_baseget​_comp()
      stringget​_type​_name()
      intmax​_size()
      intmin​_size()
      bitis​_unbounded()
      bitis​_port()
      bitis​_export()
      bitis​_imp()
      intsize()
      voidset​_if(int index)
      intm​_get​_if​_mask()
      voidset​_default​_index(int index)
      voiddebug​_connected​_to(int level, int max_level)
      voiddebug​_provided​_to(int level, int max_level)
      voidget​_connected​_to(uvm_port_list list)
      voidget​_provided​_to(uvm_port_list list)
      bitm​_check​_relationship(this_type provider)
      voidm​_add​_list(this_type provider)
      voidresolve​_bindings()
      uvm_port_baseget​_if(int index)

    Class uvm​_hdl​_path​_concat

      Fields Summary
      TypeNameDescription
      uvm_hdl_path_slice[]slices

      Variable: slices Array of individual slices, stored in most-to-least significant order

      Method Summary
      TypeMethodDescription
      voidset(uvm_hdl_path_slice[] t)

      Function: set Initialize the concatenation using an array literal

      voidadd​_slice(uvm_hdl_path_slice slice)

      Function: add_slice Append the specified ~slice~ literal to the path concatenation

      voidadd​_path(string path, int offset, int size)

      Function: add_path Append the specified ~path~ to the path concatenation, for the specified number of bits at the specified ~offset~.

    Class uvm​_reg​_item

    • Extends: uvm​_sequence​_item

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_elem_kind_eelement​_kind

      Variable: element_kind

      Kind of element being accessed: REG, MEM, or FIELD. See <uvm_elem_kind_e>.

      uvm_objectelement

      Variable: element

      A handle to the RegModel model element associated with this transaction. Use <element_kind> to determine the type to cast to: <uvm_reg>, <uvm_mem>, or <uvm_reg_field>.

      uvm_access_ekind
      anonymousvalue
      uvm_reg_addr_toffset
      uvm_status_estatus

      Variable: status

      The result of the transaction: IS_OK, HAS_X, or ERROR. See <uvm_status_e>.

      uvm_reg_maplocal​_map

      Variable: local_map

      The local map used to obtain addresses. Users may customize address-translation using this map. Access to the sequencer and bus adapter can be obtained by getting this map's root map, then calling <uvm_reg_map::get_sequencer> and <uvm_reg_map::get_adapter>.

      uvm_reg_mapmap

      Variable: map

      The original map specified for the operation. The actual used may differ when a test or sequence written at the block level is reused at the system level.

      uvm_path_epath

      Variable: path

      The path being used: <UVM_FRONTDOOR> or <UVM_BACKDOOR>.

      uvm_sequence_baseparent
      intprior

      Variable: prior

      The priority requested of this transfer, as defined by <uvm_sequence_base::start_item>.

      uvm_objectextension
      stringbd​_kind

      Variable: bd_kind

      If path is UVM_BACKDOOR, this member specifies the abstraction kind for the backdoor access, e.g. "RTL" or "GATES".

      stringfname

      Variable: fname

      The file name from where this transaction originated, if provided at the call site.

      intlineno

      Variable: lineno

      The file name from where this transaction originated, if provided at the call site.

      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new

      Create a new instance of this type, giving it the optional ~name~.

      stringconvert2string()
      voiddo​_copy(uvm_object rhs)

    Virtual class uvm​_reg​_adapter

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      bitsupports​_byte​_enable
      bitprovides​_responses
      uvm_sequence_baseparent​_sequence
      uvm_reg_itemm​_item
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      uvm_sequence_itemreg2bus(uvm_reg_bus_op rw)
      voidbus2reg(uvm_sequence_item bus_item, uvm_reg_bus_op rw)
      uvm_reg_itemget​_item()
      voidm​_set​_item(uvm_reg_item item)

    Class uvm​_reg​_tlm​_adapter

    • Extends: uvm​_reg​_adapter

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      uvm_sequence_itemreg2bus(uvm_reg_bus_op rw)
      voidbus2reg(uvm_sequence_item bus_item, uvm_reg_bus_op rw)

    Class uvm​_predict​_s

      Fields Summary
      TypeNameDescription
      bit[]addr
      uvm_reg_itemreg​_item

    Class uvm​_reg​_predictor

    • Extends: uvm​_component

    • Fields Summary
      TypeNameDescription
      uvm_analysis_impbus​_in

      Variable: bus_in

      Observed bus transactions of type ~BUSTYPE~ are received from this port and processed.

      For each incoming transaction, the predictor will attempt to get the register or memory handle corresponding to the observed bus address.

      If there is a match, the predictor calls the register or memory's predict method, passing in the observed bus data. The register or memory mirror will be updated with this data, subject to its configured access behavior--RW, RO, WO, etc. The predictor will also convert the bus transaction to a generic <uvm_reg_item> and send it out the ~reg_ap~ analysis port.

      If the register is wider than the bus, the predictor will collect the multiple bus transactions needed to determine the value being read or written.

      uvm_analysis_portreg​_ap

      Variable: reg_ap

      Analysis output port that publishes <uvm_reg_item> transactions converted from bus transactions received on ~bus_in~.

      uvm_reg_mapmap

      Variable: map

      The map used to convert a bus address to the corresponding register or memory handle. Must be configured before the run phase.

      uvm_reg_adapteradapter

      Variable: adapter

      The adapter used to convey the parameters of a bus operation in terms of a canonical <uvm_reg_bus_op> datum. The <uvm_reg_adapter> must be configured before the run phase.

      stringtype​_name
      uvm_predict_s[]m​_pending
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      logicnew(string name, uvm_component parent)

      Function: new

      Create a new instance of this type, giving it the optional ~name~ and ~parent~.

      stringget​_type​_name()
      voidpre​_predict(uvm_reg_item rw)
      voidwrite(BUSTYPE tr)
      voidcheck​_phase(uvm_phase phase)

    Class uvm​_reg​_sequence

      Fields Summary
      TypeNameDescription
      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      stringtype​_name
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)

      Function: new

      Create a new instance, giving it the optional ~name~.

      voidbody()
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidput​_response(uvm_sequence_item response_item)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      stringget​_type​_name()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)

    Virtual class uvm​_reg​_frontdoor

      Description

      Class: uvm_reg_frontdoor

      Facade class for register and memory frontdoor access.

      User-defined frontdoor access sequence

      Base class for user-defined access to register and memory reads and writes through a physical interface.

      By default, different registers and memories are mapped to different addresses in the address space and are accessed via those exclusively through physical addresses.

      The frontdoor allows access using a non-linear and/or non-mapped mechanism. Users can extend this class to provide the physical access to these registers.

      Fields Summary
      TypeNameDescription
      uvm_reg_itemrw​_info

      Variable: rw_info

      Holds information about the register being read or written

      uvm_sequencer_basesequencer

      Variable: sequencer

      Sequencer executing the operation

      stringfname
      intlineno
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      stringtype​_name
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new

      Constructor, new object given optional ~name~.

      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_object_registryget​_type()
      uvm_object_wrapperget​_object​_type()
      stringget​_type​_name()
      uvm_objectcreate(string name)
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidbody()
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Virtual class uvm​_reg​_cbs

    • Extends: uvm​_callback

    • Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidpre​_write(uvm_reg_item rw)
      voidpost​_write(uvm_reg_item rw)
      voidpre​_read(uvm_reg_item rw)
      voidpost​_read(uvm_reg_item rw)
      voidpost​_predict(uvm_reg_field fld, uvm_reg_data_t previous, uvm_reg_data_t value, uvm_predict_e kind, uvm_path_e path, uvm_reg_map map)
      voidencode(uvm_reg_data_t[] data)
      voiddecode(uvm_reg_data_t[] data)

    Class uvm​_reg​_read​_only​_cbs

    • Extends: uvm​_reg​_cbs

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_reg_read_only_cbsm​_me
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      voidpre​_write(uvm_reg_item rw)
      uvm_reg_read_only_cbsget()
      voidadd(uvm_reg rg)
      voidremove(uvm_reg rg)

    Class uvm​_reg​_write​_only​_cbs

    • Extends: uvm​_reg​_cbs

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_reg_write_only_cbsm​_me
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      voidpre​_read(uvm_reg_item rw)
      uvm_reg_write_only_cbsget()
      voidadd(uvm_reg rg)
      voidremove(uvm_reg rg)

    Class uvm​_reg​_backdoor

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringfname
      intlineno
      unknown[]m​_update​_thread
      stringtype​_name
      bitm​_register​_cb​_uvm​_reg​_cbs
      Method Summary
      TypeMethodDescription
      logicnew(string name)

      Function: new

      Create an instance of this class

      Create an instance of the user-defined backdoor class for the specified register or memory

      voiddo​_pre​_read(uvm_reg_item rw)
      voiddo​_post​_read(uvm_reg_item rw)
      voiddo​_pre​_write(uvm_reg_item rw)
      voiddo​_post​_write(uvm_reg_item rw)
      voidwrite(uvm_reg_item rw)
      voidread(uvm_reg_item rw)
      voidread​_func(uvm_reg_item rw)
      bitis​_auto​_updated(uvm_reg_field field)
      voidwait​_for​_change(uvm_object element)
      voidstart​_update​_thread(uvm_object element)
      voidkill​_update​_thread(uvm_object element)
      bithas​_update​_threads()
      voidpre​_read(uvm_reg_item rw)
      voidpost​_read(uvm_reg_item rw)
      voidpre​_write(uvm_reg_item rw)
      voidpost​_write(uvm_reg_item rw)
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)

    Class uvm​_reg​_field

    • Extends: uvm​_object

    • Description

      CLASS: uvm_reg_field Field abstraction class

      A field represents a set of bits that behave consistently as a single entity.

      A field is contained within a single register, but may have different access policies depending on the address map use the access the register (thus the field).

      Fields Summary
      TypeNameDescription
      uvm_reg_data_tvalue

      Mirrored after randomize()

      uvm_reg_data_tm​_mirrored

      What we think is in the HW

      uvm_reg_data_tm​_desired

      Mirrored after set()

      stringm​_access
      uvm_regm​_parent
      intm​_lsb
      intm​_size
      bitm​_volatile
      uvm_reg_data_t[]m​_reset
      bitm​_written
      bitm​_read​_in​_progress
      bitm​_write​_in​_progress
      stringm​_fname
      intm​_lineno
      intm​_cover​_on
      bitm​_individually​_accessible
      uvm_check_em​_check
      intm​_max​_size
      bit[]m​_policy​_names
      stringtype​_name
      bitm​_predefined
      bitm​_register​_cb​_uvm​_reg​_cbs
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_reg_fieldnew(string name)
      voidconfigure(uvm_reg parent, int size, int lsb_pos, string access, bit volatile, uvm_reg_data_t reset, bit has_reset, bit is_rand, bit individually_accessible)
      stringget​_full​_name()
      uvm_regget​_parent()
      uvm_regget​_register()
      intget​_lsb​_pos()
      intget​_n​_bits()
      intget​_max​_size()
      stringset​_access(string mode)
      bitdefine​_access(string name)
      bitm​_predefine​_policies()
      stringget​_access(uvm_reg_map map)
      bitis​_known​_access(uvm_reg_map map)
      voidset​_volatility(bit volatile)
      bitis​_volatile()
      voidset(uvm_reg_data_t value, string fname, int lineno)
      uvm_reg_data_tget(string fname, int lineno)
      uvm_reg_data_tget​_mirrored​_value(string fname, int lineno)
      voidreset(string kind)
      uvm_reg_data_tget​_reset(string kind)
      bithas​_reset(string kind, bit delete)
      voidset​_reset(uvm_reg_data_t value, string kind)
      bitneeds​_update()
      voidwrite(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidread(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidpoke(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidpeek(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidmirror(uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidset​_compare(uvm_check_e check)
      uvm_check_eget​_compare()
      bitis​_indv​_accessible(uvm_path_e path, uvm_reg_map local_map)
      bitpredict(uvm_reg_data_t value, uvm_reg_byte_en_t be, uvm_predict_e kind, uvm_path_e path, uvm_reg_map map, string fname, int lineno)
      uvm_reg_data_tXpredictX(uvm_reg_data_t cur_val, uvm_reg_data_t wr_val, uvm_reg_map map)
      uvm_reg_data_tXupdateX()
      bitXcheck​_accessX(uvm_reg_item rw, uvm_reg_map_info map_info, string caller)
      voiddo​_write(uvm_reg_item rw)
      voiddo​_read(uvm_reg_item rw)
      voiddo​_predict(uvm_reg_item rw, uvm_predict_e kind, uvm_reg_byte_en_t be)
      voidpre​_randomize()
      voidpost​_randomize()
      voidpre​_write(uvm_reg_item rw)
      voidpost​_write(uvm_reg_item rw)
      voidpre​_read(uvm_reg_item rw)
      voidpost​_read(uvm_reg_item rw)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      uvm_objectclone()
      voiddo​_copy(uvm_object rhs)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_pack(uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)

    Class uvm​_vreg​_field

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      bitm​_register​_cb​_uvm​_vreg​_field​_cbs
      uvm_vregparent
      intlsb
      intsize
      stringfname
      intlineno
      bitread​_in​_progress
      bitwrite​_in​_progress
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      uvm_vreg_fieldnew(string name)
      voidconfigure(uvm_vreg parent, int size, int lsb_pos)
      stringget​_full​_name()
      uvm_vregget​_parent()
      uvm_vregget​_register()
      intget​_lsb​_pos​_in​_register()
      intget​_n​_bits()
      stringget​_access(uvm_reg_map map)
      voidwrite(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidread(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidpoke(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidpeek(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidpre​_write(longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map)
      voidpost​_write(longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status)
      voidpre​_read(longint idx, uvm_path_e path, uvm_reg_map map)
      voidpost​_read(longint idx, uvm_reg_data_t rdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      uvm_objectclone()
      voiddo​_copy(uvm_object rhs)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_pack(uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)

    Class uvm​_vreg​_field​_cbs

    • Extends: uvm​_callback

    • Fields Summary
      TypeNameDescription
      stringfname
      intlineno
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidpre​_write(uvm_vreg_field field, longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map)
      voidpost​_write(uvm_vreg_field field, longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status)
      voidpre​_read(uvm_vreg_field field, longint idx, uvm_path_e path, uvm_reg_map map)
      voidpost​_read(uvm_vreg_field field, longint idx, uvm_reg_data_t rdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status)

    Virtual class uvm​_reg

    • Extends: uvm​_object

    • Description

      CLASS: uvm_reg Register abstraction base class

      A register represents a set of fields that are accessible as a single entity.

      A register may be mapped to one or more address maps, each with different access rights and policy.

      Fields Summary
      TypeNameDescription
      bitm​_locked
      uvm_reg_blockm​_parent
      uvm_reg_filem​_regfile​_parent
      intm​_n​_bits
      intm​_n​_used​_bits
      bit[]m​_maps
      uvm_reg_field[]m​_fields

      Fields in LSB to MSB order

      intm​_has​_cover
      intm​_cover​_on
      anonymousm​_atomic
      anonymousm​_process
      stringm​_fname
      intm​_lineno
      bitm​_read​_in​_progress
      bitm​_write​_in​_progress
      bitm​_update​_in​_progress
      bitm​_is​_busy
      bitm​_is​_locked​_by​_field
      uvm_reg_backdoorm​_backdoor
      intm​_max​_size
      uvm_object_string_poolm​_hdl​_paths​_pool
      bitm​_register​_cb​_uvm​_reg​_cbs
      Method Summary
      TypeMethodDescription
      uvm_regnew(string name, int n_bits, int has_coverage)
      voidconfigure(uvm_reg_block blk_parent, uvm_reg_file regfile_parent, string hdl_path)
      voidset​_offset(uvm_reg_map map, uvm_reg_addr_t offset, bit unmapped)
      voidset​_parent(uvm_reg_block blk_parent, uvm_reg_file regfile_parent)
      voidadd​_field(uvm_reg_field field)
      voidadd​_map(uvm_reg_map map)
      voidXlock​_modelX()
      stringget​_full​_name()
      uvm_reg_blockget​_parent()
      uvm_reg_blockget​_block()
      uvm_reg_fileget​_regfile()
      intget​_n​_maps()
      bitis​_in​_map(uvm_reg_map map)
      voidget​_maps(uvm_reg_map[] maps)
      uvm_reg_mapget​_local​_map(uvm_reg_map map, string caller)
      uvm_reg_mapget​_default​_map(string caller)
      stringget​_rights(uvm_reg_map map)
      intget​_n​_bits()
      intget​_n​_bytes()
      intget​_max​_size()
      voidget​_fields(uvm_reg_field[] fields)
      uvm_reg_fieldget​_field​_by​_name(string name)
      stringXget​_fields​_accessX(uvm_reg_map map)
      uvm_reg_addr_tget​_offset(uvm_reg_map map)
      uvm_reg_addr_tget​_address(uvm_reg_map map)
      intget​_addresses(uvm_reg_map map, uvm_reg_addr_t[] addr)
      voidset(uvm_reg_data_t value, string fname, int lineno)
      uvm_reg_data_tget(string fname, int lineno)
      uvm_reg_data_tget​_mirrored​_value(string fname, int lineno)
      bitneeds​_update()
      voidreset(string kind)
      uvm_reg_data_tget​_reset(string kind)
      bithas​_reset(string kind, bit delete)
      voidset​_reset(uvm_reg_data_t value, string kind)
      voidwrite(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidread(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidpoke(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidpeek(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidupdate(uvm_status_e status, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidmirror(uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      bitpredict(uvm_reg_data_t value, uvm_reg_byte_en_t be, uvm_predict_e kind, uvm_path_e path, uvm_reg_map map, string fname, int lineno)
      bitis​_busy()
      voidXset​_busyX(bit busy)
      voidXreadX(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidXatomicX(bit on)
      bitXcheck​_accessX(uvm_reg_item rw, uvm_reg_map_info map_info, string caller)
      bitXis​_locked​_by​_fieldX()
      bitdo​_check(uvm_reg_data_t expected, uvm_reg_data_t actual, uvm_reg_map map)
      voiddo​_write(uvm_reg_item rw)
      voiddo​_read(uvm_reg_item rw)
      voiddo​_predict(uvm_reg_item rw, uvm_predict_e kind, uvm_reg_byte_en_t be)
      voidset​_frontdoor(uvm_reg_frontdoor ftdr, uvm_reg_map map, string fname, int lineno)
      uvm_reg_frontdoorget​_frontdoor(uvm_reg_map map)
      voidset​_backdoor(uvm_reg_backdoor bkdr, string fname, int lineno)
      uvm_reg_backdoorget​_backdoor(bit inherited)
      voidclear​_hdl​_path(string kind)
      voidadd​_hdl​_path(uvm_hdl_path_slice[] slices, string kind)
      voidadd​_hdl​_path​_slice(string name, int offset, int size, bit first, string kind)
      bithas​_hdl​_path(string kind)
      voidget​_hdl​_path(uvm_hdl_path_concat[] paths, string kind)
      voidget​_hdl​_path​_kinds(string[] kinds)
      voidget​_full​_hdl​_path(uvm_hdl_path_concat[] paths, string kind, string separator)
      voidbackdoor​_read(uvm_reg_item rw)
      voidbackdoor​_write(uvm_reg_item rw)
      uvm_status_ebackdoor​_read​_func(uvm_reg_item rw)
      voidbackdoor​_watch()
      voidinclude​_coverage(string scope, uvm_reg_cvr_t models, uvm_object accessor)
      uvm_reg_cvr_tbuild​_coverage(uvm_reg_cvr_t models)
      voidadd​_coverage(uvm_reg_cvr_t models)
      bithas​_coverage(uvm_reg_cvr_t models)
      uvm_reg_cvr_tset​_coverage(uvm_reg_cvr_t is_on)
      bitget​_coverage(uvm_reg_cvr_t is_on)
      voidsample(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map)
      voidsample​_values()
      voidXsampleX(uvm_reg_data_t data, uvm_reg_data_t byte_en, bit is_read, uvm_reg_map map)
      voidpre​_write(uvm_reg_item rw)
      voidpost​_write(uvm_reg_item rw)
      voidpre​_read(uvm_reg_item rw)
      voidpost​_read(uvm_reg_item rw)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      uvm_objectclone()
      voiddo​_copy(uvm_object rhs)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_pack(uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)

    Class uvm​_reg​_indirect​_data

    • Extends: uvm​_reg

    • Fields Summary
      TypeNameDescription
      uvm_regm​_idx
      uvm_reg[]m​_tbl
      Method Summary
      TypeMethodDescription
      logicnew(string name, int n_bits, int has_cover)

      Function: new Create an instance of this class

      Should not be called directly, other than via super.new(). The value of ~n_bits~ must match the number of bits in the indirect register array.

      voidbuild()
      voidconfigure(uvm_reg idx, uvm_reg[] reg_a, uvm_reg_block blk_parent, uvm_reg_file regfile_parent)

      Function: configure Configure the indirect data register.

      The ~idx~ register specifies the index, in the ~reg_a~ register array, of the register to access. The ~idx~ must be written to first. A read or write operation to this register will subsequently read or write the indexed register in the register array.

      The number of bits in each register in the register array must be equal to ~n_bits~ of this register.

      See <uvm_reg::configure()> for the remaining arguments.

      voidadd​_map(uvm_reg_map map)
      voidadd​_frontdoors(uvm_reg_map map)
      voiddo​_predict(uvm_reg_item rw, uvm_predict_e kind, uvm_reg_byte_en_t be)
      uvm_reg_mapget​_local​_map(uvm_reg_map map, string caller)
      voidadd​_field(uvm_reg_field field)
      voidset(uvm_reg_data_t value, string fname, int lineno)
      uvm_reg_data_tget(string fname, int lineno)
      uvm_regget​_indirect​_reg(string fname, int lineno)
      bitneeds​_update()
      voidwrite(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidread(uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidpoke(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidpeek(uvm_status_e status, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidupdate(uvm_status_e status, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidmirror(uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)

    Class uvm​_reg​_indirect​_ftdr​_seq

    • Extends: uvm​_reg​_frontdoor

    • Fields Summary
      TypeNameDescription
      uvm_regm​_addr​_reg
      uvm_regm​_data​_reg
      intm​_idx
      Method Summary
      TypeMethodDescription
      logicnew(uvm_reg addr_reg, int idx, uvm_reg data_reg)
      voidbody()

    Class uvm​_reg​_fifo

    • Extends: uvm​_reg

    • Fields Summary
      TypeNameDescription
      uvm_reg_fieldvalue
      intm​_set​_cnt
      intm​_size
      anonymousfifo
      Method Summary
      TypeMethodDescription
      logicnew(string name, int size, int n_bits, int has_cover)

      Function: new

      Creates an instance of a FIFO register having ~size~ elements of ~n_bits~ each.

      voidbuild()
      voidset​_compare(uvm_check_e check)

      Function: set_compare

      Sets the compare policy during a mirror (read) of the DUT FIFO. The DUT read value is checked against its mirror only when both the ~check~ argument in the <mirror()> call and the compare policy for the field is <UVM_CHECK>.

      intsize()

      Function: size

      The number of entries currently in the FIFO.

      intcapacity()
      voidset(uvm_reg_data_t value, string fname, int lineno)
      voidupdate(uvm_status_e status, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      uvm_reg_data_tget(string fname, int lineno)
      voiddo​_predict(uvm_reg_item rw, uvm_predict_e kind, uvm_reg_byte_en_t be)
      voidpre​_write(uvm_reg_item rw)
      voidpre​_read(uvm_reg_item rw)
      voidpost​_randomize()

    Virtual class uvm​_reg​_file

    • Extends: uvm​_object

    • Description

      CLASS: uvm_reg_file Register file abstraction base class

      A register file is a collection of register files and registers used to create regular repeated structures.

      Register files are usually instantiated as arrays.

      Fields Summary
      TypeNameDescription
      uvm_reg_blockparent
      uvm_reg_filem​_rf
      stringdefault​_hdl​_path
      uvm_object_string_poolhdl​_paths​_pool
      Method Summary
      TypeMethodDescription
      uvm_reg_filenew(string name)
      voidconfigure(uvm_reg_block blk_parent, uvm_reg_file regfile_parent, string hdl_path)
      stringget​_full​_name()
      uvm_reg_blockget​_parent()
      uvm_reg_blockget​_block()
      uvm_reg_fileget​_regfile()
      voidclear​_hdl​_path(string kind)
      voidadd​_hdl​_path(string path, string kind)
      bithas​_hdl​_path(string kind)
      voidget​_hdl​_path(string[] paths, string kind)
      voidget​_full​_hdl​_path(string[] paths, string kind, string separator)
      voidset​_default​_hdl​_path(string kind)
      stringget​_default​_hdl​_path()
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      uvm_objectclone()
      voiddo​_copy(uvm_object rhs)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_pack(uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)

    Class uvm​_mem​_mam

      Fields Summary
      TypeNameDescription
      uvm_mem_mam_policydefault​_alloc

      Variable: default_alloc

      Region allocation policy

      This object is repeatedly randomized when allocating new regions.

      uvm_memmemory
      uvm_mem_mam_cfgcfg
      uvm_mem_region[]in​_use
      intfor​_each​_idx
      stringfname
      intlineno
      Method Summary
      TypeMethodDescription
      uvm_mem_mamnew(string name, uvm_mem_mam_cfg cfg, uvm_mem mem)
      uvm_mem_mam_cfgreconfigure(uvm_mem_mam_cfg cfg)
      uvm_mem_regionreserve​_region(anonymous start_offset, int n_bytes, string fname, int lineno)
      uvm_mem_regionrequest​_region(int n_bytes, uvm_mem_mam_policy alloc, string fname, int lineno)
      voidrelease​_region(uvm_mem_region region)
      voidrelease​_all​_regions()
      stringconvert2string()
      uvm_mem_regionfor​_each(bit reset)
      uvm_memget​_memory()

    Class uvm​_mem​_region

      Fields Summary
      TypeNameDescription
      bit[]Xstart​_offsetX

      Can't be local since function

      bit[]Xend​_offsetX

      calls not supported in constraints

      intlen
      intn​_bytes
      uvm_mem_mamparent
      stringfname
      intlineno
      uvm_vregXvregX
      Method Summary
      TypeMethodDescription
      uvm_mem_regionnew(anonymous start_offset, anonymous end_offset, int len, int n_bytes, uvm_mem_mam parent)
      bit[]get​_start​_offset()
      bit[]get​_end​_offset()
      intget​_len()
      intget​_n​_bytes()
      voidrelease​_region()
      uvm_memget​_memory()
      uvm_vregget​_virtual​_registers()
      voidwrite(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidread(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidburst​_write(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t[] value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidburst​_read(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t[] value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidpoke(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidpeek(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      stringconvert2string()

    Class uvm​_mem​_mam​_policy

      Fields Summary
      TypeNameDescription
      intlen

      variable: len Number of addresses required

      anonymousstart​_offset
      bit[]min​_offset

      variable: min_offset Minimum address offset in the managed address space

      bit[]max​_offset

      variable: max_offset Maximum address offset in the managed address space

      uvm_mem_region[]in​_use

      variable: in_use Regions already allocated in the managed address space

    Class uvm​_mem​_mam​_cfg

      Description

      CLASS: uvm_mem_mam_cfg Specifies the memory managed by an instance of a <uvm_mem_mam> memory allocation manager class.

      Fields Summary
      TypeNameDescription
      intn​_bytes
      anonymousstart​_offset
      anonymousend​_offset
      alloc_mode_emode
      locality_elocality

    Class uvm​_vreg

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      bitm​_register​_cb​_uvm​_vreg​_cbs
      bitlocked
      uvm_reg_blockparent
      intn​_bits
      intn​_used​_bits
      uvm_vreg_field[]fields

      Fields in LSB to MSB order

      uvm_memmem

      Where is it implemented?

      uvm_reg_addr_toffset

      Start of vreg0

      intincr

      From start to start of next

      longintsize

      number of vregs

      bitis​_static
      uvm_mem_regionregion

      Not NULL if implemented via MAM

      anonymousatomic

      Field RMW operations must be atomic

      stringfname
      intlineno
      bitread​_in​_progress
      bitwrite​_in​_progress
      Method Summary
      TypeMethodDescription
      uvm_vregnew(string name, int n_bits)
      voidconfigure(uvm_reg_block parent, uvm_mem mem, longint size, uvm_reg_addr_t offset, int incr)
      bitimplement(longint n, uvm_mem mem, uvm_reg_addr_t offset, int incr)
      uvm_mem_regionallocate(longint n, uvm_mem_mam mam, uvm_mem_mam_policy alloc)
      uvm_mem_regionget​_region()
      voidrelease​_region()
      voidset​_parent(uvm_reg_block parent)
      voidXlock​_modelX()
      voidadd​_field(uvm_vreg_field field)
      voidXatomicX(bit on)
      stringget​_full​_name()
      uvm_reg_blockget​_parent()
      uvm_reg_blockget​_block()
      uvm_memget​_memory()
      intget​_n​_maps()
      bitis​_in​_map(uvm_reg_map map)
      voidget​_maps(uvm_reg_map[] maps)
      stringget​_rights(uvm_reg_map map)
      stringget​_access(uvm_reg_map map)
      intget​_size()
      intget​_n​_bytes()
      intget​_n​_memlocs()
      intget​_incr()
      voidget​_fields(uvm_vreg_field[] fields)
      uvm_vreg_fieldget​_field​_by​_name(string name)
      uvm_reg_addr_tget​_offset​_in​_memory(longint idx)
      uvm_reg_addr_tget​_address(longint idx, uvm_reg_map map)
      voidwrite(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidread(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidpoke(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidpeek(longint idx, uvm_status_e status, uvm_reg_data_t value, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidreset(string kind)
      voidpre​_write(longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map)
      voidpost​_write(longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status)
      voidpre​_read(longint idx, uvm_path_e path, uvm_reg_map map)
      voidpost​_read(longint idx, uvm_reg_data_t rdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      uvm_objectclone()
      voiddo​_copy(uvm_object rhs)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_pack(uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)

    Class uvm​_vreg​_cbs

    • Extends: uvm​_callback

    • Fields Summary
      TypeNameDescription
      stringfname
      intlineno
      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidpre​_write(uvm_vreg rg, longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map)
      voidpost​_write(uvm_vreg rg, longint idx, uvm_reg_data_t wdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status)
      voidpre​_read(uvm_vreg rg, longint idx, uvm_path_e path, uvm_reg_map map)
      voidpost​_read(uvm_vreg rg, longint idx, uvm_reg_data_t rdat, uvm_path_e path, uvm_reg_map map, uvm_status_e status)

    Class uvm​_mem

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      bitm​_locked
      bitm​_read​_in​_progress
      bitm​_write​_in​_progress
      stringm​_access
      longintm​_size
      uvm_reg_blockm​_parent
      bit[]m​_maps
      intm​_n​_bits
      uvm_reg_backdoorm​_backdoor
      bitm​_is​_powered​_down
      intm​_has​_cover
      intm​_cover​_on
      stringm​_fname
      intm​_lineno
      bit[]m​_vregs
      uvm_object_string_poolm​_hdl​_paths​_pool
      intm​_max​_size
      uvm_mem_mammam

      variable: mam

      Memory allocation manager

      Memory allocation manager for the memory corresponding to this abstraction class instance. Can be used to allocate regions of consecutive addresses of specific sizes, such as DMA buffers, or to locate virtual register array.

      bitm​_register​_cb​_uvm​_reg​_cbs
      Method Summary
      TypeMethodDescription
      uvm_memnew(string name, longint size, int n_bits, string access, int has_coverage)
      voidconfigure(uvm_reg_block parent, string hdl_path)
      voidset​_offset(uvm_reg_map map, uvm_reg_addr_t offset, bit unmapped)
      voidset​_parent(uvm_reg_block parent)
      voidadd​_map(uvm_reg_map map)
      voidXlock​_modelX()
      voidXadd​_vregX(uvm_vreg vreg)
      voidXdelete​_vregX(uvm_vreg vreg)
      stringget​_full​_name()
      uvm_reg_blockget​_parent()
      uvm_reg_blockget​_block()
      intget​_n​_maps()
      bitis​_in​_map(uvm_reg_map map)
      voidget​_maps(uvm_reg_map[] maps)
      uvm_reg_mapget​_local​_map(uvm_reg_map map, string caller)
      uvm_reg_mapget​_default​_map(string caller)
      stringget​_rights(uvm_reg_map map)
      stringget​_access(uvm_reg_map map)
      longintget​_size()
      intget​_n​_bytes()
      intget​_n​_bits()
      intget​_max​_size()
      voidget​_virtual​_registers(uvm_vreg[] regs)
      voidget​_virtual​_fields(uvm_vreg_field[] fields)
      uvm_vregget​_vreg​_by​_name(string name)
      uvm_vreg_fieldget​_vfield​_by​_name(string name)
      uvm_vregget​_vreg​_by​_offset(uvm_reg_addr_t offset, uvm_reg_map map)
      uvm_reg_addr_tget​_offset(uvm_reg_addr_t offset, uvm_reg_map map)
      uvm_reg_addr_tget​_address(uvm_reg_addr_t offset, uvm_reg_map map)
      intget​_addresses(uvm_reg_addr_t offset, uvm_reg_map map, uvm_reg_addr_t[] addr)
      voidwrite(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidread(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidburst​_write(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t[] value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidburst​_read(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t[] value, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidpoke(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      voidpeek(uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_sequence_base parent, uvm_object extension, string fname, int lineno)
      bitXcheck​_accessX(uvm_reg_item rw, uvm_reg_map_info map_info, string caller)
      voiddo​_write(uvm_reg_item rw)
      voiddo​_read(uvm_reg_item rw)
      voidset​_frontdoor(uvm_reg_frontdoor ftdr, uvm_reg_map map, string fname, int lineno)
      uvm_reg_frontdoorget​_frontdoor(uvm_reg_map map)
      voidset​_backdoor(uvm_reg_backdoor bkdr, string fname, int lineno)
      uvm_reg_backdoorget​_backdoor(bit inherited)
      voidclear​_hdl​_path(string kind)
      voidadd​_hdl​_path(uvm_hdl_path_slice[] slices, string kind)
      voidadd​_hdl​_path​_slice(string name, int offset, int size, bit first, string kind)
      bithas​_hdl​_path(string kind)
      voidget​_hdl​_path(uvm_hdl_path_concat[] paths, string kind)
      voidget​_full​_hdl​_path(uvm_hdl_path_concat[] paths, string kind, string separator)
      voidget​_hdl​_path​_kinds(string[] kinds)
      voidbackdoor​_read(uvm_reg_item rw)
      voidbackdoor​_write(uvm_reg_item rw)
      uvm_status_ebackdoor​_read​_func(uvm_reg_item rw)
      voidpre​_write(uvm_reg_item rw)
      voidpost​_write(uvm_reg_item rw)
      voidpre​_read(uvm_reg_item rw)
      voidpost​_read(uvm_reg_item rw)
      uvm_reg_cvr_tbuild​_coverage(uvm_reg_cvr_t models)
      voidadd​_coverage(uvm_reg_cvr_t models)
      bithas​_coverage(uvm_reg_cvr_t models)
      uvm_reg_cvr_tset​_coverage(uvm_reg_cvr_t is_on)
      bitget​_coverage(uvm_reg_cvr_t is_on)
      voidsample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map map)
      voidXsampleX(uvm_reg_addr_t addr, bit is_read, uvm_reg_map map)
      voiddo​_print(uvm_printer printer)
      stringconvert2string()
      uvm_objectclone()
      voiddo​_copy(uvm_object rhs)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_pack(uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)

    Class uvm​_reg​_map​_info

      Fields Summary
      TypeNameDescription
      uvm_reg_addr_toffset
      stringrights
      bitunmapped
      uvm_reg_addr_t[]addr
      uvm_reg_frontdoorfrontdoor
      uvm_reg_map_addr_rangemem​_range
      bitis​_initialized

      if set marks the uvm_reg_map_info as initialized, prevents using an uninitialized map (for instance if the model has not been locked accidently and the maps have not been computed before)

    Virtual class uvm​_reg​_transaction​_order​_policy

    • Extends: uvm​_object

    • Description

      Class: uvm_reg_transaction_order_policy

      Method Summary
      TypeMethodDescription
      logicnew(string name)
      voidorder(uvm_reg_bus_op[] q)

    Class uvm​_reg​_map

    • Extends: uvm​_object

    • Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_reg_addr_tm​_base​_addr
      intm​_n​_bytes
      uvm_endianness_em​_endian
      bitm​_byte​_addressing
      uvm_object_wrapperm​_sequence​_wrapper
      uvm_reg_adapterm​_adapter
      uvm_sequencer_basem​_sequencer
      bitm​_auto​_predict
      bitm​_check​_on​_read
      uvm_reg_blockm​_parent
      intm​_system​_n​_bytes
      uvm_reg_mapm​_parent​_map
      uvm_reg_addr_t[]m​_parent​_maps

      value=offset of this map at parent level

      uvm_reg_addr_t[]m​_submaps

      value=offset of submap at this level

      string[]m​_submap​_rights

      value=rights of submap at this level

      uvm_reg_map_info[]m​_regs​_info
      uvm_reg_map_info[]m​_mems​_info
      uvm_reg[]m​_regs​_by​_offset
      uvm_reg[]m​_regs​_by​_offset​_wo
      uvm_mem[]m​_mems​_by​_offset
      uvm_reg_transaction_order_policypolicy
      uvm_reg_mapm​_backdoor
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      voidXinit​_address​_mapX()
      uvm_reg_mapbackdoor()
      uvm_reg_mapnew(string name)
      voidconfigure(uvm_reg_block parent, uvm_reg_addr_t base_addr, int n_bytes, uvm_endianness_e endian, bit byte_addressing)
      voidadd​_reg(uvm_reg rg, uvm_reg_addr_t offset, string rights, bit unmapped, uvm_reg_frontdoor frontdoor)
      voidadd​_mem(uvm_mem mem, uvm_reg_addr_t offset, string rights, bit unmapped, uvm_reg_frontdoor frontdoor)
      voidadd​_submap(uvm_reg_map child_map, uvm_reg_addr_t offset)
      voidset​_sequencer(uvm_sequencer_base sequencer, uvm_reg_adapter adapter)
      voidset​_submap​_offset(uvm_reg_map submap, uvm_reg_addr_t offset)
      uvm_reg_addr_tget​_submap​_offset(uvm_reg_map submap)
      voidset​_base​_addr(uvm_reg_addr_t offset)
      voidreset(string kind)
      voidadd​_parent​_map(uvm_reg_map parent_map, uvm_reg_addr_t offset)
      voidXverify​_map​_configX()
      voidm​_set​_reg​_offset(uvm_reg rg, uvm_reg_addr_t offset, bit unmapped)
      voidm​_set​_mem​_offset(uvm_mem mem, uvm_reg_addr_t offset, bit unmapped)
      stringget​_full​_name()
      uvm_reg_mapget​_root​_map()
      uvm_reg_blockget​_parent()
      uvm_reg_mapget​_parent​_map()
      uvm_reg_addr_tget​_base​_addr(uvm_hier_e hier)
      intget​_n​_bytes(uvm_hier_e hier)
      intget​_addr​_unit​_bytes()
      uvm_endianness_eget​_endian(uvm_hier_e hier)
      uvm_sequencer_baseget​_sequencer(uvm_hier_e hier)
      uvm_reg_adapterget​_adapter(uvm_hier_e hier)
      voidget​_submaps(uvm_reg_map[] maps, uvm_hier_e hier)
      voidget​_registers(uvm_reg[] regs, uvm_hier_e hier)
      voidget​_fields(uvm_reg_field[] fields, uvm_hier_e hier)
      voidget​_memories(uvm_mem[] mems, uvm_hier_e hier)
      voidget​_virtual​_registers(uvm_vreg[] regs, uvm_hier_e hier)
      voidget​_virtual​_fields(uvm_vreg_field[] fields, uvm_hier_e hier)
      uvm_reg_map_infoget​_reg​_map​_info(uvm_reg rg, bit error)
      uvm_reg_map_infoget​_mem​_map​_info(uvm_mem mem, bit error)
      intget​_size()
      intget​_physical​_addresses(uvm_reg_addr_t base_addr, uvm_reg_addr_t mem_offset, int n_bytes, uvm_reg_addr_t[] addr)
      uvm_regget​_reg​_by​_offset(uvm_reg_addr_t offset, bit read)
      uvm_memget​_mem​_by​_offset(uvm_reg_addr_t offset)
      voidset​_auto​_predict(bit on)

      Function: set_auto_predict

      Sets the auto-predict mode for his map.

      When ~on~ is ~TRUE~, the register model will automatically update its mirror (what it thinks should be in the DUT) immediately after any bus read or write operation via this map. Before a <uvm_reg::write> or <uvm_reg::read> operation returns, the register's <uvm_reg::predict> method is called to update the mirrored value in the register.

      When ~on~ is ~FALSE~, bus reads and writes via this map do not automatically update the mirror. For real-time updates to the mirror in this mode, you connect a <uvm_reg_predictor> instance to the bus monitor. The predictor takes observed bus transactions from the bus monitor, looks up the associated <uvm_reg> register given the address, then calls that register's <uvm_reg::predict> method. While more complex, this mode will capture all register read/write activity, including that not directly descendant from calls to <uvm_reg::write> and <uvm_reg::read>.

      By default, auto-prediction is turned off.

      bitget​_auto​_predict()

      Function: get_auto_predict

      Gets the auto-predict mode setting for this map.

      voidset​_check​_on​_read(bit on)

      Function: set_check_on_read

      Sets the check-on-read mode for his map and all of its submaps.

      When ~on~ is ~TRUE~, the register model will automatically check any value read back from a register or field against the current value in its mirror and report any discrepancy. This effectively combines the functionality of the <uvm_reg::read()> and ~uvm_reg::mirror(UVM_CHECK)~ method. This mode is useful when the register model is used passively.

      When ~on~ is ~FALSE~, no check is made against the mirrored value.

      At the end of the read operation, the mirror value is updated based on the value that was read regardless of this mode setting.

      By default, auto-prediction is turned off.

      bitget​_check​_on​_read()

      Function: get_check_on_read

      Gets the check-on-read mode setting for this map.

      voiddo​_bus​_write(uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter)
      voiddo​_bus​_read(uvm_reg_item rw, uvm_sequencer_base sequencer, uvm_reg_adapter adapter)
      voiddo​_write(uvm_reg_item rw)
      voiddo​_read(uvm_reg_item rw)
      voidXget​_bus​_infoX(uvm_reg_item rw, uvm_reg_map_info map_info, int size, int lsb, int addr_skip)
      stringconvert2string()
      uvm_objectclone()
      voiddo​_print(uvm_printer printer)
      voiddo​_copy(uvm_object rhs)
      voidset​_transaction​_order​_policy(uvm_reg_transaction_order_policy pol)

      Function: set_transaction_order_policy set the transaction order policy

      uvm_reg_transaction_order_policyget​_transaction​_order​_policy()

      Function: get_transaction_order_policy set the transaction order policy

    Virtual class uvm​_reg​_block

    • Extends: uvm​_object

    • Description

      Class: uvm_reg_block

      Block abstraction base class

      A block represents a design hierarchy. It can contain registers, register files, memories and sub-blocks.

      A block has one or more address maps, each corresponding to a physical interface on the block.

      Fields Summary
      TypeNameDescription
      uvm_reg_blockparent
      bit[]m​_roots
      int[]blks
      int[]regs
      int[]vregs
      int[]mems
      bit[]maps
      uvm_path_edefault​_path

      Variable: default_path Default access path for the registers and memories in this block.

      stringdefault​_hdl​_path
      uvm_reg_backdoorbackdoor
      uvm_object_string_poolhdl​_paths​_pool
      string[]root​_hdl​_paths
      bitlocked
      inthas​_cover
      intcover​_on
      stringfname
      intlineno
      intid
      uvm_reg_mapdefault​_map

      Variable: default_map

      Default address map

      Default address map for this block, to be used when no address map is specified for a register operation and that register is accessible from more than one address map.

      It is also the implicit address map for a block with a single, unnamed address map because it has only one physical interface.

      Method Summary
      TypeMethodDescription
      uvm_reg_blocknew(string name, int has_coverage)
      voidconfigure(uvm_reg_block parent, string hdl_path)
      uvm_reg_mapcreate​_map(string name, uvm_reg_addr_t base_addr, int n_bytes, uvm_endianness_e endian, bit byte_addressing)
      bitcheck​_data​_width(int width)
      voidset​_default​_map(uvm_reg_map map)
      uvm_reg_mapget​_default​_map()
      voidset​_parent(uvm_reg_block parent)
      voidadd​_block(uvm_reg_block blk)
      voidadd​_map(uvm_reg_map map)
      voidadd​_reg(uvm_reg rg)
      voidadd​_vreg(uvm_vreg vreg)
      voidadd​_mem(uvm_mem mem)
      voidlock​_model()
      bitis​_locked()
      stringget​_full​_name()
      uvm_reg_blockget​_parent()
      voidget​_root​_blocks(uvm_reg_block[] blks)
      intfind​_blocks(string name, uvm_reg_block[] blks, uvm_reg_block root, uvm_object accessor)
      uvm_reg_blockfind​_block(string name, uvm_reg_block root, uvm_object accessor)
      voidget​_blocks(uvm_reg_block[] blks, uvm_hier_e hier)
      voidget​_maps(uvm_reg_map[] maps)
      voidget​_registers(uvm_reg[] regs, uvm_hier_e hier)
      voidget​_fields(uvm_reg_field[] fields, uvm_hier_e hier)
      voidget​_memories(uvm_mem[] mems, uvm_hier_e hier)
      voidget​_virtual​_registers(uvm_vreg[] regs, uvm_hier_e hier)
      voidget​_virtual​_fields(uvm_vreg_field[] fields, uvm_hier_e hier)
      uvm_reg_blockget​_block​_by​_name(string name)
      uvm_reg_mapget​_map​_by​_name(string name)
      uvm_regget​_reg​_by​_name(string name)
      uvm_reg_fieldget​_field​_by​_name(string name)
      uvm_memget​_mem​_by​_name(string name)
      uvm_vregget​_vreg​_by​_name(string name)
      uvm_vreg_fieldget​_vfield​_by​_name(string name)
      uvm_reg_cvr_tbuild​_coverage(uvm_reg_cvr_t models)
      voidadd​_coverage(uvm_reg_cvr_t models)
      bithas​_coverage(uvm_reg_cvr_t models)
      uvm_reg_cvr_tset​_coverage(uvm_reg_cvr_t is_on)
      bitget​_coverage(uvm_reg_cvr_t is_on)
      voidsample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map map)
      voidsample​_values()
      voidXsampleX(uvm_reg_addr_t addr, bit is_read, uvm_reg_map map)
      uvm_path_eget​_default​_path()
      voidreset(string kind)
      bitneeds​_update()
      voidupdate(uvm_status_e status, uvm_path_e path, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidmirror(uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_reg​_by​_name(uvm_status_e status, string name, uvm_reg_data_t data, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg​_by​_name(uvm_status_e status, string name, uvm_reg_data_t data, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem​_by​_name(uvm_status_e status, string name, uvm_reg_addr_t offset, uvm_reg_data_t data, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem​_by​_name(uvm_status_e status, string name, uvm_reg_addr_t offset, uvm_reg_data_t data, uvm_path_e path, uvm_reg_map map, uvm_sequence_base parent, int prior, uvm_object extension, string fname, int lineno)
      voidreadmemh(string filename)
      voidwritememh(string filename)
      uvm_reg_backdoorget​_backdoor(bit inherited)
      voidset​_backdoor(uvm_reg_backdoor bkdr, string fname, int lineno)
      voidclear​_hdl​_path(string kind)
      voidadd​_hdl​_path(string path, string kind)
      bithas​_hdl​_path(string kind)
      voidget​_hdl​_path(string[] paths, string kind)
      voidget​_full​_hdl​_path(string[] paths, string kind, string separator)
      voidset​_default​_hdl​_path(string kind)
      stringget​_default​_hdl​_path()
      voidset​_hdl​_path​_root(string path, string kind)
      bitis​_hdl​_path​_root(string kind)
      voiddo​_print(uvm_printer printer)
      voiddo​_copy(uvm_object rhs)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      voiddo​_pack(uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      stringconvert2string()
      uvm_objectclone()
      voidXinit​_address​_mapsX()

    Class uvm​_reg​_hw​_reset​_seq

      Fields Summary
      TypeNameDescription
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voiddo​_block(uvm_reg_block blk)
      voidreset​_blk(uvm_reg_block blk)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_reg​_single​_bit​_bash​_seq

      Fields Summary
      TypeNameDescription
      uvm_regrg

      Variable: rg The register to be tested

      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voidbash​_kth​_bit(uvm_reg rg, int k, string mode, uvm_reg_map map, uvm_reg_data_t dc_mask)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_reg​_bit​_bash​_seq

      Fields Summary
      TypeNameDescription
      uvm_reg_single_bit_bash_seqreg​_seq
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voiddo​_block(uvm_reg_block blk)
      voidreset​_blk(uvm_reg_block blk)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_mem​_single​_walk​_seq

      Fields Summary
      TypeNameDescription
      stringtype​_name
      uvm_memmem
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_mem​_walk​_seq

      Fields Summary
      TypeNameDescription
      uvm_mem_single_walk_seqmem​_seq
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voiddo​_block(uvm_reg_block blk)
      voidreset​_blk(uvm_reg_block blk)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_mem​_single​_access​_seq

      Fields Summary
      TypeNameDescription
      uvm_memmem

      Variable: mem

      The memory to be tested

      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_mem​_access​_seq

      Fields Summary
      TypeNameDescription
      uvm_mem_single_access_seqmem​_seq
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voiddo​_block(uvm_reg_block blk)
      voidreset​_blk(uvm_reg_block blk)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_reg​_single​_access​_seq

      Fields Summary
      TypeNameDescription
      uvm_regrg

      Variable: rg The register to be tested

      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_reg​_access​_seq

      Fields Summary
      TypeNameDescription
      uvm_reg_single_access_seqreg​_seq
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voiddo​_block(uvm_reg_block blk)
      voidreset​_blk(uvm_reg_block blk)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_reg​_mem​_access​_seq

      Fields Summary
      TypeNameDescription
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voidreset​_blk(uvm_reg_block blk)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_reg​_shared​_access​_seq

      Fields Summary
      TypeNameDescription
      uvm_regrg

      Variable: rg The register to be tested

      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_mem​_shared​_access​_seq

      Fields Summary
      TypeNameDescription
      uvm_memmem

      variable: mem The memory to be tested

      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_reg​_mem​_shared​_access​_seq

      Fields Summary
      TypeNameDescription
      uvm_reg_shared_access_seqreg​_seq
      uvm_mem_shared_access_seqmem​_seq
      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voiddo​_block(uvm_reg_block blk)
      voidreset​_blk(uvm_reg_block blk)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_reg​_mem​_built​_in​_seq

      Fields Summary
      TypeNameDescription
      stringtype​_name
      bit[]tests

      Variable: tests

      The pre-defined test sequences to be executed.

      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Class uvm​_reg​_mem​_hdl​_paths​_seq

      Fields Summary
      TypeNameDescription
      string[]abstractions

      Variable: abstractions If set, check the HDL paths for the specified design abstractions. If empty, check the HDL path for the default design abstraction, as specified with <uvm_reg_block::set_default_hdl_path()>

      stringtype​_name
      bituse​_uvm​_seeding
      stringm​_leaf​_name
      intm​_inst​_id
      intm​_inst​_count
      uvm_status_container​_​_m​_uvm​_status​_container
      uvm_object[]uvm​_global​_copy​_map
      uvm_event_poolevents
      uvm_eventbegin​_event

      Variable: begin_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus begins, typically as a result of a driver calling <uvm_component::begin_tr>. Processes that wait on this event will block until the transaction has begun.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      uvm_eventend​_event

      Variable: end_event

      A ~uvm_event#(uvm_object)~ that is triggered when this transaction's actual execution on the bus ends, typically as a result of a driver calling <uvm_component::end_tr>. Processes that wait on this event will block until the transaction has ended.

      For more information, see the general discussion for <uvm_transaction>. See <uvm_event#(T)> for details on the event API.

      | virtual task my_sequence::body(); | ... | start_item(item); \ | item.randomize(); } `uvm_do(item) | finish_item(item); / | // return from finish item does not always mean item is completed | item.end_event.wait_on(); | ...

      integerm​_transaction​_id
      timebegin​_time
      timeend​_time
      timeaccept​_time
      uvm_componentinitiator
      uvm_tr_streamstream​_handle
      uvm_recordertr​_recorder
      intm​_sequence​_id
      bitm​_use​_sequence​_info
      intm​_depth
      uvm_sequencer_basem​_sequencer
      uvm_sequence_basem​_parent​_sequence
      bitissued1
      bitissued2
      bitprint​_sequence​_info
      uvm_sequence_statem​_sequence​_state
      intm​_next​_transaction​_id
      intm​_priority
      uvm_recorderm​_tr​_recorder
      intm​_wait​_for​_grant​_semaphore
      int[]m​_sqr​_seq​_ids
      bit[]children​_array
      uvm_sequence_item[]response​_queue
      intresponse​_queue​_depth
      bitresponse​_queue​_error​_report​_disabled
      bitdo​_not​_randomize

      Variable: do_not_randomize

      If set, prevents the sequence from being randomized before being executed by the uvm_do*() and uvm_rand_send*() macros, or as a default sequence.

      unknownm​_sequence​_process
      bitm​_use​_response​_handler
      bitis​_rel​_default
      bitwait​_rel​_default
      uvm_get_to_lock_dapm​_automatic​_phase​_objection​_dap
      uvm_get_to_lock_dapm​_starting​_phase​_dap
      uvm_phasestarting​_phase

      DEPRECATED!! Use get/set_starting_phase accessors instead!

      uvm_phasem​_set​_starting​_phase

      Value set via set_starting_phase

      bitm​_warn​_deprecated​_set

      Ensures we only warn once per sequence

      intseq​_kind
      uvm_sequencer_param_baseparam​_sequencer
      uvm_reg_itemreq

      Variable: req

      The sequence contains a field of the request type called req. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_sequence_itemrsp

      Variable: rsp

      The sequence contains a field of the response type called rsp. The user can use this field, if desired, or create another field to use. The default ~do_print~ will print this field.

      uvm_reg_blockmodel

      Variable: model

      Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

      uvm_reg_adapteradapter

      Variable: adapter

      Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

      uvm_sequencerreg​_seqr

      Variable: reg_seqr

      Layered upstream "register" sequencer.

      Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

      seq_parent_eparent​_select
      uvm_sequence_baseupstream​_parent
      Method Summary
      TypeMethodDescription
      type_idget​_type()
      uvm_object_wrapperget​_object​_type()
      uvm_objectcreate(string name)
      stringget​_type​_name()
      void​_​_m​_uvm​_field​_automation(uvm_object tmp_data__, int what__, string str__)
      logicnew(string name)
      voidbody()
      voidreset​_blk(uvm_reg_block blk)
      voiddo​_block(uvm_reg_block blk, string kind)
      voidcheck​_reg(uvm_reg r, string kind)
      voidcheck​_mem(uvm_mem m, string kind)
      voidreseed()
      voidset​_name(string name)
      stringget​_name()
      stringget​_full​_name()
      intget​_inst​_id()
      intget​_inst​_count()
      uvm_objectclone()
      voidprint(uvm_printer printer)
      stringsprint(uvm_printer printer)
      voiddo​_print(uvm_printer printer)

      Function- do_print

      stringconvert2string()
      voidrecord(uvm_recorder recorder)
      voiddo​_record(uvm_recorder recorder)
      voidcopy(uvm_object rhs)
      voiddo​_copy(uvm_object rhs)
      bitcompare(uvm_object rhs, uvm_comparer comparer)
      bitdo​_compare(uvm_object rhs, uvm_comparer comparer)
      intpack(bit[] bitstream, uvm_packer packer)
      intpack​_bytes(byte[] bytestream, uvm_packer packer)
      intpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_pack(uvm_packer packer)
      intunpack(bit[] bitstream, uvm_packer packer)
      intunpack​_bytes(byte[] bytestream, uvm_packer packer)
      intunpack​_ints(int[] intstream, uvm_packer packer)
      voiddo​_unpack(uvm_packer packer)
      voidset​_int​_local(string field_name, uvm_bitstream_t value, bit recurse)
      voidset​_string​_local(string field_name, string value, bit recurse)
      voidset​_object​_local(string field_name, uvm_object value, bit clone, bit recurse)
      voidm​_pack(uvm_packer packer)
      voidm​_unpack​_pre(uvm_packer packer)
      voidm​_unpack​_post(uvm_packer packer)
      uvm_report_objectm​_get​_report​_object()
      voidaccept​_tr(time accept_time)
      voiddo​_accept​_tr()
      integerbegin​_tr(time begin_time)
      integerbegin​_child​_tr(time begin_time, integer parent_handle)
      voiddo​_begin​_tr()
      voidend​_tr(time end_time, bit free_handle)
      voiddo​_end​_tr()
      integerget​_tr​_handle()
      voiddisable​_recording()
      voidenable​_recording(uvm_tr_stream stream)
      bitis​_recording​_enabled()
      bitis​_active()
      uvm_event_poolget​_event​_pool()
      voidset​_initiator(uvm_component initiator)
      uvm_componentget​_initiator()
      timeget​_accept​_time()
      timeget​_begin​_time()
      timeget​_end​_time()
      voidset​_transaction​_id(integer id)
      integerget​_transaction​_id()
      integerm​_begin​_tr(time begin_time, integer parent_handle)
      voidset​_sequence​_id(int id)
      intget​_sequence​_id()
      voidset​_item​_context(uvm_sequence_base parent_seq, uvm_sequencer_base sequencer)
      voidset​_use​_sequence​_info(bit value)
      bitget​_use​_sequence​_info()
      voidset​_id​_info(uvm_sequence_item item)
      voidset​_sequencer(uvm_sequencer_base sequencer)
      uvm_sequencer_baseget​_sequencer()
      voidset​_parent​_sequence(uvm_sequence_base parent)
      uvm_sequence_baseget​_parent​_sequence()
      voidset​_depth(int value)
      intget​_depth()
      bitis​_item()
      stringget​_root​_sequence​_name()
      voidm​_set​_p​_sequencer()
      uvm_sequence_baseget​_root​_sequence()
      stringget​_sequence​_path()
      uvm_report_objectuvm​_get​_report​_object()
      intuvm​_report​_enabled(int verbosity, uvm_severity severity, string id)
      voiduvm​_report(uvm_severity severity, string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_info(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_warning(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_error(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_report​_fatal(string id, string message, int verbosity, string filename, int line, string context_name, bit report_enabled_checked)
      voiduvm​_process​_report​_message(uvm_report_message report_message)
      uvm_sequence_state_enumget​_sequence​_state()
      voidwait​_for​_sequence​_state(int state_mask)
      voidstart(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence, int this_priority, bit call_pre_post)
      voidpre​_start()
      voidpre​_body()
      voidpre​_do(bit is_item)
      voidmid​_do(uvm_sequence_item this_item)
      voidpost​_do(uvm_sequence_item this_item)
      voidpost​_body()
      voidpost​_start()
      voidm​_init​_phase​_daps(bit create)

      Function- m_init_phase_daps Either creates or renames DAPS

      uvm_phaseget​_starting​_phase()

      Function: get_starting_phase Returns the 'starting phase'.

      If non-~null~, the starting phase specifies the phase in which this sequence was started. The starting phase is set automatically when this sequence is started as the default sequence on a sequencer. See <uvm_sequencer_base::start_phase_sequence> for more information.

      Internally, the <uvm_sequence_base> uses an <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_starting​_phase(uvm_phase phase)

      Function: set_starting_phase Sets the 'starting phase'.

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the starting phase value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the starting phase value can be modified again.

      voidset​_automatic​_phase​_objection(bit value)

      Function: set_automatic_phase_objection Sets the 'automatically object to starting phase' bit.

      The most common interaction with the starting phase within a sequence is to simply ~raise~ the phase's objection prior to executing the sequence, and ~drop~ the objection after ending the sequence (either naturally, or via a call to ). In order to simplify this interaction for the user, the UVM provides the ability to perform this functionality automatically.

      For example: | function my_sequence::new(string name="unnamed"); | super.new(name); | set_automatic_phase_objection(1); | endfunction : new

      From a timeline point of view, the automatic phase objection looks like: | start() is executed | --! Objection is raised !-- | pre_start() is executed | pre_body() is optionally executed | body() is executed | post_body() is optionally executed | post_start() is executed | --! Objection is dropped !-- | start() unblocks

      This functionality can also be enabled in sequences which were not written with UVM Run-Time Phasing in mind: | my_legacy_seq_type seq = new("seq"); | seq.set_automatic_phase_objection(1); | seq.start(my_sequencer);

      Internally, the <uvm_sequence_base> uses a <uvm_get_to_lock_dap> to protect the ~automatic_phase_objection~ value from being modified after the reference has been read. Once the sequence has ended its execution (either via natural termination, or being killed), then the ~automatic_phase_objection~ value can be modified again.

      NEVER set the automatic phase objection bit to 1 if your sequence runs with a forever loop inside of the body, as the objection will never get dropped!

      bitget​_automatic​_phase​_objection()

      Function: get_automatic_phase_objection Returns (and locks) the value of the 'automatically object to starting phase' bit.

      If 1, then the sequence will automatically raise an objection to the starting phase (if the starting phase is not ~null~) immediately prior to <pre_start> being called. The objection will be dropped after <post_start> has executed, or has been called.

      voidm​_safe​_raise​_starting​_phase(string description, int count)

      m_safe_raise_starting_phase

      voidm​_safe​_drop​_starting​_phase(string description, int count)

      m_safe_drop_starting_phase

      voidset​_priority(int value)
      intget​_priority()
      bitis​_relevant()
      voidwait​_for​_relevant()
      voidlock(uvm_sequencer_base sequencer)
      voidgrab(uvm_sequencer_base sequencer)
      voidunlock(uvm_sequencer_base sequencer)
      voidungrab(uvm_sequencer_base sequencer)
      bitis​_blocked()
      bithas​_lock()
      voidkill()
      voiddo​_kill()
      voidm​_kill()
      uvm_sequence_itemcreate​_item(uvm_object_wrapper type_var, uvm_sequencer_base l_sequencer, string name)
      voidstart​_item(uvm_sequence_item item, int set_priority, uvm_sequencer_base sequencer)
      voidfinish​_item(uvm_sequence_item item, int set_priority)
      voidwait​_for​_grant(int item_priority, bit lock_request)
      voidsend​_request(uvm_sequence_item request, bit rerandomize)
      voidwait​_for​_item​_done(int transaction_id)
      voiduse​_response​_handler(bit enable)
      bitget​_use​_response​_handler()
      voidresponse​_handler(uvm_sequence_item response)
      voidset​_response​_queue​_error​_report​_disabled(bit value)
      bitget​_response​_queue​_error​_report​_disabled()
      voidset​_response​_queue​_depth(int value)
      intget​_response​_queue​_depth()
      voidclear​_response​_queue()
      voidput​_base​_response(uvm_sequence_item response)
      voidput​_response(uvm_sequence_item response_item)
      voidget​_base​_response(uvm_sequence_item response, int transaction_id)
      intnum​_sequences()
      intget​_seq​_kind(string type_name)
      uvm_sequence_baseget​_sequence(int req_kind)
      voiddo​_sequence​_kind(int req_kind)
      uvm_sequence_baseget​_sequence​_by​_name(string seq_name)
      voidcreate​_and​_start​_sequence​_by​_name(string seq_name)
      intm​_get​_sqr​_sequence​_id(int sequencer_id, bit update_sequence_id)
      voidm​_set​_sqr​_sequence​_id(int sequencer_id, int sequence_id)
      uvm_reg_itemget​_current​_item()
      voidget​_response(RSP response, int transaction_id)
      voiddo​_reg​_item(uvm_reg_item rw)
      voidwrite​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidupdate​_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidmirror​_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidwrite​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidread​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno)
      voidpoke​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)
      voidpeek​_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno)

    Module xbar​_main

    This design unit is implemented in xbar​_main.sv

    This file depends on: tlul_fifo_async.sv, tl_main_pkg.sv, tlul_socket_m1.sv, tlul_pkg.sv, lc_ctrl_pkg.sv, tlul_socket_1n.sv

    Ports

    NameDirectionTypeDescription
    clk​_main​_iinlogic
    clk​_fixed​_iinlogic
    rst​_main​_niinlogic
    rst​_fixed​_niinlogic
    tl​_corei​_iintl_h2d_t

    Host interfaces

    tl​_corei​_oouttl_d2h_t
    tl​_cored​_iintl_h2d_t
    tl​_cored​_oouttl_d2h_t
    tl​_dm​_sba​_iintl_h2d_t
    tl​_dm​_sba​_oouttl_d2h_t
    tl​_rom​_oouttl_h2d_t

    Device interfaces

    tl​_rom​_iintl_d2h_t
    tl​_debug​_mem​_oouttl_h2d_t
    tl​_debug​_mem​_iintl_d2h_t
    tl​_ram​_main​_oouttl_h2d_t
    tl​_ram​_main​_iintl_d2h_t
    tl​_eflash​_oouttl_h2d_t
    tl​_eflash​_iintl_d2h_t
    tl​_peri​_oouttl_h2d_t
    tl​_peri​_iintl_d2h_t
    tl​_flash​_ctrl​_oouttl_h2d_t
    tl​_flash​_ctrl​_iintl_d2h_t
    tl​_hmac​_oouttl_h2d_t
    tl​_hmac​_iintl_d2h_t
    tl​_kmac​_oouttl_h2d_t
    tl​_kmac​_iintl_d2h_t
    tl​_aes​_oouttl_h2d_t
    tl​_aes​_iintl_d2h_t
    tl​_entropy​_src​_oouttl_h2d_t
    tl​_entropy​_src​_iintl_d2h_t
    tl​_csrng​_oouttl_h2d_t
    tl​_csrng​_iintl_d2h_t
    tl​_edn0​_oouttl_h2d_t
    tl​_edn0​_iintl_d2h_t
    tl​_edn1​_oouttl_h2d_t
    tl​_edn1​_iintl_d2h_t
    tl​_rv​_plic​_oouttl_h2d_t
    tl​_rv​_plic​_iintl_d2h_t
    tl​_otbn​_oouttl_h2d_t
    tl​_otbn​_iintl_d2h_t
    tl​_keymgr​_oouttl_h2d_t
    tl​_keymgr​_iintl_d2h_t
    tl​_sram​_ctrl​_main​_oouttl_h2d_t
    tl​_sram​_ctrl​_main​_iintl_d2h_t
    scanmode​_iinlc_tx_t

    Instantiations

    Block Diagram

    Module xbar​_peri

    This design unit is implemented in xbar​_peri.sv

    This file depends on: tlul_pkg.sv, lc_ctrl_pkg.sv, tlul_socket_1n.sv, tl_peri_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_peri​_iinlogic
    rst​_peri​_niinlogic
    tl​_main​_iintl_h2d_t

    Host interfaces

    tl​_main​_oouttl_d2h_t
    tl​_uart0​_oouttl_h2d_t

    Device interfaces

    tl​_uart0​_iintl_d2h_t
    tl​_uart1​_oouttl_h2d_t
    tl​_uart1​_iintl_d2h_t
    tl​_uart2​_oouttl_h2d_t
    tl​_uart2​_iintl_d2h_t
    tl​_uart3​_oouttl_h2d_t
    tl​_uart3​_iintl_d2h_t
    tl​_i2c0​_oouttl_h2d_t
    tl​_i2c0​_iintl_d2h_t
    tl​_i2c1​_oouttl_h2d_t
    tl​_i2c1​_iintl_d2h_t
    tl​_i2c2​_oouttl_h2d_t
    tl​_i2c2​_iintl_d2h_t
    tl​_pattgen​_oouttl_h2d_t
    tl​_pattgen​_iintl_d2h_t
    tl​_gpio​_oouttl_h2d_t
    tl​_gpio​_iintl_d2h_t
    tl​_spi​_device​_oouttl_h2d_t
    tl​_spi​_device​_iintl_d2h_t
    tl​_spi​_host0​_oouttl_h2d_t
    tl​_spi​_host0​_iintl_d2h_t
    tl​_spi​_host1​_oouttl_h2d_t
    tl​_spi​_host1​_iintl_d2h_t
    tl​_rv​_timer​_oouttl_h2d_t
    tl​_rv​_timer​_iintl_d2h_t
    tl​_usbdev​_oouttl_h2d_t
    tl​_usbdev​_iintl_d2h_t
    tl​_pwrmgr​_aon​_oouttl_h2d_t
    tl​_pwrmgr​_aon​_iintl_d2h_t
    tl​_rstmgr​_aon​_oouttl_h2d_t
    tl​_rstmgr​_aon​_iintl_d2h_t
    tl​_clkmgr​_aon​_oouttl_h2d_t
    tl​_clkmgr​_aon​_iintl_d2h_t
    tl​_pinmux​_aon​_oouttl_h2d_t
    tl​_pinmux​_aon​_iintl_d2h_t
    tl​_ram​_ret​_aon​_oouttl_h2d_t
    tl​_ram​_ret​_aon​_iintl_d2h_t
    tl​_otp​_ctrl​_oouttl_h2d_t
    tl​_otp​_ctrl​_iintl_d2h_t
    tl​_lc​_ctrl​_oouttl_h2d_t
    tl​_lc​_ctrl​_iintl_d2h_t
    tl​_sensor​_ctrl​_aon​_oouttl_h2d_t
    tl​_sensor​_ctrl​_aon​_iintl_d2h_t
    tl​_alert​_handler​_oouttl_h2d_t
    tl​_alert​_handler​_iintl_d2h_t
    tl​_sram​_ctrl​_ret​_aon​_oouttl_h2d_t
    tl​_sram​_ctrl​_ret​_aon​_iintl_d2h_t
    tl​_aon​_timer​_aon​_oouttl_h2d_t
    tl​_aon​_timer​_aon​_iintl_d2h_t
    tl​_ast​_wrapper​_oouttl_h2d_t
    tl​_ast​_wrapper​_iintl_d2h_t
    scanmode​_iinlc_tx_t

    Instantiations

    Block Diagram

    Module aes​_core

    This design unit is implemented in aes​_core.sv

    This file depends on: aes_control.sv, aes_sel_buf_chk.sv, prim_subreg_shadow.sv, uvm_pkg.sv, aes_prng_clearing.sv, aes_cipher_core.sv, aes_pkg.sv, aes_ctr.sv, aes_reg_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    AES192Enablebit1
    Maskingbit0
    SBoxImplsbox_impl_eSBoxImplLut
    SecStartTriggerDelayint0
    SecAllowForcingMasksbit0
    NumSharesintMasking ? 2 : 1

    derived parameter

    RndCnstClearingLfsrSeedclearing_lfsr_seed_tRndCnstClearingLfsrSeedDefault
    RndCnstClearingLfsrPermclearing_lfsr_perm_tRndCnstClearingLfsrPermDefault
    RndCnstMaskingLfsrSeedmasking_lfsr_seed_tRndCnstMaskingLfsrSeedDefault
    RndCnstMskgChunkLfsrPermmskg_chunk_lfsr_perm_tRndCnstMskgChunkLfsrPermDefault
    NumChunksint128/WidthPRDClearing

    Generate clearing signals of appropriate widths.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    entropy​_clearing​_req​_ooutlogic

    Entropy request interfaces for clearing and masking PRNGs

    entropy​_clearing​_ack​_iinlogic
    entropy​_clearing​_iin[WidthPRDClearing-1:0] logic
    entropy​_masking​_req​_ooutlogic
    entropy​_masking​_ack​_iinlogic
    entropy​_masking​_iin[WidthPRDMasking-1:0] logic
    alert​_recov​_ooutlogic

    Alerts

    alert​_fatal​_ooutlogic
    reg2hwinaes_reg2hw_t

    Bus Interface

    hw2regoutaes_hw2reg_t

    Instantiations

    Block Diagram

    State Machines

    Module aes​_reg​_top

    This design unit is implemented in aes​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, aes_reg_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint7
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutaes_reg2hw_t

    Write

    hw2reginaes_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module alert​_handler​_accu

    This design unit is implemented in alert​_handler​_accu.sv

    This file depends on: uvm_pkg.sv, alert_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    class​_en​_iinlogic

    class enable

    clr​_iinlogic

    clear the accumulator

    class​_trig​_iinlogic

    increments the accu

    thresh​_iin[AccuCntDw-1:0] logic

    escalation trigger threshold

    accu​_cnt​_oout[AccuCntDw-1:0] logic

    output of current accu value

    accu​_trig​_ooutlogic

    escalation trigger output

    Block Diagram

    Module alert​_handler​_class

    This design unit is implemented in alert​_handler​_class.sv

    This file depends on: alert_pkg.sv

    Ports

    NameDirectionTypeDescription
    alert​_trig​_iin[NAlerts-1:0] logic

    alert trigger

    loc​_alert​_trig​_iin[N_LOC_ALERT-1:0] logic

    alert trigger

    alert​_en​_iin[NAlerts-1:0] logic

    alert enable

    loc​_alert​_en​_iin[N_LOC_ALERT-1:0] logic

    alert enable

    alert​_class​_iin[CLASS_DW-1:0] [NAlerts-1:0] logic

    class assignment

    loc​_alert​_class​_iin[CLASS_DW-1:0] [N_LOC_ALERT-1:0] logic

    class assignment

    alert​_cause​_oout[NAlerts-1:0] logic

    alert cause

    loc​_alert​_cause​_oout[N_LOC_ALERT-1:0] logic

    alert cause

    class​_trig​_oout[N_CLASSES-1:0] logic

    class triggered

    Block Diagram

    Module alert​_handler​_esc​_timer

    This design unit is implemented in alert​_handler​_esc​_timer.sv

    This file depends on: uvm_pkg.sv, alert_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    en​_iinlogic

    enables timeout/escalation

    clr​_iinlogic

    aborts escalation

    accum​_trig​_iinlogic

    this will trigger escalation

    timeout​_en​_iinlogic

    enables timeout

    timeout​_cyc​_iin[EscCntDw-1:0] logic

    interrupt timeout. 0 = disabled

    esc​_en​_iin[N_ESC_SEV-1:0] logic

    escalation signal enables

    esc​_map​_iin[PHASE_DW-1:0] [N_ESC_SEV-1:0] logic

    escalation signal / phase map

    phase​_cyc​_iin[EscCntDw-1:0] [N_PHASES-1:0] logic

    cycle counts of individual phases

    esc​_trig​_ooutlogic

    asserted if escalation triggers

    esc​_cnt​_oout[EscCntDw-1:0] logic

    current timeout / escalation count

    esc​_sig​_req​_oout[N_ESC_SEV-1:0] logic

    escalation signal outputs

    esc​_state​_ooutcstate_e

    current state output 000: idle, 001: irq timeout counting 100: phase0, 101: phase1, 110: phase2, 111: phase3

    Block Diagram

    State Machines

    Module alert​_handler​_ping​_timer

    This design unit is implemented in alert​_handler​_ping​_timer.sv

    This file depends on: uvm_pkg.sv, prim_lfsr.sv, alert_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    RndCnstLfsrSeedlfsr_seed_tRndCnstLfsrSeedDefault

    Compile time random constants, to be overriden by topgen.

    RndCnstLfsrPermlfsr_perm_tRndCnstLfsrPermDefault
    MaxLenSVAbit1'b1

    Enable this for DV, disable this for long LFSRs in FPV

    LockupSVAbit1'b1

    Can be disabled in cases where entropy inputs are unused in order to not distort coverage (the SVA will be unreachable in such cases)

    NModsToPingintNAlerts + N_ESC_SEV
    IdDwint$clog2(NModsToPing)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    entropy​_iinlogic

    from TRNG

    en​_iinlogic

    enable ping testing

    alert​_en​_iin[NAlerts-1:0] logic

    determines which alerts to ping

    ping​_timeout​_cyc​_iin[PING_CNT_DW-1:0] logic

    timeout in cycles

    wait​_cyc​_mask​_iin[PING_CNT_DW-1:0] logic

    wait cycles mask

    alert​_ping​_req​_oout[NAlerts-1:0] logic

    request to alert receivers

    esc​_ping​_req​_oout[N_ESC_SEV-1:0] logic

    enable to esc senders

    alert​_ping​_ok​_iin[NAlerts-1:0] logic

    response from alert receivers

    esc​_ping​_ok​_iin[N_ESC_SEV-1:0] logic

    response from esc senders

    alert​_ping​_fail​_ooutlogic

    any of the alert receivers failed

    esc​_ping​_fail​_ooutlogic

    any of the esc senders failed

    Instantiations

    Block Diagram

    State Machines

    Package alert​_handler​_reg​_pkg

    This design unit is implemented in alert​_handler​_reg​_pkg.sv

    Module alert​_handler​_reg​_wrap

    This design unit is implemented in alert​_handler​_reg​_wrap.sv

    This file depends on: alert_handler_reg_pkg.sv, alert_pkg.sv, prim_intr_hw.sv, tlul_pkg.sv, alert_handler_reg_top.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Bus Interface (device)

    tl​_oouttl_d2h_t
    irq​_oout[N_CLASSES-1:0] logic

    interrupt

    crashdump​_ooutalert_crashdump_t

    State information for HW crashdump

    hw2reg​_wrapinhw2reg_wrap_t

    hw2reg

    reg2hw​_wrapoutreg2hw_wrap_t

    reg2hw

    Instantiations

    Block Diagram

    Module aon​_osc

    This design unit is implemented in aon​_osc.sv

    Description

    of aon_osc

    Parameters

    NameTypeDefault ValueDescription
    AON​_EN​_RDLYtime5us
    AonClkPeriodtime5000ns

    5000ns (200Khz)

    Ports

    NameDirectionTypeDescription
    vcore​_pok​_h​_iinlogic

    VCORE POK @3.3V

    aon​_en​_iinlogic

    AON Source Clock Enable

    aon​_clk​_ooutlogic

    AON Clock Output

    Block Diagram

    Module aon​_timer​_core

    This design unit is implemented in aon​_timer​_core.sv

    This file depends on: lc_ctrl_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_aon​_iinlogic
    rst​_aon​_niinlogic
    lc​_escalate​_en​_iin[2:0] lc_tx_t
    sleep​_mode​_iinlogic
    wkup​_enable​_ooutlogic

    Register read outputs

    wkup​_prescaler​_oout[11:0] logic
    wkup​_thold​_oout[31:0] logic
    wkup​_count​_oout[31:0] logic
    wdog​_enable​_ooutlogic
    wdog​_pause​_ooutlogic
    wdog​_bark​_thold​_oout[31:0] logic
    wdog​_bite​_thold​_oout[31:0] logic
    wdog​_count​_oout[31:0] logic
    wkup​_ctrl​_reg​_wr​_iinlogic

    Register write inputs

    wkup​_ctrl​_wr​_data​_iin[12:0] logic
    wkup​_thold​_reg​_wr​_iinlogic
    wkup​_thold​_wr​_data​_iin[31:0] logic
    wkup​_count​_reg​_wr​_iinlogic
    wkup​_count​_wr​_data​_iin[31:0] logic
    wdog​_ctrl​_reg​_wr​_iinlogic
    wdog​_ctrl​_wr​_data​_iin[1:0] logic
    wdog​_bark​_thold​_reg​_wr​_iinlogic
    wdog​_bark​_thold​_wr​_data​_iin[31:0] logic
    wdog​_bite​_thold​_reg​_wr​_iinlogic
    wdog​_bite​_thold​_wr​_data​_iin[31:0] logic
    wdog​_count​_reg​_wr​_iinlogic
    wdog​_count​_wr​_data​_iin[31:0] logic
    wkup​_intr​_ooutlogic
    wdog​_intr​_ooutlogic
    wdog​_reset​_req​_ooutlogic

    Block Diagram

    Package aon​_timer​_reg​_pkg

    This design unit is implemented in aon​_timer​_reg​_pkg.sv

    Module aon​_timer​_reg​_top

    This design unit is implemented in aon​_timer​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, aon_timer_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint6
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutaon_timer_reg2hw_t

    Write

    hw2reginaon_timer_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Package clkmgr​_reg​_pkg

    This design unit is implemented in clkmgr​_reg​_pkg.sv

    Module clkmgr​_reg​_top

    This design unit is implemented in clkmgr​_reg​_top.sv

    This file depends on: prim_subreg.sv, uvm_pkg.sv, clkmgr_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint4
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutclkmgr_reg2hw_t

    Write

    hw2reginclkmgr_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module csrng​_core

    This design unit is implemented in csrng​_core.sv

    This file depends on: csrng_pkg.sv, entropy_src_pkg.sv, csrng_state_db.sv, csrng_ctr_drbg_upd.sv, prim_lc_sync.sv, prim_intr_hw.sv, csrng_reg_pkg.sv, csrng_block_encrypt.sv, prim_arbiter_ppc.sv, csrng_ctr_drbg_gen.sv, csrng_ctr_drbg_cmd.sv, aes_pkg.sv, lc_ctrl_pkg.sv, csrng_main_sm.sv, prim_packer_fifo.sv, csrng_cmd_stage.sv

    Description

    csrng_core

    Parameters

    NameTypeDefault ValueDescription
    SBoxImplsbox_impl_eaes_pkg::SBoxImplLut
    NHwAppsint2
    NAppsintNHwApps + 1
    AppCmdWidthint32
    AppCmdFifoDepthint2
    GenBitsWidthint128
    Cmdint3
    StateIdint4
    KeyLenint256
    BlkLenint128
    SeedLenint384
    CtrLenint32
    NBlkEncArbReqsint2
    BlkEncArbWidthintKeyLen+BlkLen+StateId+Cmd
    NUpdateArbReqsint2
    UpdateArbWidthintKeyLen+BlkLen+SeedLen+StateId+Cmd

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    reg2hwincsrng_reg2hw_t
    hw2regoutcsrng_hw2reg_t
    efuse​_sw​_app​_enable​_iinlogic

    Efuse Interface

    lc​_hw​_debug​_en​_iinlc_tx_t

    Lifecycle broadcast inputs

    entropy​_src​_hw​_if​_ooutentropy_src_hw_if_req_t

    Entropy Interface

    entropy​_src​_hw​_if​_iinentropy_src_hw_if_rsp_t
    csrng​_cmd​_iin[NHwApps-1:0] csrng_req_t

    Application Interfaces

    csrng​_cmd​_oout[NHwApps-1:0] csrng_rsp_t
    alert​_test​_ooutlogic

    Alerts

    fatal​_alert​_ooutlogic
    intr​_cs​_cmd​_req​_done​_ooutlogic
    intr​_cs​_entropy​_req​_ooutlogic
    intr​_cs​_hw​_inst​_exc​_ooutlogic
    intr​_cs​_fatal​_err​_ooutlogic

    Instantiations

    Block Diagram

    Package csrng​_reg​_pkg

    This design unit is implemented in csrng​_reg​_pkg.sv

    Module csrng​_reg​_top

    This design unit is implemented in csrng​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, csrng_reg_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint6
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutcsrng_reg2hw_t

    Write

    hw2regincsrng_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module dm​_csrs

    This design unit is implemented in dm​_csrs.sv

    This file depends on: prim_fifo_sync.sv, dm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    NrHartsint1
    BusWidthint32
    SelectableHarts[NrHarts-1:0] logic{NrHarts{1'b1}}
    HartSelLenint(NrHarts == 1) ? 1 : $clog2(NrHarts)

    the amount of bits we need to represent all harts

    NrHartsAlignedint2**HartSelLen
    DataEnddm_csr_edm::dm_csr_e'(dm::Data0 + {4'h0, dm::DataCount} - 8'h1)
    ProgBufEnddm_csr_edm::dm_csr_e'(dm::ProgBuf0 + {4'h0, dm::ProgBufSize} - 8'h1)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock

    rst​_niinlogic

    Asynchronous reset active low

    testmode​_iinlogic
    dmi​_rst​_niinlogic

    Debug Module Intf reset active-low

    dmi​_req​_valid​_iinlogic
    dmi​_req​_ready​_ooutlogic
    dmi​_req​_iindmi_req_t
    dmi​_resp​_valid​_ooutlogic

    every request needs a response one cycle later

    dmi​_resp​_ready​_iinlogic
    dmi​_resp​_ooutdmi_resp_t
    ndmreset​_ooutlogic

    non-debug module reset active-high

    dmactive​_ooutlogic

    1 -> debug-module is active, 0 -> synchronous re-set

    hartinfo​_iin[NrHarts-1:0] hartinfo_t

    static hartinfo

    halted​_iin[NrHarts-1:0] logic

    hart is halted

    unavailable​_iin[NrHarts-1:0] logic

    e.g.: powered down

    resumeack​_iin[NrHarts-1:0] logic

    hart acknowledged resume request

    hartsel​_oout[19:0] logic

    hartselect to ctrl module

    haltreq​_oout[NrHarts-1:0] logic

    request to halt a hart

    resumereq​_oout[NrHarts-1:0] logic

    request hart to resume

    clear​_resumeack​_ooutlogic
    cmd​_valid​_ooutlogic

    debugger writing to cmd field

    cmd​_ooutcommand_t

    abstract command

    cmderror​_valid​_iinlogic

    an error occurred

    cmderror​_iincmderr_e

    this error occurred

    cmdbusy​_iinlogic

    cmd is currently busy executing

    progbuf​_oout[31:0] [dm::ProgBufSize-1:0] logic

    to system bus

    data​_oout[31:0] [dm::DataCount-1:0] logic
    data​_iin[31:0] [dm::DataCount-1:0] logic
    data​_valid​_iinlogic
    sbaddress​_oout[BusWidth-1:0] logic

    system bus access module (SBA)

    sbaddress​_iin[BusWidth-1:0] logic
    sbaddress​_write​_valid​_ooutlogic
    sbreadonaddr​_ooutlogic

    control signals in

    sbautoincrement​_ooutlogic
    sbaccess​_oout[2:0] logic
    sbreadondata​_ooutlogic

    data out

    sbdata​_oout[BusWidth-1:0] logic
    sbdata​_read​_valid​_ooutlogic
    sbdata​_write​_valid​_ooutlogic
    sbdata​_iin[BusWidth-1:0] logic

    read data in

    sbdata​_valid​_iinlogic
    sbbusy​_iinlogic

    control signals

    sberror​_valid​_iinlogic

    bus error occurred

    sberror​_iin[2:0] logic

    bus error occurred

    Instantiations

    Block Diagram

    Module dm​_mem

    This design unit is implemented in dm​_mem.sv

    This file depends on: debug_rom_one_scratch.sv, dm_pkg.sv, debug_rom.sv

    Parameters

    NameTypeDefault ValueDescription
    NrHartsint1
    BusWidthint32
    SelectableHarts[NrHarts-1:0] logic{NrHarts{1'b1}}
    DmBaseAddressint'0
    DbgAddressBitsint12
    HartSelLenint(NrHarts == 1) ? 1 : $clog2(NrHarts)
    NrHartsAlignedint2**HartSelLen
    MaxAarint(BusWidth == 64) ? 4 : 3
    HasSndScratchbit(DmBaseAddress != 0)
    LoadBaseAddr[4:0] logic(DmBaseAddress == 0) ? 5'd0 : 5'd10

    Depending on whether we are at the zero page or not we either use x0 or x10/a0

    DataBaseAddr[DbgAddressBits-1:0] logic(dm::DataAddr)
    DataEndAddr[DbgAddressBits-1:0] logic(dm::DataAddr + 4*dm::DataCount - 1)
    ProgBufBaseAddr[DbgAddressBits-1:0] logic(dm::DataAddr - 4*dm::ProgBufSize)
    ProgBufEndAddr[DbgAddressBits-1:0] logic(dm::DataAddr - 1)
    AbstractCmdBaseAddr[DbgAddressBits-1:0] logic(ProgBufBaseAddr - 4*10)
    AbstractCmdEndAddr[DbgAddressBits-1:0] logic(ProgBufBaseAddr - 1)
    WhereToAddr[DbgAddressBits-1:0] logic'h300
    FlagsBaseAddr[DbgAddressBits-1:0] logic'h400
    FlagsEndAddr[DbgAddressBits-1:0] logic'h7FF
    HaltedAddr[DbgAddressBits-1:0] logic'h100
    GoingAddr[DbgAddressBits-1:0] logic'h104
    ResumingAddr[DbgAddressBits-1:0] logic'h108
    ExceptionAddr[DbgAddressBits-1:0] logic'h10C

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock

    rst​_niinlogic

    debug module reset

    debug​_req​_oout[NrHarts-1:0] logic
    hartsel​_iin[19:0] logic
    haltreq​_iin[NrHarts-1:0] logic

    from Ctrl and Status register

    resumereq​_iin[NrHarts-1:0] logic
    clear​_resumeack​_iinlogic
    halted​_oout[NrHarts-1:0] logic

    hart acknowledge halt

    resuming​_oout[NrHarts-1:0] logic

    hart is resuming

    progbuf​_iin[31:0] [dm::ProgBufSize-1:0] logic

    program buffer to expose

    data​_iin[31:0] [dm::DataCount-1:0] logic

    data in

    data​_oout[31:0] [dm::DataCount-1:0] logic

    data out

    data​_valid​_ooutlogic

    data out is valid

    cmd​_valid​_iinlogic

    abstract command interface

    cmd​_iincommand_t
    cmderror​_valid​_ooutlogic
    cmderror​_ooutcmderr_e
    cmdbusy​_ooutlogic
    req​_iinlogic

    SRAM interface

    we​_iinlogic
    addr​_iin[BusWidth-1:0] logic
    wdata​_iin[BusWidth-1:0] logic
    be​_iin[BusWidth/8-1:0] logic
    rdata​_oout[BusWidth-1:0] logic

    Block Diagram

    State Machines

    Module dm​_sba

    This design unit is implemented in dm​_sba.sv

    This file depends on: dm_pkg.sv

    Description

    Copyright 2018 ETH Zurich and University of Bologna.

    Parameters

    NameTypeDefault ValueDescription
    BusWidthint32
    ReadByteEnablebit1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock

    rst​_niinlogic
    dmactive​_iinlogic

    synchronous reset active low

    master​_req​_ooutlogic
    master​_add​_oout[BusWidth-1:0] logic
    master​_we​_ooutlogic
    master​_wdata​_oout[BusWidth-1:0] logic
    master​_be​_oout[BusWidth/8-1:0] logic
    master​_gnt​_iinlogic
    master​_r​_valid​_iinlogic
    master​_r​_rdata​_iin[BusWidth-1:0] logic
    sbaddress​_iin[BusWidth-1:0] logic
    sbaddress​_write​_valid​_iinlogic
    sbreadonaddr​_iinlogic

    control signals in

    sbaddress​_oout[BusWidth-1:0] logic
    sbautoincrement​_iinlogic
    sbaccess​_iin[2:0] logic
    sbreadondata​_iinlogic

    data in

    sbdata​_iin[BusWidth-1:0] logic
    sbdata​_read​_valid​_iinlogic
    sbdata​_write​_valid​_iinlogic
    sbdata​_oout[BusWidth-1:0] logic

    read data out

    sbdata​_valid​_ooutlogic
    sbbusy​_ooutlogic

    control signals

    sberror​_valid​_ooutlogic

    bus error occurred

    sberror​_oout[2:0] logic

    bus error occurred

    Block Diagram

    Module dmi​_jtag

    This design unit is implemented in dmi​_jtag.sv

    This file depends on: dmi_cdc.sv, dm_pkg.sv, dmi_jtag_tap.sv

    Parameters

    NameTypeDefault ValueDescription
    IdcodeValue[31:0] logic32'h00000001

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    DMI Clock

    rst​_niinlogic

    Asynchronous reset active low

    testmode​_iinlogic
    dmi​_rst​_nooutlogic

    hard reset

    dmi​_req​_ooutdmi_req_t
    dmi​_req​_valid​_ooutlogic
    dmi​_req​_ready​_iinlogic
    dmi​_resp​_iindmi_resp_t
    dmi​_resp​_ready​_ooutlogic
    dmi​_resp​_valid​_iinlogic
    tck​_iinlogic

    JTAG test clock pad

    tms​_iinlogic

    JTAG test mode select pad

    trst​_niinlogic

    JTAG test reset pad

    td​_iinlogic

    JTAG test data input pad

    td​_ooutlogic

    JTAG test data output pad

    tdo​_oe​_ooutlogic

    Data out output enable

    Instantiations

    Block Diagram

    State Machines

    Module edn​_core

    This design unit is implemented in edn​_core.sv

    This file depends on: csrng_pkg.sv, prim_arbiter_ppc.sv, edn_reg_pkg.sv, edn_main_sm.sv, prim_intr_hw.sv, prim_fifo_sync.sv, edn_pkg.sv, prim_packer_fifo.sv, edn_ack_sm.sv

    Parameters

    NameTypeDefault ValueDescription
    NumEndPointsint4
    BootInsCmdint32'h0000_0001
    BootGenCmdint32'h0000_1003
    RescmdFifoWidthint32
    RescmdFifoDepthint13
    GencmdFifoWidthint32
    GencmdFifoDepthint13
    CSGenBitsWidthint128
    EndPointBusWidthint32

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    reg2hwinedn_reg2hw_t
    hw2regoutedn_hw2reg_t
    edn​_iin[NumEndPoints-1:0] edn_req_t

    EDN interfaces

    edn​_oout[NumEndPoints-1:0] edn_rsp_t
    csrng​_cmd​_ooutcsrng_req_t

    CSRNG Application Interface

    csrng​_cmd​_iincsrng_rsp_t
    alert​_test​_ooutlogic

    Alerts

    fatal​_alert​_ooutlogic
    intr​_edn​_cmd​_req​_done​_ooutlogic

    Interrupts

    intr​_edn​_fatal​_err​_ooutlogic

    Instantiations

    Block Diagram

    Package edn​_reg​_pkg

    This design unit is implemented in edn​_reg​_pkg.sv

    Module edn​_reg​_top

    This design unit is implemented in edn​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, edn_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint6
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutedn_reg2hw_t

    Write

    hw2reginedn_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module entropy​_src​_core

    This design unit is implemented in entropy​_src​_core.sv

    This file depends on: entropy_src_pkg.sv, entropy_src_cntr_reg.sv, entropy_src_bucket_ht.sv, prim_lfsr.sv, entropy_src_ack_sm.sv, entropy_src_reg_pkg.sv, prim_intr_hw.sv, entropy_src_watermark_reg.sv, entropy_src_adaptp_ht.sv, entropy_src_main_sm.sv, entropy_src_repcnt_ht.sv, prim_fifo_sync.sv, entropy_src_markov_ht.sv, prim_packer_fifo.sv

    Parameters

    NameTypeDefault ValueDescription
    EsFifoDepthint2
    Clog2EsFifoDepthint$clog2(EsFifoDepth)
    PostHTWidthint32
    RngBusWidthint4
    HalfRegWidthint16
    FullRegWidthint32
    EigthRegWidthint4
    SeedLenint384
    PreCondFifoWidthint32
    PreCondFifoDepthint64
    PreCondWidthint64
    Clog2PreCondFifoDepthint$clog2(PreCondFifoDepth)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    reg2hwinentropy_src_reg2hw_t
    hw2regoutentropy_src_hw2reg_t
    efuse​_es​_sw​_reg​_en​_iinlogic

    Efuse Interface

    entropy​_src​_hw​_if​_iinentropy_src_hw_if_req_t

    Entropy Interface

    entropy​_src​_hw​_if​_ooutentropy_src_hw_if_rsp_t
    entropy​_src​_rng​_ooutentropy_src_rng_req_t

    RNG Interface

    entropy​_src​_rng​_iinentropy_src_rng_rsp_t
    entropy​_src​_xht​_ooutentropy_src_xht_req_t

    External Health Test Interface

    entropy​_src​_xht​_iinentropy_src_xht_rsp_t
    recov​_alert​_test​_ooutlogic
    fatal​_alert​_test​_ooutlogic
    recov​_alert​_ooutlogic
    fatal​_alert​_ooutlogic
    intr​_es​_entropy​_valid​_ooutlogic
    intr​_es​_health​_test​_failed​_ooutlogic
    intr​_es​_fatal​_err​_ooutlogic

    Instantiations

    Block Diagram

    Package entropy​_src​_reg​_pkg

    This design unit is implemented in entropy​_src​_reg​_pkg.sv

    Module entropy​_src​_reg​_top

    This design unit is implemented in entropy​_src​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, entropy_src_reg_pkg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint8
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutentropy_src_reg2hw_t

    Write

    hw2reginentropy_src_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module flash​_ctrl​_arb

    This design unit is implemented in flash​_ctrl​_arb.sv

    This file depends on: flash_ctrl_pkg.sv, flash_ctrl_reg_pkg.sv

    Description

    flash_ctrl_rd_arb

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    sw​_ctrl​_iinflash_ctrl_reg2hw_control_reg_t

    software interface to rd_ctrl / erase_ctrl

    sw​_addr​_iin[31:0] logic
    sw​_ack​_ooutlogic
    sw​_err​_ooutlogic
    sw​_rvalid​_ooutlogic

    software interface to rd_fifo

    sw​_rready​_iinlogic
    sw​_wvalid​_iinlogic

    software interface to prog_fifo

    sw​_wready​_ooutlogic
    sw​_wdata​_iin[BusWidth-1:0] logic
    hw​_req​_iinlogic

    hardware interface to rd_ctrl / erase_ctrl

    hw​_ctrl​_iinflash_ctrl_reg2hw_control_reg_t
    hw​_phase​_iinflash_lcmgr_phase_e
    hw​_addr​_iin[31:0] logic
    hw​_ack​_ooutlogic
    hw​_err​_ooutlogic
    hw​_rvalid​_ooutlogic

    hardware interface to rd_fifo

    hw​_rready​_iinlogic
    hw​_wvalid​_iinlogic

    hardware interface to prog_fifo

    hw​_wdata​_iin[BusWidth-1:0] logic
    hw​_wready​_ooutlogic
    muxed​_ctrl​_ooutflash_ctrl_reg2hw_control_reg_t

    muxed interface to rd_ctrl / erase_ctrl

    muxed​_addr​_oout[31:0] logic
    prog​_ack​_iinlogic
    prog​_err​_iinlogic
    rd​_ack​_iinlogic
    rd​_err​_iinlogic
    erase​_ack​_iinlogic
    erase​_err​_iinlogic
    rd​_fifo​_rvalid​_iinlogic

    muxed interface to rd_fifo

    rd​_fifo​_rready​_ooutlogic
    prog​_fifo​_wvalid​_ooutlogic

    muxed interface to prog_fifo

    prog​_fifo​_wdata​_oout[BusWidth-1:0] logic
    prog​_fifo​_wready​_iinlogic
    flash​_phy​_busy​_iinlogic

    flash phy initialization ongoing

    fifo​_clr​_ooutlogic

    clear fifo contents

    phase​_ooutflash_lcmgr_phase_e

    output to memory protection

    sel​_ooutflash_sel_e

    indication that sw has been selected

    Block Diagram

    State Machines

    Module flash​_ctrl​_erase

    This design unit is implemented in flash​_ctrl​_erase.sv

    This file depends on: flash_ctrl_pkg.sv

    Description

    flash_ctrl_erase

    Parameters

    NameTypeDefault ValueDescription
    WordsBitWidthint$clog2(BusWordsPerPage)
    PagesBitWidthint$clog2(PagesPerBank)
    PageAddrMask[BusAddrW-1:0] logic~(('h1 << WordsBitWidth) - 1'b1)

    The *AddrMask below masks out the bits that are not required e.g, assume we have an address 0x5_0004_345C 0x5 represents bank address 0x0004 represents page address PageAddrMask would be 0xF_FFFF_0000 BankAddrMask would be 0xF_0000_0000

    BankAddrMask[BusAddrW-1:0] logic~(('h1 << (PagesBitWidth + WordsBitWidth)) - 1'b1)

    Ports

    NameDirectionTypeDescription
    op​_start​_iinlogic

    Software Interface

    op​_type​_iinflash_erase_e
    op​_addr​_iin[BusAddrW-1:0] logic
    op​_done​_ooutlogic
    op​_err​_ooutlogic
    flash​_req​_ooutlogic

    Flash Macro Interface

    flash​_addr​_oout[BusAddrW-1:0] logic
    flash​_op​_ooutflash_erase_e
    flash​_done​_iinlogic
    flash​_error​_iinlogic

    Block Diagram

    Module flash​_ctrl​_info​_cfg

    This design unit is implemented in flash​_ctrl​_info​_cfg.sv

    This file depends on: flash_ctrl_pkg.sv, flash_ctrl_reg_pkg.sv

    Description

    flash_ctrl_info_cfg

    Parameters

    NameTypeDefault ValueDescription
    Bank[BankW-1:0] logic0
    InfoSelint0
    CfgBitWidthint$bits(info_page_cfg_t)

    Ports

    NameDirectionTypeDescription
    cfgs​_iin[InfosPerBank-1:0] info_page_cfg_t
    creator​_seed​_priv​_iinlogic
    owner​_seed​_priv​_iinlogic
    iso​_flash​_wr​_en​_iinlogic
    iso​_flash​_rd​_en​_iinlogic
    cfgs​_oout[InfosPerBank-1:0] info_page_cfg_t

    Block Diagram

    Module flash​_ctrl​_lcmgr

    This design unit is implemented in flash​_ctrl​_lcmgr.sv

    This file depends on: prim_flop_2sync.sv, top_pkg.sv, prim_lc_sync.sv, otp_ctrl_pkg.sv, flash_ctrl_pkg.sv, prim_sync_reqack.sv, prim_util_pkg.sv, flash_ctrl_reg_pkg.sv, lc_ctrl_pkg.sv

    Description

    flash_ctrl_lcmgr

    Parameters

    NameTypeDefault ValueDescription
    RndCnstAddrKeyflash_key_tRndCnstAddrKeyDefault
    RndCnstDataKeyflash_key_tRndCnstDataKeyDefault
    WipeIdxWidthintprim_util_pkg::vbits(WipeEntries)

    total number of pages to be wiped during RMA entry

    SeedReadsintSeedWidth / BusWidth

    seed related local params

    SeedRdsWidthint$clog2(SeedReads)
    SeedCntWidthint$clog2(NumSeeds+1)
    NumSeedWidthint$clog2(NumSeeds)
    PageCntWidthintprim_util_pkg::vbits(PagesPerBank + 1)
    WordCntWidthintprim_util_pkg::vbits(BusWordsPerPage + 1)
    BeatCntWidthintprim_util_pkg::vbits(WidthMultiple)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    clk​_otp​_iinlogic
    rst​_otp​_niinlogic
    init​_iinlogic

    initialization command

    init​_done​_ooutlogic
    provision​_en​_iinlogic

    only access seeds when provisioned

    ctrl​_ooutflash_ctrl_reg2hw_control_reg_t

    interface to ctrl arb control ports

    req​_ooutlogic
    addr​_oout[top_pkg::TL_AW-1:0] logic
    done​_iinlogic
    err​_iinlogic
    rready​_ooutlogic

    interface to ctrl_arb data ports

    rvalid​_iinlogic
    wvalid​_ooutlogic
    wready​_iinlogic
    rdata​_iin[BusWidth-1:0] logic

    direct form rd_fifo

    wdata​_oout[BusWidth-1:0] logic

    direct to wr_fifo

    rma​_req​_iinlc_tx_t

    external rma request This should be simplified to just multi-bit request and multi-bit response

    rma​_ack​_ooutlc_tx_t
    seeds​_oout[SeedWidth-1:0] [NumSeeds-1:0] logic

    seeds to the outside world,

    phase​_ooutflash_lcmgr_phase_e

    indicate to memory protection what phase the hw interface is in

    seed​_err​_ooutlogic

    error status to registers

    rd​_buf​_en​_ooutlogic

    enable read buffer in flash_phy

    otp​_key​_req​_ooutflash_otp_key_req_t

    request otp keys

    otp​_key​_rsp​_iinflash_otp_key_rsp_t
    addr​_key​_ooutflash_key_t
    data​_key​_ooutflash_key_t
    edn​_req​_ooutlogic

    entropy interface

    edn​_ack​_iinlogic
    lfsr​_en​_ooutlogic
    rand​_iin[BusWidth-1:0] logic
    init​_busy​_ooutlogic

    init ongoing

    Instantiations

    Block Diagram

    State Machines

    Module flash​_ctrl​_prog

    This design unit is implemented in flash​_ctrl​_prog.sv

    This file depends on: flash_ctrl_pkg.sv

    Description

    flash_ctrl_prog

    Parameters

    NameTypeDefault ValueDescription
    WindowWidthintBusAddrW - BusPgmResWidth

    program resolution check if the incoming beat is larger than the maximum program resolution, error immediately and do not allow it to start.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    op​_start​_iinlogic

    Control Interface

    op​_num​_words​_iin[11:0] logic
    op​_done​_ooutlogic
    op​_err​_ooutlogic
    op​_addr​_iin[BusAddrW-1:0] logic
    op​_type​_iinflash_prog_e
    type​_avail​_iin[ProgTypes-1:0] logic
    data​_rdy​_iinlogic

    FIFO Interface

    data​_iin[BusWidth-1:0] logic
    data​_rd​_ooutlogic
    flash​_req​_ooutlogic

    Flash Macro Interface

    flash​_addr​_oout[BusAddrW-1:0] logic
    flash​_ovfl​_ooutlogic
    flash​_data​_oout[BusWidth-1:0] logic
    flash​_last​_ooutlogic

    last beat of prog data

    flash​_type​_ooutflash_prog_e
    flash​_done​_iinlogic
    flash​_error​_iinlogic

    Block Diagram

    State Machines

    Module flash​_ctrl​_rd

    This design unit is implemented in flash​_ctrl​_rd.sv

    This file depends on: flash_ctrl_pkg.sv

    Description

    flash_ctrl_rd

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    op​_start​_iinlogic

    Software Interface

    op​_num​_words​_iin[11:0] logic
    op​_done​_ooutlogic
    op​_err​_ooutlogic
    op​_addr​_iin[BusAddrW-1:0] logic
    data​_rdy​_iinlogic

    FIFO Interface

    data​_oout[BusWidth-1:0] logic
    data​_wr​_ooutlogic
    flash​_req​_ooutlogic

    Flash Macro Interface

    flash​_addr​_oout[BusAddrW-1:0] logic
    flash​_ovfl​_ooutlogic
    flash​_data​_iin[BusWidth-1:0] logic
    flash​_done​_iinlogic
    flash​_error​_iinlogic

    Block Diagram

    State Machines

    Package flash​_ctrl​_reg​_pkg

    This design unit is implemented in flash​_ctrl​_reg​_pkg.sv

    Module flash​_ctrl​_reg​_top

    This design unit is implemented in flash​_ctrl​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, flash_ctrl_reg_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint9
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    tl​_win​_oouttl_h2d_t [3]

    Output port for window

    tl​_win​_iintl_d2h_t [3]
    reg2hwoutflash_ctrl_reg2hw_t

    Write

    hw2reginflash_ctrl_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module flash​_mp

    This design unit is implemented in flash​_mp.sv

    This file depends on: uvm_pkg.sv, flash_ctrl_pkg.sv, flash_ctrl_reg_pkg.sv, flash_mp_data_region_sel.sv

    Description

    flash_erase_ctrl

    Parameters

    NameTypeDefault ValueDescription
    TotalRegionsintMpRegions+1

    Total number of regions including default region

    HwInfoRulesint3

    Hardware interface permission table

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    if​_sel​_iinflash_sel_e

    interface selection

    region​_cfgs​_iin[MpRegions:0] mp_region_cfg_t

    configuration from sw

    bank​_cfgs​_iin[NumBanks-1:0] flash_ctrl_reg2hw_mp_bank_cfg_mreg_t
    info​_page​_cfgs​_iin[InfosPerBank-1:0] [InfoTypes-1:0] [NumBanks-1:0] info_page_cfg_t
    erase​_suspend​_iinlogic
    erase​_suspend​_done​_ooutlogic
    req​_iinlogic

    interface signals to/from *_ctrl

    phase​_iinflash_lcmgr_phase_e
    req​_addr​_iin[AllPagesW-1:0] logic
    req​_part​_iinflash_part_e
    info​_sel​_iin[InfoTypesWidth-1:0] logic
    addr​_ovfl​_iinlogic
    rd​_iinlogic
    prog​_iinlogic
    pg​_erase​_iinlogic
    bk​_erase​_iinlogic
    rd​_done​_ooutlogic
    prog​_done​_ooutlogic
    erase​_done​_ooutlogic
    error​_ooutlogic
    err​_addr​_oout[AllPagesW-1:0] logic
    req​_ooutlogic

    interface signals to/from flash_phy

    rd​_ooutlogic
    prog​_ooutlogic
    scramble​_en​_ooutlogic
    ecc​_en​_ooutlogic
    he​_en​_ooutlogic
    pg​_erase​_ooutlogic
    bk​_erase​_ooutlogic
    erase​_suspend​_ooutlogic
    rd​_done​_iinlogic
    prog​_done​_iinlogic
    erase​_done​_iinlogic

    Instantiations

    Block Diagram

    Module flash​_mp​_data​_region​_sel

    This design unit is implemented in flash​_mp​_data​_region​_sel.sv

    This file depends on: flash_ctrl_pkg.sv, flash_ctrl_reg_pkg.sv

    Description

    flash_mp_data_region_sel

    Parameters

    NameTypeDefault ValueDescription
    Regionsint4

    Ports

    NameDirectionTypeDescription
    req​_iinlogic
    phase​_iinflash_lcmgr_phase_e
    addr​_iin[AllPagesW-1:0] logic
    region​_attrs​_iindata_region_attr_t [Regions]
    sel​_cfg​_ooutmp_region_cfg_t

    Block Diagram

    Module flash​_phy​_core

    This design unit is implemented in flash​_phy​_core.sv

    This file depends on: flash_phy_prog.sv, uvm_pkg.sv, flash_phy_pkg.sv, flash_ctrl_pkg.sv, flash_phy_erase.sv, flash_phy_scramble.sv, flash_phy_rd.sv

    Description

    flash_phy_core

    Parameters

    NameTypeDefault ValueDescription
    ArbCntint4
    CntWidthint$clog2(ArbCnt + 1)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    host​_req​_iinlogic

    host request - read only

    host​_scramble​_en​_iinlogic
    host​_ecc​_en​_iinlogic
    host​_addr​_iin[BusBankAddrW-1:0] logic
    req​_iinlogic

    controller request

    scramble​_en​_iinlogic
    ecc​_en​_iinlogic
    he​_en​_iinlogic
    rd​_iinlogic
    prog​_iinlogic
    pg​_erase​_iinlogic
    bk​_erase​_iinlogic
    erase​_suspend​_req​_iinlogic
    part​_iinflash_part_e
    info​_sel​_iin[InfoTypesWidth-1:0] logic
    addr​_iin[BusBankAddrW-1:0] logic
    prog​_data​_iin[BusWidth-1:0] logic
    prog​_last​_iinlogic
    prog​_type​_iinflash_prog_e
    addr​_key​_iin[KeySize-1:0] logic
    data​_key​_iin[KeySize-1:0] logic
    rd​_buf​_en​_iinlogic
    prim​_flash​_rsp​_iinflash_phy_prim_flash_rsp_t
    prim​_flash​_req​_ooutflash_phy_prim_flash_req_t
    host​_req​_rdy​_ooutlogic
    host​_req​_done​_ooutlogic
    rd​_done​_ooutlogic
    prog​_done​_ooutlogic
    erase​_done​_ooutlogic
    rd​_data​_oout[BusWidth-1:0] logic
    rd​_err​_ooutlogic
    ecc​_single​_err​_ooutlogic
    ecc​_multi​_err​_ooutlogic
    ecc​_addr​_oout[BusBankAddrW-1:0] logic

    Instantiations

    Block Diagram

    State Machines

    Package flash​_phy​_pkg

    This design unit is implemented in flash​_phy​_pkg.sv

    This file depends on: flash_ctrl_pkg.sv

    Description

    flash_phy_pkg

    Package gpio​_reg​_pkg

    This design unit is implemented in gpio​_reg​_pkg.sv

    Module gpio​_reg​_top

    This design unit is implemented in gpio​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, gpio_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint6
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutgpio_reg2hw_t

    Write

    hw2regingpio_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module hmac​_core

    This design unit is implemented in hmac​_core.sv

    This file depends on: hmac_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    BlockSizeint512
    BlockSizeBitsint$clog2(BlockSize)
    HashWordBitsint$clog2($bits(sha_word_t))

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    secret​_keyin[255:0] logic

    {word0, word1, ..., word7}

    wipe​_secretinlogic
    wipe​_vin[31:0] logic
    hmac​_eninlogic
    reg​_hash​_startinlogic
    reg​_hash​_processinlogic
    hash​_doneoutlogic
    sha​_hash​_startoutlogic
    sha​_hash​_processoutlogic
    sha​_hash​_doneinlogic
    sha​_rvalidoutlogic

    fifo

    sha​_rdataoutsha_fifo_t
    sha​_rreadyinlogic
    fifo​_rvalidinlogic
    fifo​_rdatainsha_fifo_t
    fifo​_rreadyoutlogic
    fifo​_wseloutlogic

    0: from reg, 1: from digest

    fifo​_wvalidoutlogic
    fifo​_wdata​_selout[2:0] logic

    0: digest0 .. 7: digest7

    fifo​_wreadyinlogic
    message​_lengthin[63:0] logic
    sha​_message​_lengthout[63:0] logic

    Block Diagram

    State Machines

    Package hmac​_pkg

    This design unit is implemented in hmac​_pkg.sv

    Package hmac​_reg​_pkg

    This design unit is implemented in hmac​_reg​_pkg.sv

    Module hmac​_reg​_top

    This design unit is implemented in hmac​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, hmac_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint12
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    tl​_win​_oouttl_h2d_t [1]

    Output port for window

    tl​_win​_iintl_d2h_t [1]
    reg2hwouthmac_reg2hw_t

    Write

    hw2reginhmac_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module i2c​_core

    This design unit is implemented in i2c​_core.sv

    This file depends on: i2c_reg_pkg.sv, i2c_fsm.sv, prim_fifo_sync.sv, prim_intr_hw.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    reg2hwini2c_reg2hw_t
    hw2regouti2c_hw2reg_t
    scl​_iinlogic
    scl​_ooutlogic
    sda​_iinlogic
    sda​_ooutlogic
    intr​_fmt​_watermark​_ooutlogic
    intr​_rx​_watermark​_ooutlogic
    intr​_fmt​_overflow​_ooutlogic
    intr​_rx​_overflow​_ooutlogic
    intr​_nak​_ooutlogic
    intr​_scl​_interference​_ooutlogic
    intr​_sda​_interference​_ooutlogic
    intr​_stretch​_timeout​_ooutlogic
    intr​_sda​_unstable​_ooutlogic
    intr​_trans​_complete​_ooutlogic
    intr​_tx​_empty​_ooutlogic
    intr​_tx​_nonempty​_ooutlogic
    intr​_tx​_overflow​_ooutlogic
    intr​_acq​_overflow​_ooutlogic
    intr​_ack​_stop​_ooutlogic
    intr​_host​_timeout​_ooutlogic

    Instantiations

    Block Diagram

    Package i2c​_reg​_pkg

    This design unit is implemented in i2c​_reg​_pkg.sv

    Module i2c​_reg​_top

    This design unit is implemented in i2c​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, i2c_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint7
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwouti2c_reg2hw_t

    Write

    hw2regini2c_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module ibex​_core

    This design unit is implemented in ibex​_core.sv

    This file depends on: ibex_cs_registers.sv, uvm_pkg.sv, prim_clock_gating.sv, ibex_ex_block.sv, ibex_pmp.sv, ibex_register_file_ff.sv, ibex_pkg.sv, ibex_wb_stage.sv, ibex_id_stage.sv, ibex_if_stage.sv, prim_secded_39_32_enc.sv, ibex_register_file_fpga.sv, ibex_load_store_unit.sv, prim_secded_39_32_dec.sv, ibex_register_file_latch.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    PMPEnablebit1'b0
    PMPGranularityint0
    PMPNumRegionsint4
    MHPMCounterNumint0
    MHPMCounterWidthint40
    RV32Ebit1'b0
    RV32Mrv32m_eibex_pkg::RV32MFast
    RV32Brv32b_eibex_pkg::RV32BNone
    RegFileregfile_eibex_pkg::RegFileFF
    BranchTargetALUbit1'b0
    WritebackStagebit1'b0
    ICachebit1'b0
    ICacheECCbit1'b0
    BranchPredictorbit1'b0
    DbgTriggerEnbit1'b0
    DbgHwBreakNumint1
    SecureIbexbit1'b0
    DmHaltAddrint32'h1A110800
    DmExceptionAddrint32'h1A110808
    PMP​_NUM​_CHANint2
    DataIndTimingbitSecureIbex
    DummyInstructionsbitSecureIbex
    PCIncrCheckbitSecureIbex
    ShadowCSRbitSecureIbex
    SpecBranchbitPMPEnable & (PMPNumRegions == 16)

    Speculative branch option, trades-off performance against timing. Setting this to 1 eases branch target critical paths significantly but reduces performance by ~3% (based on CoreMark/MHz score). Set by default in the max PMP config which has the tightest budget for branch target timing.

    RegFileECCbitSecureIbex
    RegFileDataWidthintRegFileECC ? 32 + 7 : 32
    RVFI​_STAGESintWritebackStage ? 2 : 1

    When writeback stage is present RVFI information is emitted when instruction is finished in third stage but some information must be captured whilst the instruction is in the second stage. Without writeback stage RVFI information is all emitted when instruction retires in second stage. RVFI outputs are all straight from flops. So 2 stage pipeline requires a single set of flops (instr_info => RVFI_out), 3 stage pipeline requires two sets (instr_info => wb => RVFI_out)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock and Reset

    rst​_niinlogic
    test​_en​_iinlogic

    enable all clock gates for testing

    hart​_id​_iin[31:0] logic
    boot​_addr​_iin[31:0] logic
    instr​_req​_ooutlogic

    Instruction memory interface

    instr​_gnt​_iinlogic
    instr​_rvalid​_iinlogic
    instr​_addr​_oout[31:0] logic
    instr​_rdata​_iin[31:0] logic
    instr​_err​_iinlogic
    data​_req​_ooutlogic

    Data memory interface

    data​_gnt​_iinlogic
    data​_rvalid​_iinlogic
    data​_we​_ooutlogic
    data​_be​_oout[3:0] logic
    data​_addr​_oout[31:0] logic
    data​_wdata​_oout[31:0] logic
    data​_rdata​_iin[31:0] logic
    data​_err​_iinlogic
    irq​_software​_iinlogic

    Interrupt inputs

    irq​_timer​_iinlogic
    irq​_external​_iinlogic
    irq​_fast​_iin[14:0] logic
    irq​_nm​_iinlogic

    non-maskeable interrupt

    debug​_req​_iinlogic

    Debug Interface

    rvfi​_validoutlogic
    rvfi​_orderout[63:0] logic
    rvfi​_insnout[31:0] logic
    rvfi​_trapoutlogic
    rvfi​_haltoutlogic
    rvfi​_introutlogic
    rvfi​_modeout[1:0] logic
    rvfi​_ixlout[1:0] logic
    rvfi​_rs1​_addrout[4:0] logic
    rvfi​_rs2​_addrout[4:0] logic
    rvfi​_rs3​_addrout[4:0] logic
    rvfi​_rs1​_rdataout[31:0] logic
    rvfi​_rs2​_rdataout[31:0] logic
    rvfi​_rs3​_rdataout[31:0] logic
    rvfi​_rd​_addrout[4:0] logic
    rvfi​_rd​_wdataout[31:0] logic
    rvfi​_pc​_rdataout[31:0] logic
    rvfi​_pc​_wdataout[31:0] logic
    rvfi​_mem​_addrout[31:0] logic
    rvfi​_mem​_rmaskout[3:0] logic
    rvfi​_mem​_wmaskout[3:0] logic
    rvfi​_mem​_rdataout[31:0] logic
    rvfi​_mem​_wdataout[31:0] logic
    fetch​_enable​_iinlogic

    CPU Control Signals

    alert​_minor​_ooutlogic
    alert​_major​_ooutlogic
    core​_sleep​_ooutlogic

    Instantiations

    Block Diagram

    Module ibex​_tracer

    This design unit is implemented in ibex​_tracer.sv

    This file depends on: ibex_tracer_pkg.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    RS1[4:0] logic(1 << 0)

    Data items accessed during this instruction

    RS2[4:0] logic(1 << 1)
    RS3[4:0] logic(1 << 2)
    RD[4:0] logic(1 << 3)
    MEM[4:0] logic(1 << 4)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    hart​_id​_iin[31:0] logic
    rvfi​_validinlogic

    RVFI as described at https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md The standard interface does not have _i/_o suffixes. For consistency with the standard the signals in this module don't have the suffixes either.

    rvfi​_orderin[63:0] logic
    rvfi​_insnin[31:0] logic
    rvfi​_trapinlogic
    rvfi​_haltinlogic
    rvfi​_intrinlogic
    rvfi​_modein[1:0] logic
    rvfi​_ixlin[1:0] logic
    rvfi​_rs1​_addrin[4:0] logic
    rvfi​_rs2​_addrin[4:0] logic
    rvfi​_rs3​_addrin[4:0] logic
    rvfi​_rs1​_rdatain[31:0] logic
    rvfi​_rs2​_rdatain[31:0] logic
    rvfi​_rs3​_rdatain[31:0] logic
    rvfi​_rd​_addrin[4:0] logic
    rvfi​_rd​_wdatain[31:0] logic
    rvfi​_pc​_rdatain[31:0] logic
    rvfi​_pc​_wdatain[31:0] logic
    rvfi​_mem​_addrin[31:0] logic
    rvfi​_mem​_rmaskin[3:0] logic
    rvfi​_mem​_wmaskin[3:0] logic
    rvfi​_mem​_rdatain[31:0] logic
    rvfi​_mem​_wdatain[31:0] logic

    Block Diagram

    Module io​_osc

    This design unit is implemented in io​_osc.sv

    Description

    of io_osc

    Parameters

    NameTypeDefault ValueDescription
    IO​_EN​_RDLYtime5us
    IoClkPeriodreal1000000/96

    ~10416.666667ps (96Mhz)

    Ports

    NameDirectionTypeDescription
    vcore​_pok​_h​_iinlogic

    VCORE POK @3.3V

    io​_en​_iinlogic

    IO Source Clock Enable

    io​_clk​_ooutlogic

    IO Clock Output

    Block Diagram

    Module keymgr​_cfg​_en

    This design unit is implemented in keymgr​_cfg​_en.sv

    Description

    keymgr_cfg_en

    Parameters

    NameTypeDefault ValueDescription
    NonInitClrbit1'b1

    controls whether clear has an effect on output value during non-init

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    init​_iinlogic
    en​_iinlogic
    set​_iinlogic
    clr​_iinlogic
    out​_ooutlogic

    Block Diagram

    Module keymgr​_ctrl

    This design unit is implemented in keymgr​_ctrl.sv

    This file depends on: prim_flop_2sync.sv, uvm_pkg.sv, keymgr_pkg.sv, otp_ctrl_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    EntropyWidthintLfsrWidth / 2
    EntropyRoundsintKeyWidth / EntropyWidth
    CntWidthint$clog2(EntropyRounds)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    en​_iinlogic

    lifecycle enforcement

    op​_start​_iinlogic

    Software interface

    op​_iinkeymgr_ops_e
    op​_done​_ooutlogic
    status​_ooutkeymgr_op_status_e
    error​_oout[ErrLastPos-1:0] logic
    data​_en​_ooutlogic
    data​_valid​_ooutlogic
    wipe​_key​_ooutlogic
    working​_state​_ooutkeymgr_working_state_e
    sw​_binding​_unlock​_ooutlogic
    init​_ooutlogic
    root​_key​_iinotp_keymgr_key_t

    Data input

    hw​_sel​_ooutkeymgr_gen_out_e
    stage​_sel​_ooutkeymgr_stage_e
    adv​_en​_ooutlogic

    KMAC ctrl interface

    id​_en​_ooutlogic
    gen​_en​_ooutlogic
    key​_oouthw_key_req_t
    load​_key​_ooutlogic
    kmac​_done​_iinlogic
    kmac​_input​_invalid​_iinlogic

    asserted when selected data fails criteria check

    kmac​_fsm​_err​_iinlogic

    asserted when kmac fsm reaches unexpected state

    kmac​_op​_err​_iinlogic

    asserted when kmac itself reports an error

    kmac​_cmd​_err​_iinlogic

    asserted when more than one command given to kmac

    kmac​_data​_iin[KeyWidth-1:0] [Shares-1:0] logic
    entropy​_iin[RandWidth-1:0] [Shares-1:0] logic

    prng control interface

    prng​_reseed​_ack​_iinlogic
    prng​_reseed​_req​_ooutlogic
    prng​_en​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module keymgr​_input​_checks

    This design unit is implemented in keymgr​_input​_checks.sv

    This file depends on: keymgr_pkg.sv

    Description

    keymgr_input_checks

    Ports

    NameDirectionTypeDescription
    max​_key​_versions​_iin[31:0] [2**StageWidth-1:0] logic
    stage​_sel​_iinkeymgr_stage_e
    key​_iinhw_key_req_t
    key​_version​_iin[31:0] logic
    creator​_seed​_iin[KeyWidth-1:0] logic
    owner​_seed​_iin[KeyWidth-1:0] logic
    devid​_iin[DevIdWidth-1:0] logic
    health​_state​_iin[HealthStateWidth-1:0] logic
    creator​_seed​_vld​_ooutlogic
    owner​_seed​_vld​_ooutlogic
    devid​_vld​_ooutlogic
    health​_state​_vld​_ooutlogic
    key​_version​_vld​_ooutlogic
    key​_vld​_ooutlogic

    Block Diagram

    Module keymgr​_kmac​_if

    This design unit is implemented in keymgr​_kmac​_if.sv

    This file depends on: uvm_pkg.sv, keymgr_pkg.sv

    Description

    keymgr_kmac_if

    Parameters

    NameTypeDefault ValueDescription
    AdvRemintAdvDataWidth % KmacDataIfWidth
    IdRemintIdDataWidth % KmacDataIfWidth
    GenRemintGenDataWidth % KmacDataIfWidth
    AdvRoundsintAdvDataWidth / KmacDataIfWidth + (AdvRem > 0)

    Number of kmac transactions required

    IdRoundsintIdDataWidth / KmacDataIfWidth + (IdRem > 0)
    GenRoundsintGenDataWidth / KmacDataIfWidth + (GenRem > 0)
    MaxRoundsintKDFMaxWidth / KmacDataIfWidth
    AdvWidthintKmacDataIfWidth * AdvRounds

    Total transmitted bits, this is the same as *DataWidth if it all fits into kmac data interface

    IdWidthintKmacDataIfWidth * IdRounds
    GenWidthintKmacDataIfWidth * GenRounds
    CntWidthint$clog2(MaxRounds)

    calculated parameters for number of roudns and interface width

    IfBytesintKmacDataIfWidth / 8
    DecoyCopiesintKmacDataIfWidth / 32
    DecoyOutputCopiesint(KeyWidth / 32) * Shares
    AdvByteMask[IfBytes-1:0] logic(AdvRem > 0) ? (2**(AdvRem/8)-1) : {IfBytes{1'b1}}

    byte mask for the last transfer

    IdByteMask[IfBytes-1:0] logic(IdRem > 0) ? (2**(IdRem/8)-1) : {IfBytes{1'b1}}
    GenByteMask[IfBytes-1:0] logic(GenRem > 0) ? (2**(GenRem/8)-1) : {IfBytes{1'b1}}

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    adv​_data​_iin[AdvDataWidth-1:0] logic

    data input interfaces

    id​_data​_iin[IdDataWidth-1:0] logic
    gen​_data​_iin[GenDataWidth-1:0] logic
    inputs​_invalid​_iin[3:0] logic
    inputs​_invalid​_ooutlogic
    adv​_en​_iinlogic

    keymgr control to select appropriate inputs

    id​_en​_iinlogic
    gen​_en​_iinlogic
    done​_ooutlogic
    data​_oout[KeyWidth-1:0] [Shares-1:0] logic
    kmac​_data​_ooutkmac_data_req_t

    actual connection to kmac

    kmac​_data​_iinkmac_data_rsp_t
    prng​_en​_ooutlogic

    entropy input

    entropy​_iin[RandWidth-1:0] [Shares-1:0] logic
    fsm​_error​_ooutlogic

    error outputs

    kmac​_error​_ooutlogic
    cmd​_error​_ooutlogic

    Block Diagram

    State Machines

    Package keymgr​_reg​_pkg

    This design unit is implemented in keymgr​_reg​_pkg.sv

    Module keymgr​_reg​_top

    This design unit is implemented in keymgr​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, keymgr_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint8
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutkeymgr_reg2hw_t

    Write

    hw2reginkeymgr_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module keymgr​_reseed​_ctrl

    This design unit is implemented in keymgr​_reseed​_ctrl.sv

    This file depends on: keymgr_pkg.sv, prim_sync_reqack.sv, prim_util_pkg.sv, edn_pkg.sv

    Description

    keymgr_reseed_ctrl

    Parameters

    NameTypeDefault ValueDescription
    EdnRoundsintLfsrWidth / EdnWidth
    EdnCntWidthintprim_util_pkg::vbits(EdnRounds)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    clk​_edn​_iinlogic
    rst​_edn​_niinlogic
    reseed​_req​_iinlogic

    interface to keymgr_ctrl

    reseed​_ack​_ooutlogic
    reseed​_interval​_iin[15:0] logic

    interface to software

    edn​_ooutedn_req_t

    interface to edn

    edn​_iinedn_rsp_t
    seed​_en​_ooutlogic

    interface to lfsr

    seed​_oout[LfsrWidth-1:0] logic

    Instantiations

    Block Diagram

    Module keymgr​_sideload​_key​_ctrl

    This design unit is implemented in keymgr​_sideload​_key​_ctrl.sv

    This file depends on: keymgr_sideload_key.sv, uvm_pkg.sv, keymgr_pkg.sv

    Description

    keymgr_sideload_key_ctrl

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    init​_iinlogic
    clr​_key​_iinlogic

    clear key just deletes the key

    wipe​_key​_iinlogic

    wipe key deletes and renders sideloads useless until reboot

    entropy​_iin[RandWidth-1:0] [Shares-1:0] logic
    dest​_sel​_iinkeymgr_key_dest_e
    key​_sel​_iinkeymgr_gen_out_e
    load​_key​_iinlogic
    data​_en​_iinlogic
    data​_valid​_iinlogic
    key​_iinhw_key_req_t
    data​_iin[KeyWidth-1:0] [Shares-1:0] logic
    prng​_en​_ooutlogic
    aes​_key​_oouthw_key_req_t
    hmac​_key​_oouthw_key_req_t
    kmac​_key​_oouthw_key_req_t

    Instantiations

    Block Diagram

    State Machines

    Module kmac​_core

    This design unit is implemented in kmac​_core.sv

    This file depends on: prim_slicer.sv, kmac_pkg.sv, uvm_pkg.sv, sha3_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    EnMaskingbit0

    EnMasking: Enable masking security hardening inside keccak_round If it is enabled, the result digest will be two set of 1600bit.

    Shareint(EnMasking) ? 2 : 1

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    fifo​_valid​_iinlogic

    From Message FIFO

    fifo​_data​_iin[MsgWidth-1:0] logic [Share]
    fifo​_strb​_iin[MsgStrbW-1:0] logic
    fifo​_ready​_ooutlogic
    msg​_valid​_ooutlogic

    to SHA3 Core

    msg​_data​_oout[MsgWidth-1:0] logic [Share]
    msg​_strb​_oout[MsgStrbW-1:0] logic
    msg​_ready​_iinlogic
    kmac​_en​_iinlogic

    If kmac_en is cleared, Core logic doesn't function but forward incoming mesage to SHA3 core

    mode​_iinsha3_mode_e
    strength​_iinkeccak_strength_e
    key​_data​_iin[MaxKeyLen-1:0] logic [Share]

    Key input from CSR

    key​_len​_iinkey_len_e
    start​_iinlogic

    Controls : same to SHA3 core

    process​_iinlogic
    done​_iinlogic
    process​_ooutlogic

    Control to SHA3 core

    Block Diagram

    State Machines

    Module kmac​_entropy

    This design unit is implemented in kmac​_entropy.sv

    This file depends on: kmac_pkg.sv, uvm_pkg.sv, sha3_pkg.sv, prim_lfsr.sv

    Parameters

    NameTypeDefault ValueDescription
    EntropyLfsrWint64

    storage width

    EntropyStorageWint320
    EntropyMultiplyintsha3_pkg::StateW / EntropyStorageW
    StorageEntriesintEntropyStorageW / EntropyLfsrW
    StorageIndexWint$clog2(StorageEntries)
    TimerWint(EntropyTimerW > EdnWaitTimerW) ? EntropyTimerW : EdnWaitTimerW

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    entropy​_req​_ooutlogic

    EDN interface

    entropy​_ack​_iinlogic
    entropy​_data​_iin[MsgWidth-1:0] logic
    rand​_valid​_ooutlogic

    Entropy to internal

    rand​_data​_oout[sha3_pkg::StateW-1:0] logic
    rand​_consumed​_iinlogic
    in​_progress​_iinlogic

    Status

    in​_keyblock​_iinlogic
    mode​_iinentropy_mode_e

    Configurations

    entropy​_ready​_iinlogic

    // SW sets ready bit when EDN is ready to accept requests through its app. // interface.

    fast​_process​_iinlogic

    // Garbage random value when not processing Keyblock, if this config is // turned on, the logic sending garbage value and never de-assert // rand_valid_o unless it is not processing KeyBlock.

    seed​_update​_iinlogic

    // SW update of seed

    seed​_data​_iin[63:0] logic
    entropy​_timer​_limit​_iin[EntropyTimerW-1:0] logic

    // Timer limit value // If value is 0, timer is disabled

    wait​_timer​_limit​_iin[EdnWaitTimerW-1:0] logic
    err​_oouterr_t

    Error output

    err​_processed​_iinlogic

    Instantiations

    Block Diagram

    State Machines

    Module kmac​_keymgr

    This design unit is implemented in kmac​_keymgr.sv

    This file depends on: kmac_pkg.sv, uvm_pkg.sv, sha3_pkg.sv, keymgr_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    EnMaskingint0
    Shareint(EnMasking) ? 2 : 1

    derived parameter

    KeyMgrKeyWint$bits(keymgr_key_i.key_share0)

    Digest width is same to the key width keymgr_pkg::KeyWidth.

    KeyMgrDigestWint$bits(keymgr_data_o.digest_share0)
    KeyLenkey_len_e [5]'{Key128, Key192, Key256, Key384, Key512}
    SelKeySizeint(KeyMgrDigestW == 128) ? 0 : (KeyMgrDigestW == 192) ? 1 : (KeyMgrDigestW == 256) ? 2 : (KeyMgrDigestW == 384) ? 3 : (KeyMgrDigestW == 512) ? 4 : 0
    SideloadedKeykey_len_eKeyLen[SelKeySize]
    OutLenWint24

    Define right_encode(outlen) value here Look at kmac_pkg::key_len_e for the kinds of key size

    These values should be exactly the same as the key length encodings in kmac_core.sv, with the only difference being that the byte representing the byte-length of the encoded value is in the MSB position due to right encoding instead of in the LSB position (left encoding).

    EncodedOutLen[OutLenW-1:0] logic [5]'{ 24'h 0001_80, 24'h 0001_C0, 24'h 02_0001, 24'h 02_8001, 24'h 02_0002 }
    EncodedOutLenMask[OutLenW-1:0] logic [5]'{ 24'h 00FFFF, 24'h 00FFFF, 24'h FFFFFF, 24'h FFFFFF, 24'h FFFFFF }

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    reg​_key​_data​_iin[MaxKeyLen-1:0] logic [Share]

    Secret Key from register

    reg​_key​_len​_iinkey_len_e
    sw​_valid​_iinlogic

    Data from Software

    sw​_data​_iin[MsgWidth-1:0] logic
    sw​_mask​_iin[MsgWidth-1:0] logic
    sw​_ready​_ooutlogic
    keymgr​_key​_iinhw_key_req_t

    KeyMgr Sideload Key interface

    keymgr​_data​_iinkmac_data_req_t

    KeyMgr Data in/ Digest out interface + control signals

    keymgr​_data​_ooutkmac_data_rsp_t
    key​_data​_oout[MaxKeyLen-1:0] logic [Share]

    to KMAC Core: Secret key

    key​_len​_ooutkey_len_e
    kmac​_valid​_ooutlogic

    to MSG_FIFO

    kmac​_data​_oout[MsgWidth-1:0] logic
    kmac​_mask​_oout[MsgWidth-1:0] logic
    kmac​_ready​_iinlogic
    keccak​_state​_valid​_iinlogic

    STATE from SHA3 Core

    keccak​_state​_iin[sha3_pkg::StateW-1:0] logic [Share]
    reg​_state​_valid​_ooutlogic

    to STATE TL-window if KeyMgr KDF is not enabled, the incoming state goes to register if kdf_en is set, the state value goes to KeyMgr and the output to the register is all zero.

    reg​_state​_oout[sha3_pkg::StateW-1:0] logic [Share]
    keymgr​_key​_en​_iinlogic

    Configurations If key_en is set, the logic uses KeyMgr's sideloaded key as a secret key rather than register values. This only affects when software initiates. If KeyMgr initiates the hash operation, it always uses sideloaded key.

    sw​_cmd​_iinkmac_cmd_e

    Commands Command from software

    absorbed​_iinlogic

    from SHA3

    cmd​_ooutkmac_cmd_e

    to KMAC

    absorbed​_ooutlogic

    to SW

    error​_iinlogic

    Error input This error comes from KMAC/SHA3 engine. KeyMgr interface delivers the error signal to KeyMgr to drop the current op and re-initiate. If error happens, regardless of SW-initiated or KeyMgr-initiated, the error is reported to the ERR_CODE so that SW can look into.

    error​_oouterr_t

    error_o value is pushed to Error FIFO at KMAC/SHA3 top and reported to SW

    Block Diagram

    State Machines

    Module kmac​_msgfifo

    This design unit is implemented in kmac​_msgfifo.sv

    This file depends on: kmac_pkg.sv, uvm_pkg.sv, prim_fifo_sync.sv, prim_packer.sv

    Parameters

    NameTypeDefault ValueDescription
    OutWidthint64

    OutWidth is MsgFIFO data width. prim_packer converts InW to OutW prior to pushing to MsgFIFO

    MsgDepthint9

    Internal MsgFIFO Entry count

    MsgDepthWint$clog2(MsgDepth+1)

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    fifo​_valid​_iinlogic

    from REG or KeyMgr Intf input

    fifo​_data​_iin[OutWidth-1:0] logic
    fifo​_mask​_iin[OutWidth-1:0] logic
    fifo​_ready​_ooutlogic
    msg​_valid​_ooutlogic

    MSG interface

    msg​_data​_oout[OutWidth-1:0] logic
    msg​_strb​_oout[OutWidth/8-1:0] logic
    msg​_ready​_iinlogic
    fifo​_empty​_ooutlogic
    fifo​_full​_ooutlogic
    fifo​_depth​_oout[MsgDepthW-1:0] logic
    clear​_iinlogic

    Control

    process​_iinlogic

    process_i --> process_o process_o asserted after all internal messages are flushed out to MSG interface

    process​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Package kmac​_pkg

    This design unit is implemented in kmac​_pkg.sv

    This file depends on: sha3_pkg.sv

    Package kmac​_reg​_pkg

    This design unit is implemented in kmac​_reg​_pkg.sv

    Module kmac​_reg​_top

    This design unit is implemented in kmac​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, kmac_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint12
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    tl​_win​_oouttl_h2d_t [2]

    Output port for window

    tl​_win​_iintl_d2h_t [2]
    reg2hwoutkmac_reg2hw_t

    Write

    hw2reginkmac_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module kmac​_staterd

    This design unit is implemented in kmac​_staterd.sv

    This file depends on: tlul_adapter_sram.sv, prim_slicer.sv, kmac_pkg.sv, sha3_pkg.sv, tlul_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    AddrWint9

    TL-UL Address Width. Should be bigger than $clog2(kmac_pkg::StateW) * Share

    EnMaskingint0

    EnMasking: Enable masking security hardening inside keccak_round If it is enabled, the result digest will be two set of 1600bit.

    Shareint(EnMasking) ? 2 : 1

    derived parameter

    StateAddrWint$clog2(sha3_pkg::StateW/32)
    SelAddrWintAddrW-2-StateAddrW

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t
    tl​_oouttl_d2h_t
    state​_iin[sha3_pkg::StateW-1:0] logic [Share]

    State in

    endian​_swap​_iinlogic

    Config

    Instantiations

    Block Diagram

    Module lc​_ctrl​_fsm

    This design unit is implemented in lc​_ctrl​_fsm.sv

    This file depends on: prim_flop.sv, prim_lc_sender.sv, uvm_pkg.sv, lc_ctrl_state_pkg.sv, lc_ctrl_state_transition.sv, lc_ctrl_signal_decode.sv, lc_ctrl_pkg.sv, lc_ctrl_state_decode.sv

    Parameters

    NameTypeDefault ValueDescription
    RndCnstLcKeymgrDivInvalidlc_keymgr_div_tLcKeymgrDivWidth'(0)
    RndCnstLcKeymgrDivTestDevRmalc_keymgr_div_tLcKeymgrDivWidth'(1)
    RndCnstLcKeymgrDivProductionlc_keymgr_div_tLcKeymgrDivWidth'(2)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    This module is combinational, but we need the clock and reset for the assertions.

    rst​_niinlogic
    init​_req​_iinlogic

    Initialization request from power manager.

    init​_done​_ooutlogic
    idle​_ooutlogic
    esc​_scrap​_state​_iinlogic

    Escalatio input

    esc​_wipe​_secrets​_iinlogic
    lc​_state​_valid​_iinlogic

    Life cycle state vector from OTP.

    lc​_state​_iinlc_state_e
    lc​_id​_state​_iinlc_id_state_e
    lc​_cnt​_iinlc_cnt_e
    test​_unlock​_token​_iinlc_token_t

    Token input from OTP (these are all hash post-images).

    test​_exit​_token​_iinlc_token_t
    rma​_token​_iinlc_token_t
    trans​_cmd​_iinlogic

    Transition trigger interface.

    trans​_target​_iindec_lc_state_e
    dec​_lc​_state​_ooutdec_lc_state_e

    Decoded life cycle state for CSRs.

    dec​_lc​_cnt​_ooutdec_lc_cnt_t
    dec​_lc​_id​_state​_ooutdec_lc_id_state_e
    token​_hash​_req​_ooutlogic

    Token hashing interface

    token​_hash​_ack​_iinlogic
    hashed​_token​_iinlc_token_t
    otp​_prog​_req​_ooutlogic

    OTP programming interface

    otp​_prog​_lc​_state​_ooutlc_state_e
    otp​_prog​_lc​_cnt​_ooutlc_cnt_e
    otp​_prog​_ack​_iinlogic
    otp​_prog​_err​_iinlogic
    trans​_success​_ooutlogic

    Error outputs going to CSRs

    trans​_cnt​_oflw​_error​_ooutlogic
    trans​_invalid​_error​_ooutlogic
    token​_invalid​_error​_ooutlogic
    flash​_rma​_error​_ooutlogic
    otp​_prog​_error​_ooutlogic
    state​_invalid​_error​_ooutlogic
    lc​_dft​_en​_ooutlc_tx_t

    Life cycle broadcast outputs.

    lc​_nvm​_debug​_en​_ooutlc_tx_t
    lc​_hw​_debug​_en​_ooutlc_tx_t
    lc​_cpu​_en​_ooutlc_tx_t
    lc​_creator​_seed​_sw​_rw​_en​_ooutlc_tx_t
    lc​_owner​_seed​_sw​_rw​_en​_ooutlc_tx_t
    lc​_iso​_part​_sw​_rd​_en​_ooutlc_tx_t
    lc​_iso​_part​_sw​_wr​_en​_ooutlc_tx_t
    lc​_seed​_hw​_rd​_en​_ooutlc_tx_t
    lc​_keymgr​_en​_ooutlc_tx_t
    lc​_escalate​_en​_ooutlc_tx_t
    lc​_check​_byp​_en​_ooutlc_tx_t
    lc​_clk​_byp​_req​_ooutlc_tx_t
    lc​_clk​_byp​_ack​_iinlc_tx_t
    lc​_flash​_rma​_req​_ooutlc_tx_t

    Request and feedback to/from flash controller

    lc​_flash​_rma​_ack​_iinlc_tx_t
    lc​_keymgr​_div​_ooutlc_keymgr_div_t

    State group diversification value for keymgr

    Instantiations

    Block Diagram

    State Machines

    Package lc​_ctrl​_reg​_pkg

    This design unit is implemented in lc​_ctrl​_reg​_pkg.sv

    Module lc​_ctrl​_reg​_top

    This design unit is implemented in lc​_ctrl​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, lc_ctrl_reg_pkg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint7
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutlc_ctrl_reg2hw_t

    Write

    hw2reginlc_ctrl_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module otbn​_core

    This design unit is implemented in otbn​_core.sv

    This file depends on: otbn_decoder.sv, otbn_controller.sv, otbn_rf_base.sv, otbn_mac_bignum.sv, otbn_rf_bignum_fpga.sv, otbn_instruction_fetch.sv, prim_util_pkg.sv, otbn_alu_bignum.sv, otbn_lsu.sv, otbn_rf_bignum_ff.sv, otbn_pkg.sv, otbn_alu_base.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    RegFileregfile_eRegFileFF

    Register file implementation selection, see otbn_pkg.sv.

    ImemSizeByteint4096

    Size of the instruction memory, in bytes

    DmemSizeByteint4096

    Size of the data memory, in bytes

    ImemAddrWidthintprim_util_pkg::vbits(ImemSizeByte)
    DmemAddrWidthintprim_util_pkg::vbits(DmemSizeByte)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    start​_iinlogic

    start the operation

    done​_ooutlogic

    operation done

    err​_bits​_oouterr_bits_t

    valid when done_o is asserted

    start​_addr​_iin[ImemAddrWidth-1:0] logic

    start byte address in IMEM

    imem​_req​_ooutlogic

    Instruction memory (IMEM)

    imem​_addr​_oout[ImemAddrWidth-1:0] logic
    imem​_wdata​_oout[31:0] logic
    imem​_rdata​_iin[31:0] logic
    imem​_rvalid​_iinlogic
    imem​_rerror​_iinlogic
    dmem​_req​_ooutlogic

    Data memory (DMEM)

    dmem​_write​_ooutlogic
    dmem​_addr​_oout[DmemAddrWidth-1:0] logic
    dmem​_wdata​_oout[WLEN-1:0] logic
    dmem​_wmask​_oout[WLEN-1:0] logic
    dmem​_rdata​_iin[WLEN-1:0] logic
    dmem​_rvalid​_iinlogic
    dmem​_rerror​_iinlogic
    edn​_req​_ooutlogic

    Entropy distribution network (EDN)

    edn​_ack​_iinlogic
    edn​_data​_iin[EdnDataWidth-1:0] logic

    Instantiations

    Block Diagram

    Package otbn​_reg​_pkg

    This design unit is implemented in otbn​_reg​_pkg.sv

    Module otbn​_reg​_top

    This design unit is implemented in otbn​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, otbn_reg_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint16
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    tl​_win​_oouttl_h2d_t [2]

    Output port for window

    tl​_win​_iintl_d2h_t [2]
    reg2hwoutotbn_reg2hw_t

    Write

    hw2reginotbn_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module otp​_ctrl​_dai

    This design unit is implemented in otp​_ctrl​_dai.sv

    This file depends on: prim_flop.sv, uvm_pkg.sv, prim_arbiter_fixed.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, otp_ctrl_reg_pkg.sv, prim_otp_pkg.sv, prim_util_pkg.sv, lc_ctrl_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    CntWidthintOtpByteAddrWidth - $clog2(ScrmblBlockWidth/8)
    StateWidthint12

    Encoding generated with ./sparse-fsm-encode.py -d 5 -m 20 -n 12 -s 3011551511 Hamming distance histogram:

    0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||| (32.11%) 6: |||||||||||||||||||| (35.26%) 7: |||||||| (15.79%) 8: |||||| (11.58%) 9: | (2.11%) 10: (1.05%) 11: | (2.11%) 12: --

    Minimum Hamming distance: 5 Maximum Hamming distance: 11

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    init​_req​_iinlogic

    Init reqest from power manager

    init​_done​_ooutlogic
    part​_init​_req​_ooutlogic

    Init request going to partitions

    part​_init​_done​_iin[NumPart-1:0] logic
    escalate​_en​_iinlc_tx_t

    Escalation input. This moves the FSM into a terminal state and locks down the DAI.

    error​_ooutotp_err_e

    Output error state of DAI, to be consumed by OTP error/alert logic. Note that most errors are not recoverable and move the DAI FSM into a terminal error state.

    part​_access​_iin[NumPart-1:0] part_access_t

    Access/lock status from partitions

    dai​_addr​_iin[OtpByteAddrWidth-1:0] logic

    CSR interface

    dai​_cmd​_iindai_cmd_e
    dai​_req​_iinlogic
    dai​_wdata​_iin[31:0] [NumDaiWords-1:0] logic
    dai​_idle​_ooutlogic

    wired to the status CSRs

    dai​_prog​_idle​_ooutlogic

    wired to lfsr timer and pwrmgr

    dai​_cmd​_done​_ooutlogic

    this is used to raise an IRQ

    dai​_rdata​_oout[31:0] [NumDaiWords-1:0] logic
    otp​_req​_ooutlogic

    OTP interface

    otp​_cmd​_ooutcmd_e
    otp​_size​_oout[OtpSizeWidth-1:0] logic
    otp​_wdata​_oout[OtpIfWidth-1:0] logic
    otp​_addr​_oout[OtpAddrWidth-1:0] logic
    otp​_gnt​_iinlogic
    otp​_rvalid​_iinlogic
    otp​_rdata​_iin[ScrmblBlockWidth-1:0] logic
    otp​_err​_iinerr_e
    scrmbl​_mtx​_req​_ooutlogic

    Scrambling mutex request

    scrmbl​_mtx​_gnt​_iinlogic
    scrmbl​_cmd​_ooutotp_scrmbl_cmd_e

    Scrambling datapath interface

    scrmbl​_mode​_ooutdigest_mode_e
    scrmbl​_sel​_oout[ConstSelWidth-1:0] logic
    scrmbl​_data​_oout[ScrmblBlockWidth-1:0] logic
    scrmbl​_valid​_ooutlogic
    scrmbl​_ready​_iinlogic
    scrmbl​_valid​_iinlogic
    scrmbl​_data​_iin[ScrmblBlockWidth-1:0] logic

    Instantiations

    Block Diagram

    State Machines

    Module otp​_ctrl​_kdi

    This design unit is implemented in otp​_ctrl​_kdi.sv

    This file depends on: prim_flop.sv, uvm_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, otp_ctrl_reg_pkg.sv, prim_util_pkg.sv, lc_ctrl_pkg.sv, prim_arbiter_tree.sv

    Parameters

    NameTypeDefault ValueDescription
    NumReqint4 + NumSramKeyReqSlots

    LC, 2xFlash, OTBN + SRAM slots

    StateWidthint10

    Encoding generated with: $ ./sparse-fsm-encode.py -d 5 -m 11 -n 10
    -s 2544133835 --language=sv

    Hamming distance histogram:

    0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (54.55%) 6: |||||||||||||||| (45.45%) 7: -- 8: -- 9: -- 10: --

    Minimum Hamming distance: 5 Maximum Hamming distance: 6

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    kdi​_en​_iinlogic

    Pulse to enable this module after OTP partitions have been initialized.

    escalate​_en​_iinlc_tx_t

    Escalation input. This moves the FSM into a terminal state.

    fsm​_err​_ooutlogic

    FSM is in error state

    scrmbl​_key​_seed​_valid​_iinlogic

    Key seed inputs from OTP

    flash​_data​_key​_seed​_iin[FlashKeySeedWidth-1:0] logic
    flash​_addr​_key​_seed​_iin[FlashKeySeedWidth-1:0] logic
    sram​_data​_key​_seed​_iin[SramKeySeedWidth-1:0] logic
    edn​_req​_ooutlogic

    EDN interface for requesting entropy

    edn​_ack​_iinlogic
    edn​_data​_iin[EdnDataWidth-1:0] logic
    lc​_otp​_token​_iinlc_otp_token_req_t

    Lifecycle hashing request

    lc​_otp​_token​_ooutlc_otp_token_rsp_t
    flash​_otp​_key​_iinflash_otp_key_req_t

    Scrambling key requests

    flash​_otp​_key​_ooutflash_otp_key_rsp_t
    sram​_otp​_key​_iin[NumSramKeyReqSlots-1:0] sram_otp_key_req_t
    sram​_otp​_key​_oout[NumSramKeyReqSlots-1:0] sram_otp_key_rsp_t
    otbn​_otp​_key​_iinotbn_otp_key_req_t
    otbn​_otp​_key​_ooutotbn_otp_key_rsp_t
    scrmbl​_mtx​_req​_ooutlogic

    Scrambling mutex request

    scrmbl​_mtx​_gnt​_iinlogic
    scrmbl​_cmd​_ooutotp_scrmbl_cmd_e

    Scrambling datapath interface

    scrmbl​_mode​_ooutdigest_mode_e
    scrmbl​_sel​_oout[ConstSelWidth-1:0] logic
    scrmbl​_data​_oout[ScrmblBlockWidth-1:0] logic
    scrmbl​_valid​_ooutlogic
    scrmbl​_ready​_iinlogic
    scrmbl​_valid​_iinlogic
    scrmbl​_data​_iin[ScrmblBlockWidth-1:0] logic

    Instantiations

    Block Diagram

    State Machines

    Module otp​_ctrl​_lci

    This design unit is implemented in otp​_ctrl​_lci.sv

    This file depends on: prim_flop.sv, uvm_pkg.sv, lc_ctrl_state_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, otp_ctrl_reg_pkg.sv, prim_otp_pkg.sv, prim_util_pkg.sv, lc_ctrl_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Infopart_info_tpart_info_t'(0)

    Lifecycle partition information

    NumLcOtpWordsintInfo.size >> OtpAddrShift
    CntWidthintvbits(NumLcOtpWords)
    StateWidthint9

    Encoding generated with ./sparse-fsm-encode.py -d 5 -m 5 -n 9 -s 558234734 Hamming distance histogram:

    0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (60.00%) 6: ||||||||||||| (40.00%) 7: -- 8: -- 9: --

    Minimum Hamming distance: 5 Maximum Hamming distance: 6

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    lci​_en​_iinlogic
    escalate​_en​_iinlc_tx_t

    Escalation input. This moves the FSM into a terminal state and locks down the partition.

    lc​_req​_iinlogic

    Life cycle transition request. In order to perform a state transition, the LC controller signals the new count and state. The OTP wrapper then only programs bits that have not been programmed before. Note that a transition request will fail if the request attempts to clear already programmed bits within OTP.

    lc​_state​_iinlc_state_e
    lc​_count​_iinlc_cnt_e
    lc​_ack​_ooutlogic
    lc​_err​_ooutlogic
    error​_ooutotp_err_e

    Output error state of partition, to be consumed by OTP error/alert logic. Note that most errors are not recoverable and move the partition FSM into a terminal error state.

    lci​_prog​_idle​_ooutlogic
    otp​_req​_ooutlogic

    OTP interface

    otp​_cmd​_ooutcmd_e
    otp​_size​_oout[OtpSizeWidth-1:0] logic
    otp​_wdata​_oout[OtpIfWidth-1:0] logic
    otp​_addr​_oout[OtpAddrWidth-1:0] logic
    otp​_gnt​_iinlogic
    otp​_rvalid​_iinlogic
    otp​_rdata​_iin[ScrmblBlockWidth-1:0] logic
    otp​_err​_iinerr_e

    Instantiations

    Block Diagram

    State Machines

    Module otp​_ctrl​_lfsr​_timer

    This design unit is implemented in otp​_ctrl​_lfsr​_timer.sv

    This file depends on: prim_flop.sv, uvm_pkg.sv, prim_lfsr.sv, otp_ctrl_pkg.sv, otp_ctrl_reg_pkg.sv, lc_ctrl_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    ReseedLfsrWidthint16

    Entropy reseeding is triggered every time this counter expires.

    RndCnstLfsrSeedlfsr_seed_tRndCnstLfsrSeedDefault

    Compile time random constants, to be overriden by topgen.

    RndCnstLfsrPermlfsr_perm_tRndCnstLfsrPermDefault
    StateWidthint9

    Encoding generated with ./sparse-fsm-encode.py -d 5 -m 5 -n 9 -s 628816752 Hamming distance histogram:

    0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (60.00%) 6: ||||||||||||| (40.00%) 7: -- 8: -- 9: --

    Minimum Hamming distance: 5 Maximum Hamming distance: 6

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    edn​_req​_ooutlogic

    request to EDN

    edn​_ack​_iinlogic

    ack from EDN

    edn​_data​_iin[EdnDataWidth-1:0] logic

    from EDN

    timer​_en​_iinlogic

    enable timer

    otp​_prog​_busy​_iinlogic

    indicates whether prog ops are in progress

    integ​_chk​_trig​_iinlogic

    one-off trigger for integrity check

    cnsty​_chk​_trig​_iinlogic

    one-off trigger for consistency check

    chk​_pending​_ooutlogic

    indicates whether there are pending checks

    timeout​_iin[31:0] logic

    check timeout

    integ​_period​_msk​_iin[31:0] logic

    maximum integrity check mask

    cnsty​_period​_msk​_iin[31:0] logic

    maximum consistency check mask

    integ​_chk​_req​_oout[NumPart-1:0] logic

    request to all partitions

    cnsty​_chk​_req​_oout[NumPart-1:0] logic

    request to all partitions

    integ​_chk​_ack​_iin[NumPart-1:0] logic

    response from partitions

    cnsty​_chk​_ack​_iin[NumPart-1:0] logic

    response from partitions

    escalate​_en​_iinlc_tx_t

    escalation input, moves FSM into ErrorSt

    chk​_timeout​_ooutlogic

    a check has timed out

    fsm​_err​_ooutlogic

    the FSM has reached an invalid state

    Instantiations

    Block Diagram

    State Machines

    Module otp​_ctrl​_part​_buf

    This design unit is implemented in otp​_ctrl​_part​_buf.sv

    This file depends on: prim_flop.sv, uvm_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, otp_ctrl_reg_pkg.sv, prim_otp_pkg.sv, prim_util_pkg.sv, prim_buf.sv, lc_ctrl_pkg.sv, otp_ctrl_ecc_reg.sv

    Parameters

    NameTypeDefault ValueDescription
    Infopart_info_tpart_info_t'(0)

    Partition information.

    DataDefault[Info.size*8-1:0] logic'0
    DigestOffsetintInfo.offset + Info.size - ScrmblBlockWidth/8
    NumScrmblBlocksintInfo.size / (ScrmblBlockWidth/8)
    CntWidthintvbits(NumScrmblBlocks)
    StateWidthint12

    Encoding generated with ./sparse-fsm-encode.py -d 5 -m 16 -n 12 -s 3370657881 Hamming distance histogram:

    0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||| (30.00%) 6: |||||||||||||||||||| (32.50%) 7: ||||||||||| (19.17%) 8: ||||||| (11.67%) 9: || (4.17%) 10: | (2.50%) 11: -- 12: --

    Minimum Hamming distance: 5 Maximum Hamming distance: 10

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    init​_req​_iinlogic

    Pulse to start partition initialisation (required once per power cycle).

    init​_done​_ooutlogic
    integ​_chk​_req​_iinlogic

    Integrity check requests

    integ​_chk​_ack​_ooutlogic
    cnsty​_chk​_req​_iinlogic

    Consistency check requests

    cnsty​_chk​_ack​_ooutlogic
    escalate​_en​_iinlc_tx_t

    Escalation input. This moves the FSM into a terminal state and locks down the partition.

    check​_byp​_en​_iinlc_tx_t

    Check bypass enable. This bypasses integrity and consistency checks and acknowledges all incoming check requests (only used by life cycle).

    error​_ooutotp_err_e

    Output error state of partition, to be consumed by OTP error/alert logic. Note that most errors are not recoverable and move the partition FSM into a terminal error state.

    access​_iinpart_access_t

    runtime lock from CSRs

    access​_ooutpart_access_t
    digest​_oout[ScrmblBlockWidth-1:0] logic

    Buffered 64bit digest output.

    data​_oout[Info.size*8-1:0] logic
    otp​_req​_ooutlogic

    OTP interface

    otp​_cmd​_ooutcmd_e
    otp​_size​_oout[OtpSizeWidth-1:0] logic
    otp​_wdata​_oout[OtpIfWidth-1:0] logic
    otp​_addr​_oout[OtpAddrWidth-1:0] logic
    otp​_gnt​_iinlogic
    otp​_rvalid​_iinlogic
    otp​_rdata​_iin[ScrmblBlockWidth-1:0] logic
    otp​_err​_iinerr_e
    scrmbl​_mtx​_req​_ooutlogic

    Scrambling mutex request

    scrmbl​_mtx​_gnt​_iinlogic
    scrmbl​_cmd​_ooutotp_scrmbl_cmd_e

    Scrambling datapath interface

    scrmbl​_mode​_ooutdigest_mode_e
    scrmbl​_sel​_oout[ConstSelWidth-1:0] logic
    scrmbl​_data​_oout[ScrmblBlockWidth-1:0] logic
    scrmbl​_valid​_ooutlogic
    scrmbl​_ready​_iinlogic
    scrmbl​_valid​_iinlogic
    scrmbl​_data​_iin[ScrmblBlockWidth-1:0] logic

    Instantiations

    Block Diagram

    State Machines

    Module otp​_ctrl​_part​_unbuf

    This design unit is implemented in otp​_ctrl​_part​_unbuf.sv

    This file depends on: prim_flop.sv, uvm_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, otp_ctrl_reg_pkg.sv, prim_otp_pkg.sv, prim_util_pkg.sv, prim_buf.sv, lc_ctrl_pkg.sv, otp_ctrl_ecc_reg.sv

    Parameters

    NameTypeDefault ValueDescription
    Infopart_info_tpart_info_t'(0)

    Partition information.

    PartEnd[OtpByteAddrWidth:0] logic(OtpByteAddrWidth+1)'(Info.offset) + (OtpByteAddrWidth+1)'(Info.size)
    DigestOffsetint(Info.offset + (Info.size - (ScrmblBlockWidth/8)))
    StateWidthint10

    Encoding generated with ./sparse-fsm-encode.py -d 5 -m 7 -n 10 -s 4247417884 Hamming distance histogram:

    0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (52.38%) 6: |||||||||||||| (38.10%) 7: | (4.76%) 8: | (4.76%) 9: -- 10: --

    Minimum Hamming distance: 5 Maximum Hamming distance: 8

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    init​_req​_iinlogic

    Pulse to start partition initialisation (required once per power cycle).

    init​_done​_ooutlogic
    escalate​_en​_iinlc_tx_t

    Escalation input. This moves the FSM into a terminal state and locks down the partition.

    error​_ooutotp_err_e

    Output error state of partition, to be consumed by OTP error/alert logic. Note that most errors are not recoverable and move the partition FSM into a terminal error state.

    access​_iinpart_access_t

    runtime lock from CSRs

    access​_ooutpart_access_t
    digest​_oout[ScrmblBlockWidth-1:0] logic

    Buffered 64bit digest output.

    tlul​_req​_iinlogic

    Interface to TL-UL adapter

    tlul​_gnt​_ooutlogic
    tlul​_addr​_iin[SwWindowAddrWidth-1:0] logic
    tlul​_rerror​_oout[1:0] logic
    tlul​_rvalid​_ooutlogic
    tlul​_rdata​_oout[31:0] logic
    otp​_req​_ooutlogic

    OTP interface

    otp​_cmd​_ooutcmd_e
    otp​_size​_oout[OtpSizeWidth-1:0] logic
    otp​_wdata​_oout[OtpIfWidth-1:0] logic
    otp​_addr​_oout[OtpAddrWidth-1:0] logic
    otp​_gnt​_iinlogic
    otp​_rvalid​_iinlogic
    otp​_rdata​_iin[ScrmblBlockWidth-1:0] logic
    otp​_err​_iinerr_e

    Instantiations

    Block Diagram

    State Machines

    Module otp​_ctrl​_reg​_top

    This design unit is implemented in otp​_ctrl​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, otp_ctrl_reg_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint14
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    tl​_win​_oouttl_h2d_t [2]

    Output port for window

    tl​_win​_iintl_d2h_t [2]
    reg2hwoutotp_ctrl_reg2hw_t

    Write

    hw2reginotp_ctrl_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module otp​_ctrl​_scrmbl

    This design unit is implemented in otp​_ctrl​_scrmbl.sv

    This file depends on: prim_flop.sv, prim_present.sv, uvm_pkg.sv, otp_ctrl_pkg.sv, otp_ctrl_part_pkg.sv, prim_util_pkg.sv, prim_cipher_pkg.sv, lc_ctrl_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    StateWidthint9

    Encoding generated with ./sparse-fsm-encode.py -d 5 -m 5 -n 9 -s 2193087944 Hamming distance histogram:

    0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (60.00%) 6: ||||||||||||| (40.00%) 7: -- 8: -- 9: --

    Minimum Hamming distance: 5 Maximum Hamming distance: 6

    CntWidthint$clog2(NumPresentRounds+1)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    cmd​_iinotp_scrmbl_cmd_e

    input data and command

    mode​_iindigest_mode_e
    sel​_iin[ConstSelWidth-1:0] logic
    data​_iin[ScrmblBlockWidth-1:0] logic
    valid​_iinlogic
    ready​_ooutlogic
    data​_oout[ScrmblBlockWidth-1:0] logic

    output data

    valid​_ooutlogic
    escalate​_en​_iinlc_tx_t

    escalation input and FSM error indication

    fsm​_err​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module pattgen​_core

    This design unit is implemented in pattgen​_core.sv

    This file depends on: pattgen_chan.sv, pattgen_ctrl_pkg.sv, prim_intr_hw.sv, pattgen_reg_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    reg2hwinpattgen_reg2hw_t
    hw2regoutpattgen_hw2reg_t
    pda0​_tx​_ooutlogic
    pcl0​_tx​_ooutlogic
    pda1​_tx​_ooutlogic
    pcl1​_tx​_ooutlogic
    intr​_done​_ch0​_ooutlogic
    intr​_done​_ch1​_ooutlogic

    Instantiations

    Block Diagram

    Package pattgen​_reg​_pkg

    This design unit is implemented in pattgen​_reg​_pkg.sv

    Module pattgen​_reg​_top

    This design unit is implemented in pattgen​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, pattgen_reg_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint6
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutpattgen_reg2hw_t

    Write

    hw2reginpattgen_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module pinmux​_reg​_top

    This design unit is implemented in pinmux​_reg​_top.sv

    This file depends on: pinmux_reg_pkg.sv, prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint12
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutpinmux_reg2hw_t

    Write

    hw2reginpinmux_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module pinmux​_strap​_sampling

    This design unit is implemented in pinmux​_strap​_sampling.sv

    This file depends on: pinmux_reg_pkg.sv, jtag_pkg.sv, uvm_pkg.sv, prim_lc_sync.sv, pinmux_jtag_buf.sv, pinmux_pkg.sv, lc_ctrl_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    mio​_in​_iin[NMioPads-1:0] logic

    MIO inputs. TODO(#5221): need tapped IOs for JTAG mux.

    strap​_en​_iinlogic

    Used for TAP qualification

    lc​_dft​_en​_iinlc_tx_t
    lc​_hw​_debug​_en​_iinlc_tx_t
    dft​_strap​_test​_ooutdft_strap_test_req_t

    Sampled values for DFT straps

    lc​_jtag​_ooutjtag_req_t

    Qualified JTAG signals for TAPs

    lc​_jtag​_iinjtag_rsp_t
    rv​_jtag​_ooutjtag_req_t
    rv​_jtag​_iinjtag_rsp_t
    dft​_jtag​_ooutjtag_req_t
    dft​_jtag​_iinjtag_rsp_t

    Instantiations

    Block Diagram

    Module pinmux​_wkup

    This design unit is implemented in pinmux​_wkup.sv

    This file depends on: pinmux_reg_pkg.sv, prim_flop_2sync.sv, prim_filter.sv, pinmux_pkg.sv, prim_pulse_sync.sv

    Description

    Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

    Parameters

    NameTypeDefault ValueDescription
    Cyclesint4

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    clk​_aon​_iinlogic

    Always on clock / reset

    rst​_aon​_niinlogic
    wkup​_en​_iinlogic

    These signals get synchronized to the slow AON clock within this module. Note that wkup_en_i is assumed to be level encoded.

    filter​_en​_iinlogic
    wkup​_mode​_iinwkup_mode_e
    wkup​_cnt​_th​_iin[WkupCntWidth-1:0] logic
    pin​_value​_iinlogic
    wkup​_cause​_valid​_iinlogic

    Signals to/from cause register. They are synched to/from the AON clock internally

    wkup​_cause​_data​_iinlogic
    wkup​_cause​_data​_ooutlogic
    aon​_wkup​_req​_ooutlogic

    This signal is running on the AON clock and is held high as long as the cause register has not been cleared.

    Instantiations

    Block Diagram

    Module prim​_alert​_receiver

    This design unit is implemented in prim​_alert​_receiver.sv

    This file depends on: prim_diff_decode.sv, uvm_pkg.sv, prim_alert_pkg.sv, prim_buf.sv

    Parameters

    NameTypeDefault ValueDescription
    AsyncOnbit1'b0

    enables additional synchronization logic

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    ping​_req​_iinlogic

    this triggers a ping test. keep asserted until ping_ok_o is asserted.

    ping​_ok​_ooutlogic
    integ​_fail​_ooutlogic

    asserted if signal integrity issue detected

    alert​_ooutlogic

    alert output (pulsed high) if a handshake is initiated on alert_p/n and no ping request is outstanding

    alert​_rx​_ooutalert_rx_t

    ping input diff pair and ack diff pair

    alert​_tx​_iinalert_tx_t

    alert output diff pair

    Instantiations

    Block Diagram

    State Machines

    Module prim​_alert​_sender

    This design unit is implemented in prim​_alert​_sender.sv

    This file depends on: prim_diff_decode.sv, uvm_pkg.sv, prim_alert_pkg.sv, prim_buf.sv

    Parameters

    NameTypeDefault ValueDescription
    AsyncOnbit1'b1

    enables additional synchronization logic

    IsFatalbit1'b0

    alert sender will latch the incoming alert event permanently and keep on sending alert events until the next reset.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    alert​_test​_iinlogic

    alert test trigger (this will never be latched, even if IsFatal == 1)

    alert​_req​_iinlogic

    native alert from the peripheral

    alert​_ack​_ooutlogic
    alert​_state​_ooutlogic

    state of the alert latching register

    alert​_rx​_iinalert_rx_t

    ping input diff pair and ack diff pair

    alert​_tx​_ooutalert_tx_t

    alert output diff pair

    Instantiations

    Block Diagram

    State Machines

    Module prim​_arbiter​_fixed

    This design unit is implemented in prim​_arbiter​_fixed.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Nint8
    DWint32
    EnDataPortbit1

    Configurations EnDataPort: {0, 1}, if 0, input data will be ignored

    IdxWint$clog2(N)

    Derived parameters

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    used for assertions only

    rst​_niinlogic
    req​_iin[N-1:0] logic
    data​_iin[DW-1:0] logic [N]
    gnt​_oout[N-1:0] logic
    idx​_oout[IdxW-1:0] logic
    valid​_ooutlogic
    data​_oout[DW-1:0] logic
    ready​_iinlogic

    Block Diagram

    Module prim​_arbiter​_tree

    This design unit is implemented in prim​_arbiter​_tree.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Nint8
    DWint32
    EnDataPortbit1

    Configurations EnDataPort: {0, 1}, if 0, input data will be ignored

    EnReqStabAbit1

    Non-functional parameter to switch on the request stability assertion

    IdxWint$clog2(N)

    Derived parameters

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_iin[N-1:0] logic
    data​_iin[DW-1:0] logic [N]
    gnt​_oout[N-1:0] logic
    idx​_oout[IdxW-1:0] logic
    valid​_ooutlogic
    data​_oout[DW-1:0] logic
    ready​_iinlogic

    Block Diagram

    Module prim​_clock​_buf

    This design unit is implemented in prim​_clock​_buf.sv

    This file depends on: prim_generic_clock_buf.sv, prim_xilinx_clock_buf.sv, prim_pkg.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    Implimpl_eprim_pkg::ImplGeneric

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    clk​_ooutlogic

    Block Diagram

    Module prim​_clock​_div

    This design unit is implemented in prim​_clock​_div.sv

    This file depends on: prim_flop.sv, uvm_pkg.sv, prim_clock_mux2.sv, prim_clock_inv.sv, prim_clock_buf.sv

    Parameters

    NameTypeDefault ValueDescription
    Divisorint2
    ResetValuelogic0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    step​_down​_req​_iinlogic

    step down divisor by 2x

    step​_down​_ack​_ooutlogic

    step down acknowledge

    test​_en​_iinlogic
    clk​_ooutlogic

    Instantiations

    Block Diagram

    Module prim​_clock​_gating

    This design unit is implemented in prim​_clock​_gating.sv

    This file depends on: prim_xilinx_clock_gating.sv, prim_pkg.sv, prim_generic_clock_gating.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    NoFpgaGatebit1'b0

    this parameter has no function in generic

    Implimpl_eprim_pkg::ImplGeneric

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    en​_iinlogic
    test​_en​_iinlogic
    clk​_ooutlogic

    Block Diagram

    Module prim​_clock​_gating​_sync

    This design unit is implemented in prim​_clock​_gating​_sync.sv

    This file depends on: prim_flop_2sync.sv, prim_clock_gating.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    test​_en​_iinlogic
    async​_en​_iinlogic
    en​_ooutlogic
    clk​_ooutlogic

    Instantiations

    Block Diagram

    Module prim​_clock​_inv

    This design unit is implemented in prim​_clock​_inv.sv

    This file depends on: prim_generic_clock_inv.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    HasScanModebit1'b1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    scanmode​_iinlogic
    clk​_nooutlogic

    Inverted

    Block Diagram

    Module prim​_clock​_mux2

    This design unit is implemented in prim​_clock​_mux2.sv

    This file depends on: prim_xilinx_clock_mux2.sv, prim_generic_clock_mux2.sv, prim_pkg.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    NoFpgaBufGbit1'b0

    this parameter serves no function in the generic model

    Implimpl_eprim_pkg::ImplGeneric

    Ports

    NameDirectionTypeDescription
    clk0​_iinlogic
    clk1​_iinlogic
    sel​_iinlogic
    clk​_ooutlogic

    Block Diagram

    Module prim​_edn​_req

    This design unit is implemented in prim​_edn​_req.sv

    This file depends on: prim_sync_reqack_data.sv, prim_alert_pkg.sv, edn_pkg.sv, prim_packer_fifo.sv

    Parameters

    NameTypeDefault ValueDescription
    OutWidthint32
    SyncWidthint$bits({edn_i.edn_fips, edn_i.edn_bus})

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Design side

    rst​_niinlogic
    req​_iinlogic
    ack​_ooutlogic
    data​_oout[OutWidth-1:0] logic
    fips​_ooutlogic
    clk​_edn​_iinlogic

    EDN side

    rst​_edn​_niinlogic
    edn​_ooutedn_req_t
    edn​_iinedn_rsp_t

    Instantiations

    Block Diagram

    Module prim​_esc​_receiver

    This design unit is implemented in prim​_esc​_receiver.sv

    This file depends on: prim_diff_decode.sv, uvm_pkg.sv, prim_buf.sv, prim_esc_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    esc​_en​_ooutlogic

    escalation enable

    esc​_rx​_ooutesc_rx_t

    escalation / ping response

    esc​_tx​_iinesc_tx_t

    escalation output diff pair

    Instantiations

    Block Diagram

    State Machines

    Module prim​_esc​_sender

    This design unit is implemented in prim​_esc​_sender.sv

    This file depends on: prim_diff_decode.sv, uvm_pkg.sv, prim_buf.sv, prim_esc_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    ping​_req​_iinlogic

    this triggers a ping test. keep asserted until ping_ok_o is pulsed high.

    ping​_ok​_ooutlogic
    integ​_fail​_ooutlogic

    asserted if signal integrity issue detected

    esc​_req​_iinlogic

    escalation request signal

    esc​_rx​_iinesc_rx_t

    escalation / ping response

    esc​_tx​_ooutesc_tx_t

    escalation output diff pair

    Instantiations

    Block Diagram

    State Machines

    Module prim​_fifo​_async

    This design unit is implemented in prim​_fifo​_async.sv

    This file depends on: prim_flop_2sync.sv, uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint16
    Depthint3
    DepthWint$clog2(Depth+1)

    derived parameter representing 0..Depth

    PTRV​_Wint$clog2(Depth)
    PTR​_WIDTHintPTRV_W+1

    Ports

    NameDirectionTypeDescription
    clk​_wr​_iinlogic

    write port

    rst​_wr​_niinlogic
    wvalid​_iinlogic
    wready​_ooutlogic
    wdata​_iin[Width-1:0] logic
    wdepth​_oout[DepthW-1:0] logic
    clk​_rd​_iinlogic

    read port

    rst​_rd​_niinlogic
    rvalid​_ooutlogic
    rready​_iinlogic
    rdata​_oout[Width-1:0] logic
    rdepth​_oout[DepthW-1:0] logic

    Instantiations

    Block Diagram

    Module prim​_fifo​_sync

    This design unit is implemented in prim​_fifo​_sync.sv

    This file depends on: uvm_pkg.sv, prim_util_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint16
    Passbit1'b1

    if == 1 allow requests to pass through empty FIFO

    Depthint4
    OutputZeroIfEmptybit1'b1

    if == 1 always output 0 when FIFO is empty

    DepthWintprim_util_pkg::vbits(Depth+1)

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    clr​_iinlogic

    synchronous clear / flush port

    wvalid​_iinlogic

    write port

    wready​_ooutlogic
    wdata​_iin[Width-1:0] logic
    rvalid​_ooutlogic

    read port

    rready​_iinlogic
    rdata​_oout[Width-1:0] logic
    full​_ooutlogic

    occupancy

    depth​_oout[DepthW-1:0] logic

    Block Diagram

    Module prim​_filter​_ctr

    This design unit is implemented in prim​_filter​_ctr.sv

    Parameters

    NameTypeDefault ValueDescription
    Cyclesint4
    CTR​_WIDTHint$clog2(Cycles)
    CYCLESM1[CTR_WIDTH-1:0] logic(CTR_WIDTH)'(Cycles-1)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    enable​_iinlogic
    filter​_iinlogic
    filter​_ooutlogic

    Block Diagram

    Module prim​_flash

    This design unit is implemented in prim​_flash.sv

    This file depends on: prim_generic_flash.sv, flash_phy_pkg.sv, tlul_pkg.sv, lc_ctrl_pkg.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    NumBanksint2

    number of banks

    InfosPerBankint1

    info pages per bank

    InfoTypesint1

    different info types

    InfoTypesWidthint1

    different info types

    PagesPerBankint256

    data pages per bank

    WordsPerPageint256

    words per page

    DataWidthint32

    bits per word

    MetaDataWidthint12

    metadata such as ECC

    TestModeWidthint4

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    flash​_req​_iin[NumBanks-1:0] flash_phy_prim_flash_req_t
    flash​_rsp​_oout[NumBanks-1:0] flash_phy_prim_flash_rsp_t
    prog​_type​_avail​_oout[flash_phy_pkg::ProgTypes-1:0] logic
    init​_busy​_ooutlogic
    tck​_iinlogic
    tdi​_iinlogic
    tms​_iinlogic
    tdo​_ooutlogic
    bist​_enable​_iinlc_tx_t
    scanmode​_iinlc_tx_t
    scan​_en​_iinlogic
    scan​_rst​_niinlogic
    flash​_power​_ready​_h​_iinlogic
    flash​_power​_down​_h​_iinlogic
    flash​_test​_mode​_a​_iin[TestModeWidth-1:0] logic
    flash​_test​_voltage​_h​_iinlogic
    flash​_err​_ooutlogic
    flash​_alert​_pooutlogic
    flash​_alert​_nooutlogic
    flash​_alert​_ack​_iinlogic
    flash​_alert​_trig​_iinlogic
    tl​_iintl_h2d_t
    tl​_oouttl_d2h_t
    devmode​_iinlogic

    Block Diagram

    Module prim​_flop

    This design unit is implemented in prim​_flop.sv

    This file depends on: prim_generic_flop.sv, prim_xilinx_flop.sv, prim_pkg.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    Widthint1
    WidthSubOneintWidth-1
    ResetValue[WidthSubOne:0] logic0
    Implimpl_eprim_pkg::ImplGeneric

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    d​_iin[Width-1:0] logic
    q​_oout[Width-1:0] logic

    Block Diagram

    Module prim​_flop​_2sync

    This design unit is implemented in prim​_flop​_2sync.sv

    This file depends on: prim_generic_flop_2sync.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    Widthint16
    WidthSubOneintWidth-1

    temp work around #2679

    ResetValue[WidthSubOne:0] logic'0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    receive clock

    rst​_niinlogic
    d​_iin[Width-1:0] logic
    q​_oout[Width-1:0] logic

    Block Diagram

    Module prim​_generic​_flop​_2sync

    This design unit is implemented in prim​_generic​_flop​_2sync.sv

    This file depends on: prim_flop.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint16
    WidthSubOneintWidth-1

    temp work around #2679

    ResetValue[WidthSubOne:0] logic'0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    receive clock

    rst​_niinlogic
    d​_iin[Width-1:0] logic
    q​_oout[Width-1:0] logic

    Instantiations

    Block Diagram

    Module prim​_generic​_pad​_wrapper

    This design unit is implemented in prim​_generic​_pad​_wrapper.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Variantint0

    currently ignored

    AttrDwint10
    WarlOnlybit0

    If set to 1, no pad is instantiated and only warl_o is driven

    Ports

    NameDirectionTypeDescription
    inout​_ioinoutlogic

    bidirectional pad

    in​_ooutlogic

    input data

    ie​_iinlogic

    input enable

    out​_iinlogic

    output data

    oe​_iinlogic

    output enable

    attr​_iin[AttrDw-1:0] logic

    additional attributes

    warl​_oout[AttrDw-1:0] logic

    Block Diagram

    Module prim​_intr​_hw

    This design unit is implemented in prim​_intr​_hw.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint1
    FlopOutputbit1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    event

    rst​_niinlogic
    event​_intr​_iin[Width-1:0] logic
    reg2hw​_intr​_enable​_q​_iin[Width-1:0] logic

    register interface

    reg2hw​_intr​_test​_q​_iin[Width-1:0] logic
    reg2hw​_intr​_test​_qe​_iinlogic
    reg2hw​_intr​_state​_q​_iin[Width-1:0] logic
    hw2reg​_intr​_state​_de​_ooutlogic
    hw2reg​_intr​_state​_d​_oout[Width-1:0] logic
    intr​_oout[Width-1:0] logic

    outgoing interrupt

    Block Diagram

    Module prim​_lc​_sender

    This design unit is implemented in prim​_lc​_sender.sv

    This file depends on: prim_generic_flop.sv, lc_ctrl_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    lc​_en​_iinlc_tx_t
    lc​_en​_ooutlc_tx_t

    Instantiations

    Block Diagram

    Module prim​_lc​_sync

    This design unit is implemented in prim​_lc​_sync.sv

    This file depends on: prim_flop_2sync.sv, uvm_pkg.sv, prim_buf.sv, lc_ctrl_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    NumCopiesint1

    Number of separately buffered output signals. The buffer cells have a don't touch constraint on them such that synthesis tools won't collapse all copies into one signal.

    AsyncOnbit1

    This instantiates the synchronizer flops if set to 1. In special cases where the receiver is in the same clock domain as the sender, this can be set to 0. However, it is recommended to leave this at 1.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    lc​_en​_iinlc_tx_t
    lc​_en​_oout[NumCopies-1:0] lc_tx_t

    Block Diagram

    Module prim​_lfsr

    This design unit is implemented in prim​_lfsr.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    LfsrTypeunknown"GAL_XOR"

    Lfsr Type, can be FIB_XNOR or GAL_XOR

    LfsrDwint32

    Lfsr width

    EntropyDwint8

    Width of the entropy input to be XOR'd into state (lfsr_qEntropyDw-1:0)

    StateOutDwint8

    Width of output tap (from lfsr_qStateOutDw-1:0)

    DefaultSeed[LfsrDw-1:0] logicLfsrDw'(1)

    Lfsr reset state, must be nonzero!

    CustomCoeffs[LfsrDw-1:0] logic'0

    Custom polynomial coeffs

    StatePermEnbit1'b0

    If StatePermEn is set to 1, the custom permutation specified via StatePerm is applied to the state output, in order to break linear shifting patterns of the LFSR.

    StatePerm[$clog2(LfsrDw)-1:0] [LfsrDw-1:0] logic'0
    MaxLenSVAbit1'b1

    Enable this for DV, disable this for long LFSRs in FPV

    LockupSVAbit1'b1

    Can be disabled in cases where seed and entropy inputs are unused in order to not distort coverage (the SVA will be unreachable in such cases)

    ExtSeedSVAbit1'b1
    GAL​_XOR​_LUT​_OFFint4

    automatically generated with util/design/get-lfsr-coeffs.py script

    GAL​_XOR​_COEFFS[63:0] logic [61]'{ 64'h9, 64'h12, 64'h21, 64'h41, 64'h8E, 64'h108, 64'h204, 64'h402, 64'h829, 64'h100D, 64'h2015, 64'h4001, 64'h8016, 64'h10004, 64'h20013, 64'h40013, 64'h80004, 64'h100002, 64'h200001, 64'h400010, 64'h80000D, 64'h1000004, 64'h2000023, 64'h4000013, 64'h8000004, 64'h10000002, 64'h20000029, 64'h40000004, 64'h80000057, 64'h100000029, 64'h200000073, 64'h400000002, 64'h80000003B, 64'h100000001F, 64'h2000000031, 64'h4000000008, 64'h800000001C, 64'h10000000004, 64'h2000000001F, 64'h4000000002C, 64'h80000000032, 64'h10000000000D, 64'h200000000097, 64'h400000000010, 64'h80000000005B, 64'h1000000000038, 64'h200000000000E, 64'h4000000000025, 64'h8000000000004, 64'h10000000000023, 64'h2000000000003E, 64'h40000000000023, 64'h8000000000004A, 64'h100000000000016, 64'h200000000000031, 64'h40000000000003D, 64'h800000000000001, 64'h1000000000000013, 64'h2000000000000034, 64'h4000000000000001, 64'h800000000000000D }
    FIB​_XNOR​_LUT​_OFFint3

    automatically generated with get-lfsr-coeffs.py script

    FIB​_XNOR​_COEFFS[167:0] logic [166]'{ 168'h6, 168'hC, 168'h14, 168'h30, 168'h60, 168'hB8, 168'h110, 168'h240, 168'h500, 168'h829, 168'h100D, 168'h2015, 168'h6000, 168'hD008, 168'h12000, 168'h20400, 168'h40023, 168'h90000, 168'h140000, 168'h300000, 168'h420000, 168'hE10000, 168'h1200000, 168'h2000023, 168'h4000013, 168'h9000000, 168'h14000000, 168'h20000029, 168'h48000000, 168'h80200003, 168'h100080000, 168'h204000003, 168'h500000000, 168'h801000000, 168'h100000001F, 168'h2000000031, 168'h4400000000, 168'hA000140000, 168'h12000000000, 168'h300000C0000, 168'h63000000000, 168'hC0000030000, 168'h1B0000000000, 168'h300003000000, 168'h420000000000, 168'hC00000180000, 168'h1008000000000, 168'h3000000C00000, 168'h6000C00000000, 168'h9000000000000, 168'h18003000000000, 168'h30000000030000, 168'h40000040000000, 168'hC0000600000000, 168'h102000000000000, 168'h200004000000000, 168'h600003000000000, 168'hC00000000000000, 168'h1800300000000000, 168'h3000000000000030, 168'h6000000000000000, 168'hD800000000000000, 168'h10000400000000000, 168'h30180000000000000, 168'h60300000000000000, 168'h80400000000000000, 168'h140000028000000000, 168'h300060000000000000, 168'h410000000000000000, 168'h820000000001040000, 168'h1000000800000000000, 168'h3000600000000000000, 168'h6018000000000000000, 168'hC000000018000000000, 168'h18000000600000000000, 168'h30000600000000000000, 168'h40200000000000000000, 168'hC0000000060000000000, 168'h110000000000000000000, 168'h240000000480000000000, 168'h600000000003000000000, 168'h800400000000000000000, 168'h1800000300000000000000, 168'h3003000000000000000000, 168'h4002000000000000000000, 168'hC000000000000000018000, 168'h10000000004000000000000, 168'h30000C00000000000000000, 168'h600000000000000000000C0, 168'hC00C0000000000000000000, 168'h140000000000000000000000, 168'h200001000000000000000000, 168'h400800000000000000000000, 168'hA00000000001400000000000, 168'h1040000000000000000000000, 168'h2004000000000000000000000, 168'h5000000000028000000000000, 168'h8000000004000000000000000, 168'h18600000000000000000000000, 168'h30000000000000000C00000000, 168'h40200000000000000000000000, 168'hC0300000000000000000000000, 168'h100010000000000000000000000, 168'h200040000000000000000000000, 168'h5000000000000000A0000000000, 168'h800000010000000000000000000, 168'h1860000000000000000000000000, 168'h3003000000000000000000000000, 168'h4010000000000000000000000000, 168'hA000000000140000000000000000, 168'h10080000000000000000000000000, 168'h30000000000000000000180000000, 168'h60018000000000000000000000000, 168'hC0000000000000000300000000000, 168'h140005000000000000000000000000, 168'h200000001000000000000000000000, 168'h404000000000000000000000000000, 168'h810000000000000000000000000102, 168'h1000040000000000000000000000000, 168'h3000000000000006000000000000000, 168'h5000000000000000000000000000000, 168'h8000000004000000000000000000000, 168'h18000000000000000000000000030000, 168'h30000000030000000000000000000000, 168'h60000000000000000000000000000000, 168'hA0000014000000000000000000000000, 168'h108000000000000000000000000000000, 168'h240000000000000000000000000000000, 168'h600000000000C00000000000000000000, 168'h800000040000000000000000000000000, 168'h1800000000000300000000000000000000, 168'h2000000000000010000000000000000000, 168'h4008000000000000000000000000000000, 168'hC000000000000000000000000000000600, 168'h10000080000000000000000000000000000, 168'h30600000000000000000000000000000000, 168'h4A400000000000000000000000000000000, 168'h80000004000000000000000000000000000, 168'h180000003000000000000000000000000000, 168'h200001000000000000000000000000000000, 168'h600006000000000000000000000000000000, 168'hC00000000000000006000000000000000000, 168'h1000000000000100000000000000000000000, 168'h3000000000000006000000000000000000000, 168'h6000000003000000000000000000000000000, 168'h8000001000000000000000000000000000000, 168'h1800000000000000000000000000C000000000, 168'h20000000000001000000000000000000000000, 168'h48000000000000000000000000000000000000, 168'hC0000000000000006000000000000000000000, 168'h180000000000000000000000000000000000000, 168'h280000000000000000000000000000005000000, 168'h60000000C000000000000000000000000000000, 168'hC00000000000000000000000000018000000000, 168'h1800000600000000000000000000000000000000, 168'h3000000C00000000000000000000000000000000, 168'h4000000080000000000000000000000000000000, 168'hC000300000000000000000000000000000000000, 168'h10000400000000000000000000000000000000000, 168'h30000000000000000000006000000000000000000, 168'h600000000000000C0000000000000000000000000, 168'hC0060000000000000000000000000000000000000, 168'h180000006000000000000000000000000000000000, 168'h3000000000C0000000000000000000000000000000, 168'h410000000000000000000000000000000000000000, 168'hA00140000000000000000000000000000000000000 }

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    seed​_en​_iinlogic

    load external seed into the state (takes precedence)

    seed​_iin[LfsrDw-1:0] logic

    external seed input

    lfsr​_en​_iinlogic

    enables the LFSR

    entropy​_iin[EntropyDw-1:0] logic

    additional entropy to be XOR'ed into the state

    state​_oout[StateOutDw-1:0] logic

    (partial) LFSR state output

    Block Diagram

    Module prim​_otp

    This design unit is implemented in prim​_otp.sv

    This file depends on: prim_generic_otp.sv, prim_util_pkg.sv, prim_otp_pkg.sv, tlul_pkg.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    Widthint16

    Native OTP word size. This determines the size_i granule.

    Depthint1024
    SizeWidthint2

    This determines the maximum number of native words that can be transferred accross the interface in one cycle.

    PwrSeqWidthint2

    Width of the power sequencing signal.

    TlDepthint16

    Number of Test TL-UL words

    AddrWidthintprim_util_pkg::vbits(Depth)

    Derived parameters

    IfWidthint2**SizeWidth*Width
    MemInitFileunknown""

    VMEM file to initialize the memory with

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    pwr​_seq​_oout[PwrSeqWidth-1:0] logic

    Macro-specific power sequencing signals to/from AST

    pwr​_seq​_h​_iin[PwrSeqWidth-1:0] logic
    test​_tl​_iintl_h2d_t

    Test interface

    test​_tl​_oouttl_d2h_t
    ready​_ooutlogic

    Ready valid handshake for read/write command

    valid​_iinlogic
    size​_iin[SizeWidth-1:0] logic

    #(Native words)-1, e.g. size == 0 for 1 native word.

    cmd​_iincmd_e

    00: read command, 01: write command, 11: init command

    addr​_iin[AddrWidth-1:0] logic
    wdata​_iin[IfWidth-1:0] logic
    valid​_ooutlogic

    Response channel

    rdata​_oout[IfWidth-1:0] logic
    err​_oouterr_e

    Block Diagram

    Package prim​_otp​_pkg

    This design unit is implemented in prim​_otp​_pkg.sv

    Module prim​_packer

    This design unit is implemented in prim​_packer.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    InWint32
    OutWint32
    HintByteDataint0

    If 1, The input/output are byte granularity

    WidthintInW + OutW

    storage width

    ConcatWintWidth + InW

    Input concatenated width

    PtrWint$clog2(ConcatW+1)
    IdxWint$clog2(InW) + ~|$clog2(InW)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    valid​_iinlogic
    data​_iin[InW-1:0] logic
    mask​_iin[InW-1:0] logic
    ready​_ooutlogic
    valid​_ooutlogic
    data​_oout[OutW-1:0] logic
    mask​_oout[OutW-1:0] logic
    ready​_iinlogic
    flush​_iinlogic

    If 1, send out remnant and clear state

    flush​_done​_ooutlogic

    Block Diagram

    State Machines

    Module prim​_packer​_fifo

    This design unit is implemented in prim​_packer​_fifo.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    InWint32
    OutWint8
    MaxWint(InW > OutW) ? InW : OutW

    derived parameters

    MinWint(InW < OutW) ? InW : OutW
    DepthWint$clog2(MaxW/MinW)
    WidthRatiointMaxW / MinW
    FullDepth[DepthW:0] bitWidthRatio[DepthW:0]

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    clr​_iinlogic
    wvalid​_iinlogic
    wdata​_iin[InW-1:0] logic
    wready​_ooutlogic
    rvalid​_ooutlogic
    rdata​_oout[OutW-1:0] logic
    rready​_iinlogic
    depth​_oout[DepthW:0] logic

    Block Diagram

    Package prim​_pkg

    This design unit is implemented in prim​_pkg.sv

    Module prim​_prince

    This design unit is implemented in prim​_prince.sv

    This file depends on: uvm_pkg.sv, prim_cipher_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    DataWidthint64
    KeyWidthint128
    NumRoundsHalfint5

    The construction is reflective. Total number of rounds is 2*NumRoundsHalf + 2

    UseOldKeySchedbit1'b0

    This primitive uses the new key schedule proposed in https://eprint.iacr.org/2014/656.pdf Setting this parameter to 1 falls back to the original key schedule.

    HalfwayDataRegbit1'b0

    This instantiates a data register halfway in the primitive.

    HalfwayKeyRegbit1'b0

    This instantiates a key register halfway in the primitive.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    valid​_iinlogic
    data​_iin[DataWidth-1:0] logic
    key​_iin[KeyWidth-1:0] logic
    dec​_iinlogic

    set to 1 for decryption

    valid​_ooutlogic
    data​_oout[DataWidth-1:0] logic

    Block Diagram

    Module prim​_pulse​_sync

    This design unit is implemented in prim​_pulse​_sync.sv

    This file depends on: prim_flop_2sync.sv

    Ports

    NameDirectionTypeDescription
    clk​_src​_iinlogic

    source clock domain

    rst​_src​_niinlogic
    src​_pulse​_iinlogic
    clk​_dst​_iinlogic

    destination clock domain

    rst​_dst​_niinlogic
    dst​_pulse​_ooutlogic

    Instantiations

    Block Diagram

    Module prim​_ram​_1p​_adv

    This design unit is implemented in prim​_ram​_1p​_adv.sv

    This file depends on: prim_secded_hamming_39_32_dec.sv, prim_secded_22_16_enc.sv, uvm_pkg.sv, prim_secded_hamming_39_32_enc.sv, prim_secded_hamming_22_16_enc.sv, prim_secded_39_32_enc.sv, prim_util_pkg.sv, prim_secded_hamming_22_16_dec.sv, prim_secded_22_16_dec.sv, prim_secded_39_32_dec.sv, prim_ram_1p.sv

    Parameters

    NameTypeDefault ValueDescription
    Depthint512
    Widthint32
    DataBitsPerMaskint1

    Number of data bits per bit of write mask

    CfgWint8

    WTC, RTC, etc

    MemInitFileunknown""

    VMEM file to initialize the memory with

    EnableECCbit0

    Enables per-word ECC

    EnableParitybit0

    Enables per-Byte Parity

    EnableInputPipelinebit0

    Adds an input register (read latency +1)

    EnableOutputPipelinebit0

    Adds an output register (read latency +1)

    HammingECCbit0

    This switch allows to switch to standard Hamming ECC instead of the HSIAO ECC. It is recommended to leave this parameter at its default setting (HSIAO), since this results in a more compact and faster implementation.

    Awintprim_util_pkg::vbits(Depth)
    ParWidthint(EnableParity) ? Width/8 : (!EnableECC) ? 0 : (Width <= 4) ? 4 : (Width <= 11) ? 5 : (Width <= 26) ? 6 : (Width <= 57) ? 7 : (Width <= 120) ? 8 : 8

    Calculate ECC width

    TotalWidthintWidth + ParWidth
    LocalDataBitsPerMaskint(EnableParity) ? 9 : (EnableECC) ? TotalWidth : DataBitsPerMask

    If byte parity is enabled, the write enable bits are used to write memory colums with 8 + 1 = 9 bit width (data plus corresponding parity bit). If ECC is enabled, the DataBitsPerMask is ignored.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_iinlogic
    write​_iinlogic
    addr​_iin[Aw-1:0] logic
    wdata​_iin[Width-1:0] logic
    wmask​_iin[Width-1:0] logic
    rdata​_oout[Width-1:0] logic
    rvalid​_ooutlogic

    read response (rdata_o) is valid

    rerror​_oout[1:0] logic

    Bit1: Uncorrectable, Bit0: Correctable

    cfg​_iin[CfgW-1:0] logic

    config

    Instantiations

    Block Diagram

    Module prim​_ram​_2p​_adv

    This design unit is implemented in prim​_ram​_2p​_adv.sv

    This file depends on: prim_util_pkg.sv, prim_ram_2p_async_adv.sv

    Parameters

    NameTypeDefault ValueDescription
    Depthint512
    Widthint32
    DataBitsPerMaskint1

    Number of data bits per bit of write mask

    CfgWint8

    WTC, RTC, etc

    MemInitFileunknown""

    VMEM file to initialize the memory with

    EnableECCbit0

    Enables per-word ECC

    EnableParitybit0

    Enables per-Byte Parity

    EnableInputPipelinebit0

    Adds an input register (read latency +1)

    EnableOutputPipelinebit0

    Adds an output register (read latency +1)

    HammingECCbit0

    This switch allows to switch to standard Hamming ECC instead of the HSIAO ECC. It is recommended to leave this parameter at its default setting (HSIAO), since this results in a more compact and faster implementation.

    Awintprim_util_pkg::vbits(Depth)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    a​_req​_iinlogic
    a​_write​_iinlogic
    a​_addr​_iin[Aw-1:0] logic
    a​_wdata​_iin[Width-1:0] logic
    a​_wmask​_iin[Width-1:0] logic

    cannot be used with ECC, tie to 1 in that case

    a​_rdata​_oout[Width-1:0] logic
    a​_rvalid​_ooutlogic

    read response (a_rdata_o) is valid

    a​_rerror​_oout[1:0] logic

    Bit1: Uncorrectable, Bit0: Correctable

    b​_req​_iinlogic
    b​_write​_iinlogic
    b​_addr​_iin[Aw-1:0] logic
    b​_wdata​_iin[Width-1:0] logic
    b​_wmask​_iin[Width-1:0] logic

    cannot be used with ECC, tie to 1 in that case

    b​_rdata​_oout[Width-1:0] logic
    b​_rvalid​_ooutlogic

    read response (b_rdata_o) is valid

    b​_rerror​_oout[1:0] logic

    Bit1: Uncorrectable, Bit0: Correctable

    cfg​_iin[CfgW-1:0] logic

    Instantiations

    Block Diagram

    Module prim​_ram​_2p​_async​_adv

    This design unit is implemented in prim​_ram​_2p​_async​_adv.sv

    This file depends on: prim_secded_hamming_39_32_dec.sv, uvm_pkg.sv, prim_secded_hamming_39_32_enc.sv, prim_secded_39_32_enc.sv, prim_util_pkg.sv, prim_ram_2p.sv, prim_secded_39_32_dec.sv

    Parameters

    NameTypeDefault ValueDescription
    Depthint512
    Widthint32
    DataBitsPerMaskint1

    Number of data bits per bit of write mask

    CfgWint8

    WTC, RTC, etc

    MemInitFileunknown""

    VMEM file to initialize the memory with

    EnableECCbit0

    Enables per-word ECC

    EnableParitybit0

    Enables per-Byte Parity

    EnableInputPipelinebit0

    Adds an input register (read latency +1)

    EnableOutputPipelinebit0

    Adds an output register (read latency +1)

    HammingECCbit0

    This switch allows to switch to standard Hamming ECC instead of the HSIAO ECC. It is recommended to leave this parameter at its default setting (HSIAO), since this results in a more compact and faster implementation.

    Awintprim_util_pkg::vbits(Depth)
    ParWidthint(EnableParity) ? Width/8 : (!EnableECC) ? 0 : (Width <= 4) ? 4 : (Width <= 11) ? 5 : (Width <= 26) ? 6 : (Width <= 57) ? 7 : (Width <= 120) ? 8 : 8

    Calculate ECC width

    TotalWidthintWidth + ParWidth
    LocalDataBitsPerMaskint(EnableParity) ? 9 : (EnableECC) ? TotalWidth : DataBitsPerMask

    If byte parity is enabled, the write enable bits are used to write memory colums with 8 + 1 = 9 bit width (data plus corresponding parity bit). If ECC is enabled, the DataBitsPerMask is ignored.

    Ports

    NameDirectionTypeDescription
    clk​_a​_iinlogic
    clk​_b​_iinlogic
    rst​_a​_niinlogic
    rst​_b​_niinlogic
    a​_req​_iinlogic
    a​_write​_iinlogic
    a​_addr​_iin[Aw-1:0] logic
    a​_wdata​_iin[Width-1:0] logic
    a​_wmask​_iin[Width-1:0] logic

    cannot be used with ECC, tie to 1 in that case

    a​_rdata​_oout[Width-1:0] logic
    a​_rvalid​_ooutlogic

    read response (a_rdata_o) is valid

    a​_rerror​_oout[1:0] logic

    Bit1: Uncorrectable, Bit0: Correctable

    b​_req​_iinlogic
    b​_write​_iinlogic
    b​_addr​_iin[Aw-1:0] logic
    b​_wdata​_iin[Width-1:0] logic
    b​_wmask​_iin[Width-1:0] logic

    cannot be used with ECC, tie to 1 in that case

    b​_rdata​_oout[Width-1:0] logic
    b​_rvalid​_ooutlogic

    read response (b_rdata_o) is valid

    b​_rerror​_oout[1:0] logic

    Bit1: Uncorrectable, Bit0: Correctable

    cfg​_iin[CfgW-1:0] logic

    config

    Instantiations

    Block Diagram

    Module prim​_rom

    This design unit is implemented in prim​_rom.sv

    This file depends on: prim_generic_rom.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    Widthint32
    Depthint2048

    8kB default

    MemInitFileunknown""

    VMEM file to initialize the memory with

    Awint$clog2(Depth)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    req​_iinlogic
    addr​_iin[Aw-1:0] logic
    rdata​_oout[Width-1:0] logic

    Block Diagram

    Module prim​_sram​_arbiter

    This design unit is implemented in prim​_sram​_arbiter.sv

    This file depends on: prim_arbiter_ppc.sv, uvm_pkg.sv, prim_fifo_sync.sv, prim_arbiter_tree.sv

    Parameters

    NameTypeDefault ValueDescription
    Nint4
    SramDwint32
    SramAwint12
    ArbiterImplunknown"PPC"
    ARB​_DWint$bits(req_t)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_iin[N-1:0] logic
    req​_addr​_iin[SramAw-1:0] logic [N]
    req​_write​_iinlogic [N]
    req​_wdata​_iin[SramDw-1:0] logic [N]
    gnt​_oout[N-1:0] logic
    rsp​_rvalid​_oout[N-1:0] logic

    Pulse

    rsp​_rdata​_oout[SramDw-1:0] logic [N]
    rsp​_error​_oout[1:0] logic [N]
    sram​_req​_ooutlogic

    SRAM Interface

    sram​_addr​_oout[SramAw-1:0] logic
    sram​_write​_ooutlogic
    sram​_wdata​_oout[SramDw-1:0] logic
    sram​_rvalid​_iinlogic
    sram​_rdata​_iin[SramDw-1:0] logic
    sram​_rerror​_iin[1:0] logic

    Instantiations

    Block Diagram

    Module prim​_subreg

    This design unit is implemented in prim​_subreg.sv

    This file depends on: prim_subreg_arb.sv

    Parameters

    NameTypeDefault ValueDescription
    DWint32
    SWACCESSunknown"RW"

    {RW, RO, WO, W1C, W1S, W0C, RC}

    RESVAL[DW-1:0] logic'0

    Reset value

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    weinlogic

    From SW: valid for RW, WO, W1C, W1S, W0C, RC In case of RC, Top connects Read Pulse to we

    wdin[DW-1:0] logic
    deinlogic

    From HW: valid for HRW, HWO

    din[DW-1:0] logic
    qeoutlogic

    output to HW and Reg Read

    qout[DW-1:0] logic
    qsout[DW-1:0] logic

    Instantiations

    Block Diagram

    Module prim​_subst​_perm

    This design unit is implemented in prim​_subst​_perm.sv

    This file depends on: prim_cipher_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    DataWidthint64
    NumRoundsint31
    Decryptbit0

    0: encrypt, 1: decrypt

    Ports

    NameDirectionTypeDescription
    data​_iin[DataWidth-1:0] logic
    key​_iin[DataWidth-1:0] logic
    data​_oout[DataWidth-1:0] logic

    Block Diagram

    Module prim​_sync​_reqack​_data

    This design unit is implemented in prim​_sync​_reqack​_data.sv

    This file depends on: uvm_pkg.sv, prim_sync_reqack.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint1
    DataSrc2Dstbit1'b1

    Direction of data flow: 1'b1 = SRC to DST, 1'b0 = DST to SRC

    DataRegbit1'b0

    Enable optional register stage for data, only usable with DataSrc2Dst == 1'b0.

    Ports

    NameDirectionTypeDescription
    clk​_src​_iinlogic

    REQ side, SRC domain

    rst​_src​_niinlogic

    REQ side, SRC domain

    clk​_dst​_iinlogic

    ACK side, DST domain

    rst​_dst​_niinlogic

    ACK side, DST domain

    src​_req​_iinlogic

    REQ side, SRC domain

    src​_ack​_ooutlogic

    REQ side, SRC domain

    dst​_req​_ooutlogic

    ACK side, DST domain

    dst​_ack​_iinlogic

    ACK side, DST domain

    data​_iin[Width-1:0] logic
    data​_oout[Width-1:0] logic

    Instantiations

    Block Diagram

    Module prim​_sync​_slow​_fast

    This design unit is implemented in prim​_sync​_slow​_fast.sv

    This file depends on: prim_flop_2sync.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint32

    Ports

    NameDirectionTypeDescription
    clk​_slow​_iinlogic
    clk​_fast​_iinlogic
    rst​_fast​_niinlogic
    wdata​_iin[Width-1:0] logic

    Slow domain

    rdata​_oout[Width-1:0] logic

    Fast domain

    Instantiations

    Block Diagram

    Module prim​_xilinx​_pad​_wrapper

    This design unit is implemented in prim​_xilinx​_pad​_wrapper.sv

    This file depends on: IOBUF.v

    Parameters

    NameTypeDefault ValueDescription
    Variantint0

    currently ignored

    AttrDwint10
    WarlOnlybit0

    If set to 1, no pad is instantiated and only warl_o is driven

    Ports

    NameDirectionTypeDescription
    inout​_ioinoutlogic

    bidirectional pad

    in​_ooutlogic

    input data

    ie​_iinlogic

    input enable

    out​_iinlogic

    output data

    oe​_iinlogic

    output enable

    attr​_iin[AttrDw-1:0] logic

    additional attributes

    warl​_oout[AttrDw-1:0] logic

    Block Diagram

    Module pwrmgr​_cdc

    This design unit is implemented in pwrmgr​_cdc.sv

    This file depends on: prim_flop_2sync.sv, prim_pulse_sync.sv, pwrmgr_reg_pkg.sv, pwrmgr_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_slow​_iinlogic

    Clocks and resets

    clk​_iinlogic
    rst​_slow​_niinlogic
    rst​_niinlogic
    slow​_req​_pwrup​_iinlogic

    slow domain signals,

    slow​_ack​_pwrdn​_iinlogic
    slow​_pwrup​_cause​_toggle​_iinlogic
    slow​_pwrup​_cause​_iinpwrup_cause_e
    slow​_wakeup​_en​_oout[NumWkups-1:0] logic
    slow​_reset​_en​_oout[NumRstReqs-1:0] logic
    slow​_main​_pd​_nooutlogic
    slow​_io​_clk​_en​_ooutlogic
    slow​_core​_clk​_en​_ooutlogic
    slow​_usb​_clk​_en​_lp​_ooutlogic
    slow​_usb​_clk​_en​_active​_ooutlogic
    slow​_req​_pwrdn​_ooutlogic
    slow​_ack​_pwrup​_ooutlogic
    slow​_ast​_ooutpwr_ast_rsp_t
    slow​_peri​_reqs​_ooutpwr_peri_t
    slow​_peri​_reqs​_masked​_iinpwr_peri_t
    req​_pwrdn​_iinlogic

    fast domain signals

    ack​_pwrup​_iinlogic
    cfg​_cdc​_sync​_iinlogic
    wakeup​_en​_iin[NumWkups-1:0] logic
    reset​_en​_iin[NumRstReqs-1:0] logic
    main​_pd​_niinlogic
    io​_clk​_en​_iinlogic
    core​_clk​_en​_iinlogic
    usb​_clk​_en​_lp​_iinlogic
    usb​_clk​_en​_active​_iinlogic
    ack​_pwrdn​_ooutlogic
    req​_pwrup​_ooutlogic
    pwrup​_cause​_ooutpwrup_cause_e
    peri​_reqs​_ooutpwr_peri_t
    cdc​_sync​_done​_ooutlogic
    peri​_iinpwr_peri_t

    peripheral inputs, mixed domains

    flash​_iinpwr_flash_rsp_t
    flash​_ooutpwr_flash_rsp_t
    otp​_iinpwr_otp_rsp_t

    otp interface

    otp​_ooutpwr_otp_rsp_t
    ast​_iinpwr_ast_rsp_t

    AST inputs, unknown domain

    Instantiations

    Block Diagram

    Module pwrmgr​_fsm

    This design unit is implemented in pwrmgr​_fsm.sv

    This file depends on: prim_flop.sv, uvm_pkg.sv, pwrmgr_reg_pkg.sv, pwrmgr_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    OffDomainSelStartintALWAYS_ON_DOMAIN + 1

    when there are multiple on domains, the latter 1 should become another parameter

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_pwrup​_iinlogic

    interface with slow_fsm

    pwrup​_cause​_iinpwrup_cause_e
    ack​_pwrup​_ooutlogic
    req​_pwrdn​_ooutlogic
    ack​_pwrdn​_iinlogic
    low​_power​_entry​_iinlogic
    main​_pd​_niinlogic
    reset​_reqs​_iin[NumRstReqs:0] logic
    wkup​_ooutlogic

    generate wake interrupt

    wkup​_record​_ooutlogic

    enable wakeup recording

    fall​_through​_ooutlogic
    abort​_ooutlogic
    clr​_hint​_ooutlogic
    clr​_cfg​_lock​_ooutlogic
    pwr​_rst​_ooutpwr_rst_req_t

    rstmgr

    pwr​_rst​_iinpwr_rst_rsp_t
    ips​_clk​_en​_ooutlogic

    clkmgr

    clk​_en​_status​_iinlogic
    otp​_init​_ooutlogic

    otp

    otp​_done​_iinlogic
    otp​_idle​_iinlogic
    lc​_init​_ooutlogic

    lc

    lc​_done​_iinlogic
    lc​_idle​_iinlogic
    flash​_init​_ooutlogic

    flash

    flash​_done​_iinlogic
    flash​_idle​_iinlogic

    Instantiations

    Block Diagram

    State Machines

    Module pwrmgr​_reg​_top

    This design unit is implemented in pwrmgr​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, pwrmgr_reg_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint6
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutpwrmgr_reg2hw_t

    Write

    hw2reginpwrmgr_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module pwrmgr​_slow​_fsm

    This design unit is implemented in pwrmgr​_slow​_fsm.sv

    This file depends on: pwrmgr_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wakeup​_iinlogic

    sync'ed requests from peripherals

    reset​_req​_iinlogic
    req​_pwrup​_ooutlogic

    interface with fast fsm

    pwrup​_cause​_toggle​_ooutlogic
    pwrup​_cause​_ooutpwrup_cause_e
    ack​_pwrup​_iinlogic
    req​_pwrdn​_iinlogic
    ack​_pwrdn​_ooutlogic
    main​_pd​_niinlogic

    low power entry configuration

    io​_clk​_en​_iinlogic
    core​_clk​_en​_iinlogic
    usb​_clk​_en​_lp​_iinlogic
    usb​_clk​_en​_active​_iinlogic
    ast​_iinpwr_ast_rsp_t

    AST interface

    ast​_ooutpwr_ast_req_t

    Block Diagram

    State Machines

    Module pwrmgr​_wake​_info

    This design unit is implemented in pwrmgr​_wake​_info.sv

    This file depends on: pwrmgr_reg_pkg.sv, pwrmgr_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wr​_iinlogic
    data​_iin[TotalWakeWidth-1:0] logic
    start​_capture​_iinlogic
    record​_dis​_iinlogic
    wakeups​_iin[NumWkups-1:0] logic
    fall​_through​_iinlogic
    abort​_iinlogic
    info​_oout[TotalWakeWidth-1:0] logic

    Block Diagram

    Module rng​_osc

    This design unit is implemented in rng​_osc.sv

    Description

    of rng_osc

    Parameters

    NameTypeDefault ValueDescription
    RNG​_EN​_RDLYtime5us

    Ports

    NameDirectionTypeDescription
    vcaon​_pok​_iinlogic

    VCAON POK @1.1V

    rng​_en​_iinlogic

    RNG Source Clock Enable

    rng​_clk​_ooutlogic

    RNG Clock Output

    Block Diagram

    Module rstmgr​_crash​_info

    This design unit is implemented in rstmgr​_crash​_info.sv

    This file depends on: uvm_pkg.sv, rstmgr_pkg.sv, rstmgr_reg_pkg.sv

    Description

    rstmgr_crash_info

    Parameters

    NameTypeDefault ValueDescription
    CrashDumpWidthint32
    CrashRemainderintCrashDumpWidth % RdWidth > 0 ? 1 : 0
    CrashStoreSlotintCrashDumpWidth / RdWidth + CrashRemainder
    SlotCntWidthint$clog2(CrashStoreSlot)
    TotalWidthintCrashStoreSlot * RdWidth

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    dump​_iin[CrashDumpWidth-1:0] logic
    dump​_capture​_iinlogic
    slot​_sel​_iin[IdxWidth-1:0] logic
    slots​_cnt​_oout[IdxWidth-1:0] logic
    slot​_oout[RdWidth-1:0] logic

    Block Diagram

    Module rstmgr​_ctrl

    This design unit is implemented in rstmgr​_ctrl.sv

    This file depends on: prim_flop.sv, prim_flop_2sync.sv, rstmgr_pkg.sv

    Description

    rstmgr_ctrl

    Parameters

    NameTypeDefault ValueDescription
    PowerDomainsint2
    OffDomainsintPowerDomains - 1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    rst​_req​_iin[PowerDomains-1:0] logic
    rst​_parent​_niin[PowerDomains-1:0] logic

    parent reset

    rst​_noout[PowerDomains-1:0] logic

    Instantiations

    Block Diagram

    Module rstmgr​_por

    This design unit is implemented in rstmgr​_por.sv

    This file depends on: prim_flop.sv, prim_flop_2sync.sv, prim_clock_mux2.sv

    Description

    rstmgr_por

    Parameters

    NameTypeDefault ValueDescription
    FilterStagesint3
    StretchCountint32
    CtrWidthint$clog2(StretchCount+1)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    scan​_rst​_niinlogic
    scanmode​_iinlogic
    rst​_nooutlogic

    Instantiations

    Block Diagram

    Package rstmgr​_reg​_pkg

    This design unit is implemented in rstmgr​_reg​_pkg.sv

    Module rstmgr​_reg​_top

    This design unit is implemented in rstmgr​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, rstmgr_reg_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint6
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutrstmgr_reg2hw_t

    Write

    hw2reginrstmgr_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module rv​_plic​_gateway

    This design unit is implemented in rv​_plic​_gateway.sv

    Parameters

    NameTypeDefault ValueDescription
    N​_SOURCEint32

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    src​_iin[N_SOURCE-1:0] logic
    le​_iin[N_SOURCE-1:0] logic

    Level0 Edge1

    claim​_iin[N_SOURCE-1:0] logic

    $onehot0(claim_i)

    complete​_iin[N_SOURCE-1:0] logic

    $onehot0(complete_i)

    ip​_oout[N_SOURCE-1:0] logic

    Block Diagram

    Package rv​_plic​_reg​_pkg

    This design unit is implemented in rv​_plic​_reg​_pkg.sv

    Module rv​_plic​_reg​_top

    This design unit is implemented in rv​_plic​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, rv_plic_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint10
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutrv_plic_reg2hw_t

    Write

    hw2reginrv_plic_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module rv​_plic​_target

    This design unit is implemented in rv​_plic​_target.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    N​_SOURCEint32
    MAX​_PRIOint7
    SrcWidthint$clog2(N_SOURCE+1)

    derived parameter

    PrioWidthint$clog2(MAX_PRIO+1)

    derived parameter

    NumLevelsint$clog2(N_SOURCE)

    align to powers of 2 for simplicity a full binary tree with N levels has 2N + 2N-1 nodes

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    ip​_iin[N_SOURCE-1:0] logic
    ie​_iin[N_SOURCE-1:0] logic
    prio​_iin[PrioWidth-1:0] logic [N_SOURCE]
    threshold​_iin[PrioWidth-1:0] logic
    irq​_ooutlogic
    irq​_id​_oout[SrcWidth-1:0] logic

    Block Diagram

    Package rv​_timer​_reg​_pkg

    This design unit is implemented in rv​_timer​_reg​_pkg.sv

    Module rv​_timer​_reg​_top

    This design unit is implemented in rv​_timer​_reg​_top.sv

    This file depends on: rv_timer_reg_pkg.sv, prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint9
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutrv_timer_reg2hw_t

    Write

    hw2reginrv_timer_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Package sensor​_ctrl​_pkg

    This design unit is implemented in sensor​_ctrl​_pkg.sv

    This file depends on: sensor_ctrl_reg_pkg.sv

    Description

    sensor_ctrl_pkg

    Module sensor​_ctrl​_reg​_top

    This design unit is implemented in sensor​_ctrl​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, sensor_ctrl_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint5
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutsensor_ctrl_reg2hw_t

    Write

    hw2reginsensor_ctrl_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module sha2

    This design unit is implemented in sha2.sv

    This file depends on: hmac_pkg.sv, sha2_pad.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wipe​_secretinlogic
    wipe​_vinsha_word_t
    fifo​_rvalidinlogic

    FIFO read signal

    fifo​_rdatainsha_fifo_t
    fifo​_rreadyoutlogic
    sha​_eninlogic

    If disabled, it clears internal content.

    hash​_startinlogic
    hash​_processinlogic
    hash​_doneoutlogic
    message​_lengthin[63:0] logic

    bits but byte based

    digestout[7:0] sha_word_t

    Instantiations

    Block Diagram

    State Machines

    Module sha3

    This design unit is implemented in sha3.sv

    This file depends on: uvm_pkg.sv, sha3_pkg.sv, sha3pad.sv, keccak_round.sv

    Parameters

    NameTypeDefault ValueDescription
    EnMaskingbit0

    Enable Masked Keccak if 1

    Shareint(EnMasking) ? 2 : 1

    derived parameter

    ReuseSharebit0

    Configurations Decide if implements Re-use the adjacent shares as entropy in DOM AND logic

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    msg​_valid​_iinlogic

    MSG interface

    msg​_data​_iin[MsgWidth-1:0] logic [Share]
    msg​_strb​_iin[MsgStrbW-1:0] logic

    one strobe for shares

    msg​_ready​_ooutlogic
    rand​_valid​_iinlogic

    Entropy interface

    rand​_data​_iin[StateW-1:0] logic
    rand​_consumed​_ooutlogic
    ns​_data​_iin[NSRegisterSize*8-1:0] logic

    See sha3_pkg for details

    mode​_iinsha3_mode_e

    see sha3pad for details

    strength​_iinkeccak_strength_e

    see sha3pad for details

    start​_iinlogic

    see sha3pad for details

    process​_iinlogic

    see sha3pad for details

    run​_iinlogic

    run_i is a pulse signal to trigger the keccak_round manually by SW. It is used to run additional keccak_f after sponge absorbing is completed. See keccak_run signal

    done​_iinlogic

    see sha3pad for details

    absorbed​_ooutlogic
    squeezing​_ooutlogic
    block​_processed​_ooutlogic

    Indicate of one block processed. KMAC main state tracks the progression based on this signal.

    sha3​_fsm​_ooutsha3_st_e
    state​_valid​_ooutlogic

    digest output This value is valid only after all absorbing process is completed. In invalid state, the output state will be zero to prevent information leakage.

    state​_oout[StateW-1:0] logic [Share]
    error​_oouterr_t

    error_o value is pushed to Error FIFO at KMAC/SHA3 top and reported to SW

    Instantiations

    Block Diagram

    State Machines

    Package sha3​_pkg

    This design unit is implemented in sha3​_pkg.sv

    Package spi​_device​_pkg

    This design unit is implemented in spi​_device​_pkg.sv

    This file depends on: spi_device_reg_pkg.sv

    Package spi​_device​_reg​_pkg

    This design unit is implemented in spi​_device​_reg​_pkg.sv

    Module spi​_device​_reg​_top

    This design unit is implemented in spi​_device​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, spi_device_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint13
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    tl​_win​_oouttl_h2d_t [1]

    Output port for window

    tl​_win​_iintl_d2h_t [1]
    reg2hwoutspi_device_reg2hw_t

    Write

    hw2reginspi_device_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module spi​_fwm​_rxf​_ctrl

    This design unit is implemented in spi​_fwm​_rxf​_ctrl.sv

    Parameters

    NameTypeDefault ValueDescription
    FifoDwint8
    SramAwint11
    SramDwint32
    NumBytesintSramDw/FifoDw

    derived parameter

    SDWint$clog2(NumBytes)

    derived parameter

    PtrWintSramAw + SDW + 1

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    base​_index​_iin[SramAw-1:0] logic

    Configuration

    limit​_index​_iin[SramAw-1:0] logic
    timer​_vin[7:0] logic
    rptrin[PtrW-1:0] logic
    wptrout[PtrW-1:0] logic
    depthout[PtrW-1:0] logic
    fulloutlogic
    fifo​_validinlogic
    fifo​_readyoutlogic
    fifo​_rdatain[FifoDw-1:0] logic
    sram​_reqoutlogic
    sram​_writeoutlogic
    sram​_addrout[SramAw-1:0] logic
    sram​_wdataout[SramDw-1:0] logic
    sram​_gntinlogic
    sram​_rvalidinlogic
    sram​_rdatain[SramDw-1:0] logic
    sram​_errorin[1:0] logic

    Block Diagram

    State Machines

    Module spi​_fwm​_txf​_ctrl

    This design unit is implemented in spi​_fwm​_txf​_ctrl.sv

    Parameters

    NameTypeDefault ValueDescription
    FifoDwint8
    SramAwint11
    SramDwint32
    NumBytesintSramDw/FifoDw

    derived parameter

    SDWint$clog2(NumBytes)

    derived parameter

    PtrWintSramAw + SDW + 1

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    base​_index​_iin[SramAw-1:0] logic

    Configuration

    limit​_index​_iin[SramAw-1:0] logic
    abortinlogic

    Abort State Machine if TX Async at stuck

    wptrin[PtrW-1:0] logic
    rptrout[PtrW-1:0] logic
    depthout[PtrW-1:0] logic
    fifo​_validoutlogic
    fifo​_readyinlogic
    fifo​_wdataout[FifoDw-1:0] logic
    sram​_reqoutlogic
    sram​_writeoutlogic
    sram​_addrout[SramAw-1:0] logic
    sram​_wdataout[SramDw-1:0] logic
    sram​_gntinlogic
    sram​_rvalidinlogic
    sram​_rdatain[SramDw-1:0] logic
    sram​_errorin[1:0] logic

    Block Diagram

    State Machines

    Module spi​_fwmode

    This design unit is implemented in spi​_fwmode.sv

    This file depends on: spi_device_pkg.sv

    Ports

    NameDirectionTypeDescription
    mode​_iinspi_mode_e

    Only works at mode_i == FwMode

    rx​_wvalid​_ooutlogic

    RX, TX FIFO interface

    rx​_wready​_iinlogic
    rx​_data​_ooutspi_byte_t
    tx​_rvalid​_iinlogic
    tx​_rready​_ooutlogic
    tx​_data​_iinspi_byte_t
    rx​_overflow​_ooutlogic
    tx​_underflow​_ooutlogic
    rx​_data​_valid​_iinlogic

    Serial to Parallel

    rx​_data​_iinspi_byte_t
    io​_mode​_ooutio_mode_e
    tx​_wvalid​_ooutlogic

    Parallel to SPI

    tx​_data​_ooutspi_byte_t
    tx​_wready​_iinlogic

    Block Diagram

    Package spi​_host​_reg​_pkg

    This design unit is implemented in spi​_host​_reg​_pkg.sv

    Module spi​_host​_reg​_top

    This design unit is implemented in spi​_host​_reg​_top.sv

    This file depends on: prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, spi_host_reg_pkg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint2
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutspi_host_reg2hw_t

    Write

    hw2reginspi_host_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module spi​_p2s

    This design unit is implemented in spi​_p2s.sv

    This file depends on: uvm_pkg.sv, spi_device_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Bitsint$bits(spi_byte_t)
    BitWidthint$clog2(Bits)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    data​_valid​_iinlogic

    Input byte interface

    data​_iinspi_byte_t
    data​_sent​_ooutlogic
    csb​_iinlogic

    for line floating

    s​_en​_oout[3:0] logic
    s​_oout[3:0] logic
    cpha​_iinlogic

    Configuration If CPHA=1, then the first byte should be delayed. But this does not matter in SPI Flash. Only applicable to Generic mode

    order​_iinlogic

    Control txorder: controls which bit goes out first.

    io​_mode​_iinio_mode_e

    IO mode

    Block Diagram

    Module spi​_s2p

    This design unit is implemented in spi​_s2p.sv

    This file depends on: uvm_pkg.sv, spi_device_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Lengthint8 + 32 + 8 + 2048

    Definitions //

    Maximum Length of a transaction is: 8 bit opcode + 24 or 32 bit address + max 8 bit dummy cycle + 256B payload

    BitCntWint$clog2(Length+1)
    Bitsint$bits(spi_byte_t)
    BitWidthint$clog2(Bits)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic

    inverted CSb input

    s​_iin[3:0] logic

    SPI data

    data​_valid​_ooutlogic

    to following logic

    data​_ooutspi_byte_t
    bitcnt​_oout[11:0] logic

    up to 256B payload

    order​_iinlogic

    Configuration

    io​_mode​_iinio_mode_e

    Block Diagram

    Package sram​_ctrl​_reg​_pkg

    This design unit is implemented in sram​_ctrl​_reg​_pkg.sv

    Module sram​_ctrl​_reg​_top

    This design unit is implemented in sram​_ctrl​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, sram_ctrl_reg_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint5
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutsram_ctrl_reg2hw_t

    Write

    hw2reginsram_ctrl_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module sys​_osc

    This design unit is implemented in sys​_osc.sv

    Description

    of sys_osc

    Parameters

    NameTypeDefault ValueDescription
    SYS​_EN​_RDLYtime5us
    SysClkPeriodreal10000

    10000ps (100Mhz)

    Ports

    NameDirectionTypeDescription
    vcore​_pok​_h​_iinlogic

    VCORE POK @3.3V

    sys​_en​_iinlogic

    System Source Clock Enable

    sys​_jen​_iinlogic

    System Source Clock Jitter Enable

    sys​_clk​_ooutlogic

    System Clock Output

    Block Diagram

    Module timer​_core

    This design unit is implemented in timer​_core.sv

    Parameters

    NameTypeDefault ValueDescription
    Nint1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    activeinlogic
    prescalerin[11:0] logic
    stepin[7:0] logic
    tickoutlogic
    mtime​_dout[63:0] logic
    mtimein[63:0] logic
    mtimecmpin[63:0] logic [N]
    introut[N-1:0] logic

    Block Diagram

    Package tl​_peri​_pkg

    This design unit is implemented in tl​_peri​_pkg.sv

    Module tlul​_adapter​_host

    This design unit is implemented in tlul​_adapter​_host.sv

    This file depends on: prim_secded_64_57_enc.sv, uvm_pkg.sv, top_pkg.sv, tlul_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    MAX​_REQSint2
    WordSizeint$clog2(top_pkg::TL_DBW)
    OutstandingReqCntWint(MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_iinlogic
    gnt​_ooutlogic
    addr​_iin[top_pkg::TL_AW-1:0] logic
    we​_iinlogic
    wdata​_iin[top_pkg::TL_DW-1:0] logic
    be​_iin[top_pkg::TL_DBW-1:0] logic
    type​_iintl_type_e
    valid​_ooutlogic
    rdata​_oout[top_pkg::TL_DW-1:0] logic
    err​_ooutlogic
    tl​_oouttl_h2d_t
    tl​_iintl_d2h_t

    Instantiations

    Block Diagram

    Module tlul​_adapter​_reg

    This design unit is implemented in tlul​_adapter​_reg.sv

    This file depends on: tlul_err.sv, uvm_pkg.sv, top_pkg.sv, tlul_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    RegAwint8
    RegDwint32

    Shall be matched with TL_DW

    RegBwintRegDw/8
    IWint$bits(tl_i.a_source)
    SZWint$bits(tl_i.a_size)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    TL-UL interface

    tl​_oouttl_d2h_t
    re​_ooutlogic

    Register interface

    we​_ooutlogic
    addr​_oout[RegAw-1:0] logic
    wdata​_oout[RegDw-1:0] logic
    be​_oout[RegBw-1:0] logic
    rdata​_iin[RegDw-1:0] logic
    error​_iinlogic

    Instantiations

    Block Diagram

    Module tlul​_err

    This design unit is implemented in tlul​_err.sv

    This file depends on: uvm_pkg.sv, tlul_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    IWint$bits(tl_i.a_source)
    SZWint$bits(tl_i.a_size)
    DWint$bits(tl_i.a_data)
    MWint$bits(tl_i.a_mask)
    SubAWint$clog2(DW/8)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t
    err​_ooutlogic

    Block Diagram

    Module tlul​_fifo​_async

    This design unit is implemented in tlul​_fifo​_async.sv

    This file depends on: uvm_pkg.sv, tlul_pkg.sv, prim_fifo_async.sv

    Parameters

    NameTypeDefault ValueDescription
    ReqDepthint3
    RspDepthint3
    REQFIFO​_WIDTHint$bits(tlul_pkg::tl_h2d_t)-2

    Put everything on the request side into one FIFO

    RSPFIFO​_WIDTHint$bits(tlul_pkg::tl_d2h_t) -2

    Ports

    NameDirectionTypeDescription
    clk​_h​_iinlogic
    rst​_h​_niinlogic
    clk​_d​_iinlogic
    rst​_d​_niinlogic
    tl​_h​_iintl_h2d_t
    tl​_h​_oouttl_d2h_t
    tl​_d​_oouttl_h2d_t
    tl​_d​_iintl_d2h_t

    Instantiations

    Block Diagram

    Module tlul​_fifo​_sync

    This design unit is implemented in tlul​_fifo​_sync.sv

    This file depends on: top_pkg.sv, prim_fifo_sync.sv, tlul_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    ReqPassbit1'b1
    RspPassbit1'b1
    ReqDepthint2
    RspDepthint2
    SpareReqWint1
    SpareRspWint1
    REQFIFO​_WIDTHint$bits(tlul_pkg::tl_h2d_t) -2 + SpareReqW

    Put everything on the request side into one FIFO

    RSPFIFO​_WIDTHint$bits(tlul_pkg::tl_d2h_t) -2 + SpareRspW

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_h​_iintl_h2d_t
    tl​_h​_oouttl_d2h_t
    tl​_d​_oouttl_h2d_t
    tl​_d​_iintl_d2h_t
    spare​_req​_iin[SpareReqW-1:0] logic
    spare​_req​_oout[SpareReqW-1:0] logic
    spare​_rsp​_iin[SpareRspW-1:0] logic
    spare​_rsp​_oout[SpareRspW-1:0] logic

    Instantiations

    Block Diagram

    Module tlul​_socket​_1n

    This design unit is implemented in tlul​_socket​_1n.sv

    This file depends on: tlul_err_resp.sv, uvm_pkg.sv, top_pkg.sv, tlul_pkg.sv, tlul_fifo_sync.sv

    Parameters

    NameTypeDefault ValueDescription
    Nint4
    HReqPassbit1'b1
    HRspPassbit1'b1
    DReqPass[N-1:0] bit{N{1'b1}}
    DRspPass[N-1:0] bit{N{1'b1}}
    HReqDepth[3:0] bit4'h2
    HRspDepth[3:0] bit4'h2
    DReqDepth[N*4-1:0] bit{N{4'h2}}
    DRspDepth[N*4-1:0] bit{N{4'h2}}
    NWDint$clog2(N+1)

    derived parameter

    MaxOutstandingint2**top_pkg::TL_AIW

    Up to 256 ounstanding

    OutstandingWint$clog2(MaxOutstanding+1)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_h​_iintl_h2d_t
    tl​_h​_oouttl_d2h_t
    tl​_d​_oouttl_h2d_t [N]
    tl​_d​_iintl_d2h_t [N]
    dev​_select​_iin[NWD-1:0] logic

    Instantiations

    Block Diagram

    Module tlul​_socket​_m1

    This design unit is implemented in tlul​_socket​_m1.sv

    This file depends on: uvm_pkg.sv, prim_arbiter_ppc.sv, top_pkg.sv, tlul_pkg.sv, tlul_fifo_sync.sv, prim_arbiter_tree.sv

    Parameters

    NameTypeDefault ValueDescription
    Mint4
    HReqPass[M-1:0] bit{M{1'b1}}
    HRspPass[M-1:0] bit{M{1'b1}}
    HReqDepth[M*4-1:0] bit{M{4'h2}}
    HRspDepth[M*4-1:0] bit{M{4'h2}}
    DReqPassbit1'b1
    DRspPassbit1'b1
    DReqDepth[3:0] bit4'h2
    DRspDepth[3:0] bit4'h2
    IDWinttop_pkg::TL_AIW

    Signals

    tl_h_i/o0 | tl_h_i/o1 | ... | tl_h_i/oM-1 | | | u_hostfifo0 u_hostfifo1 u_hostfifoM-1 | | | hreq_fifo_o(i) / hrsp_fifo_i(i)

    Required ID width to distinguish between host ports Used in response steering

    STIDWint$clog2(M)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_h​_iintl_h2d_t [M]
    tl​_h​_oouttl_d2h_t [M]
    tl​_d​_oouttl_h2d_t
    tl​_d​_iintl_d2h_t

    Instantiations

    Block Diagram

    Module uart​_core

    This design unit is implemented in uart​_core.sv

    This file depends on: prim_flop_2sync.sv, uart_tx.sv, uart_reg_pkg.sv, prim_fifo_sync.sv, uart_rx.sv, prim_intr_hw.sv

    Parameters

    NameTypeDefault ValueDescription
    NcoWidthint$bits(reg2hw.ctrl.nco.q)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    reg2hwinuart_reg2hw_t
    hw2regoutuart_hw2reg_t
    rxinlogic
    txoutlogic
    intr​_tx​_watermark​_ooutlogic
    intr​_rx​_watermark​_ooutlogic
    intr​_tx​_empty​_ooutlogic
    intr​_rx​_overflow​_ooutlogic
    intr​_rx​_frame​_err​_ooutlogic
    intr​_rx​_break​_err​_ooutlogic
    intr​_rx​_timeout​_ooutlogic
    intr​_rx​_parity​_err​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Package uart​_reg​_pkg

    This design unit is implemented in uart​_reg​_pkg.sv

    Module uart​_reg​_top

    This design unit is implemented in uart​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, uart_reg_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint6
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutuart_reg2hw_t

    Write

    hw2reginuart_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module usb​_osc

    This design unit is implemented in usb​_osc.sv

    Description

    of usb_osc

    Parameters

    NameTypeDefault ValueDescription
    USB​_EN​_RDLYtime5us
    USB​_VAL​_RDLYtime80ns
    USB​_VAL​_FDLYtime80ns
    UsbClkPeriodreal1000000/48

    ~20833.33333ps (48Mhz)

    Ports

    NameDirectionTypeDescription
    vcore​_pok​_h​_iinlogic

    VCORE POK @3.3V

    usb​_en​_iinlogic

    USB Source Clock Enable

    usb​_ref​_val​_iinlogic

    USB Reference Valid

    usb​_clk​_ooutlogic

    USB Clock Output

    Block Diagram

    Module usbdev​_aon​_wake

    This design unit is implemented in usbdev​_aon​_wake.sv

    This file depends on: usbdev_pkg.sv, prim_flop_2sync.sv, prim_filter.sv

    Ports

    NameDirectionTypeDescription
    clk​_aon​_iinlogic
    rst​_aon​_niinlogic
    usb​_out​_of​_rst​_alw​_iinlogic

    signals tagged upwr are only valid when this is set

    usb​_dp​_async​_alw​_iinlogic

    These come from the chip pin

    usb​_dn​_async​_alw​_iinlogic
    usb​_dppullup​_en​_alw​_iinlogic

    These come from post pinmux sleep handling logic

    usb​_dnpullup​_en​_alw​_iinlogic
    usb​_aon​_wake​_en​_upwr​_iinlogic

    Register signals from IP

    usb​_aon​_woken​_upwr​_iinlogic
    usb​_suspended​_upwr​_iinlogic

    Status from IP, must be valid for long enough for aon clock to catch (>15us)

    wake​_req​_alw​_ooutlogic

    wake/powerup request

    state​_debug​_ooutawk_state_e

    state debug information

    Instantiations

    Block Diagram

    State Machines

    Module usbdev​_flop​_2syncpulse

    This design unit is implemented in usbdev​_flop​_2syncpulse.sv

    This file depends on: prim_flop_2sync.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint16

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    receive clock

    rst​_niinlogic
    d​_iin[Width-1:0] logic
    q​_oout[Width-1:0] logic

    Instantiations

    Block Diagram

    Module usbdev​_iomux

    This design unit is implemented in usbdev​_iomux.sv

    This file depends on: usbdev_reg_pkg.sv, prim_flop_2sync.sv, prim_generic_clock_mux2.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    clk​_usb​_48mhz​_iinlogic

    use usb_ prefix for signals in this clk

    rst​_usb​_48mhz​_niinlogic
    sys​_hw2reg​_sense​_ooutusbdev_hw2reg_phy_pins_sense_reg_t

    Register interface (system clk)

    sys​_reg2hw​_drive​_iinusbdev_reg2hw_phy_pins_drive_reg_t
    sys​_reg2hw​_config​_iinusbdev_reg2hw_phy_config_reg_t
    sys​_usb​_sense​_ooutlogic
    cio​_usb​_d​_iinlogic

    External USB Interface(s) (async)

    cio​_usb​_dp​_iinlogic
    cio​_usb​_dn​_iinlogic
    cio​_usb​_d​_ooutlogic
    cio​_usb​_se0​_ooutlogic
    cio​_usb​_dp​_ooutlogic
    cio​_usb​_dn​_ooutlogic
    cio​_usb​_oe​_ooutlogic
    cio​_usb​_tx​_mode​_se​_ooutlogic
    cio​_usb​_sense​_iinlogic
    cio​_usb​_dp​_pullup​_en​_ooutlogic
    cio​_usb​_dn​_pullup​_en​_ooutlogic
    cio​_usb​_suspend​_ooutlogic
    usb​_rx​_d​_ooutlogic

    Internal USB Interface (usb clk)

    usb​_rx​_dp​_ooutlogic
    usb​_rx​_dn​_ooutlogic
    usb​_tx​_d​_iinlogic
    usb​_tx​_se0​_iinlogic
    usb​_tx​_oe​_iinlogic
    usb​_pwr​_sense​_ooutlogic
    usb​_pullup​_en​_iinlogic
    usb​_suspend​_iinlogic

    Instantiations

    Block Diagram

    Package usbdev​_reg​_pkg

    This design unit is implemented in usbdev​_reg​_pkg.sv

    Module usbdev​_reg​_top

    This design unit is implemented in usbdev​_reg​_top.sv

    This file depends on: usbdev_reg_pkg.sv, prim_subreg_ext.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv, tlul_socket_1n.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint12
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    tl​_win​_oouttl_h2d_t [1]

    Output port for window

    tl​_win​_iintl_d2h_t [1]
    reg2hwoutusbdev_reg2hw_t

    Write

    hw2reginusbdev_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module usbdev​_usbif

    This design unit is implemented in usbdev​_usbif.sv

    This file depends on: usbdev_linkstate.sv, usb_fs_nb_pe.sv

    Description

    This module runs on the 48MHz USB clock

    Parameters

    NameTypeDefault ValueDescription
    NEndpointsint12
    AVFifoWidthint4
    RXFifoWidthint4
    MaxPktSizeByteint64
    NBufint4
    SramAwint4
    NBufWidthint$clog2(NBuf)

    derived parameter

    PktWint$clog2(MaxPktSizeByte)

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_48mhz​_iinlogic

    48MHz USB clock

    rst​_niinlogic
    usb​_d​_iinlogic

    Pins (synchronous)

    usb​_dp​_iinlogic
    usb​_dn​_iinlogic
    usb​_d​_ooutlogic
    usb​_se0​_ooutlogic
    usb​_oe​_ooutlogic
    usb​_pullup​_en​_ooutlogic
    usb​_sense​_iinlogic
    rx​_setup​_iin[NEndpoints-1:0] logic

    receive (OUT or SETUP) side

    rx​_out​_iin[NEndpoints-1:0] logic
    rx​_stall​_iin[NEndpoints-1:0] logic
    av​_rvalid​_iinlogic
    av​_rready​_ooutlogic
    av​_rdata​_iin[AVFifoWidth - 1:0] logic
    event​_av​_empty​_ooutlogic
    rx​_wvalid​_ooutlogic
    rx​_wready​_iinlogic
    rx​_wdata​_oout[RXFifoWidth - 1:0] logic
    event​_rx​_full​_ooutlogic
    setup​_received​_ooutlogic
    out​_endpoint​_oout[3:0] logic
    out​_endpoint​_val​_ooutlogic
    in​_buf​_iin[NBufWidth - 1:0] logic

    transmit (IN) side

    in​_size​_iin[PktW:0] logic
    in​_stall​_iin[NEndpoints-1:0] logic
    in​_rdy​_iin[NEndpoints-1:0] logic
    set​_sent​_ooutlogic
    in​_endpoint​_oout[3:0] logic
    in​_endpoint​_val​_ooutlogic
    mem​_req​_ooutlogic

    memory interface

    mem​_write​_ooutlogic
    mem​_addr​_oout[SramAw-1:0] logic
    mem​_wdata​_oout[31:0] logic
    mem​_rdata​_iin[31:0] logic
    enable​_iinlogic

    control

    devaddr​_iin[6:0] logic
    clr​_devaddr​_ooutlogic
    ep​_iso​_iin[NEndpoints-1:0] logic
    cfg​_eop​_single​_bit​_iinlogic

    1: detect a single SE0 bit as EOP

    cfg​_rx​_differential​_iinlogic

    1: use differential rx data on usb_d_i

    tx​_osc​_test​_mode​_iinlogic

    Oscillator test mode: constant JK output

    data​_toggle​_clear​_iin[NEndpoints-1:0] logic

    Clear the data toggles for an EP

    frame​_start​_ooutlogic

    status

    frame​_oout[10:0] logic
    link​_state​_oout[2:0] logic
    link​_disconnect​_ooutlogic
    link​_connect​_ooutlogic
    link​_reset​_ooutlogic
    link​_active​_ooutlogic
    link​_suspend​_ooutlogic
    link​_resume​_ooutlogic
    link​_in​_err​_ooutlogic
    link​_out​_err​_ooutlogic
    host​_lost​_ooutlogic
    rx​_crc​_err​_ooutlogic
    rx​_pid​_err​_ooutlogic
    rx​_bitstuff​_err​_ooutlogic

    Instantiations

    Block Diagram

    Module aes​_cipher​_core

    This design unit is implemented in aes​_cipher​_core.sv

    This file depends on: aes_mix_columns.sv, aes_sel_buf_chk.sv, uvm_pkg.sv, aes_prng_masking.sv, aes_sub_bytes.sv, aes_cipher_control.sv, aes_shift_rows.sv, aes_pkg.sv, aes_key_expand.sv

    Parameters

    NameTypeDefault ValueDescription
    AES192Enablebit1
    Maskingbit0
    SBoxImplsbox_impl_eSBoxImplLut
    SecAllowForcingMasksbit0
    NumSharesintMasking ? 2 : 1

    derived parameter

    RndCnstMaskingLfsrSeedmasking_lfsr_seed_tRndCnstMaskingLfsrSeedDefault
    RndCnstMskgChunkLfsrPermmskg_chunk_lfsr_perm_tRndCnstMskgChunkLfsrPermDefault
    NumChunksint128/WidthPRDClearing

    Generate clearing signals of appropriate widths.

    WidthPRDRowint4*WidthPRDSBox

    Extract randomness for masking the input data.

    The masking PRNG is used for generating both the PRD for the S-Boxes/SubBytes operation as well as for the input data masks. When using any of the masked Canright S-Box implementations, it is important that the SubBytes input masks (generated by the PRNG in Round X-1) and the SubBytes output masks (generated by the PRNG in Round X) are independent. Inside the PRNG, this is achieved by using multiple, separately re-seeded LFSR chunks and by selecting the separate LFSR chunks in alternating fashion. Since the input data masks become the SubBytes input masks in the first round, we select the same 8 bit lanes for the input data masks which are also used to form the SubBytes output mask for the masked Canright S-Box implementations, i.e., the 8 LSBs of the per S-Box PRD. In particular, we have:

    prd_masking = { prd_key_expand, ... , sb_prd4, sb_out_mask4, sb_prd0, sb_out_mask0 }

    Where sb_out_maskx contains the SubBytes output mask for byte x (when using a masked Canright S-Box implementation) and sb_prdx contains additional PRD consumed by SubBytes for byte x.

    When using a masked S-Box implementation other than Canright, we still select the 8 LSBs of the per-S-Box PRD to form the input data mask of the corresponding byte. We do this to distribute the input data masks over all LFSR chunks of the masking PRNG. We do the extraction on a row basis.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    in​_valid​_iinlogic

    Input handshake signals

    in​_ready​_ooutlogic
    out​_valid​_ooutlogic

    Output handshake signals

    out​_ready​_iinlogic
    cfg​_valid​_iinlogic

    Used for gating assertions only.

    op​_iinciph_op_e
    key​_len​_iinkey_len_e
    crypt​_iinlogic
    crypt​_ooutlogic
    dec​_key​_gen​_iinlogic
    dec​_key​_gen​_ooutlogic
    key​_clear​_iinlogic
    key​_clear​_ooutlogic
    data​_out​_clear​_iinlogic

    Re-use the cipher core muxes.

    data​_out​_clear​_ooutlogic
    alert​_ooutlogic
    prd​_clearing​_iin[WidthPRDClearing-1:0] logic

    Pseudo-random data for register clearing

    force​_zero​_masks​_iinlogic

    Useful for SCA only.

    data​_in​_mask​_oout[7:0] [3:0] [3:0] logic
    entropy​_req​_ooutlogic
    entropy​_ack​_iinlogic
    entropy​_iin[WidthPRDMasking-1:0] logic
    state​_init​_iin[7:0] [3:0] [3:0] logic [NumShares]

    I/O data & initial key

    key​_init​_iin[31:0] [7:0] logic [NumShares]
    state​_oout[7:0] [3:0] [3:0] logic [NumShares]

    Instantiations

    Block Diagram

    Module aes​_control

    This design unit is implemented in aes​_control.sv

    This file depends on: prim_flop.sv, aes_reg_status.sv, uvm_pkg.sv, aes_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    SecStartTriggerDelayint0
    StateWidthint6

    Types $ ./sparse-fsm-encode.py -d 3 -m 6 -n 6
    -s 31468618 --language=sv

    Hamming distance histogram:

    0: -- 1: -- 2: -- 3: |||||||||||||||||||| (53.33%) 4: ||||||||||||||| (40.00%) 5: || (6.67%) 6: --

    Minimum Hamming distance: 3 Maximum Hamming distance: 5

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    ctrl​_qe​_iinlogic

    Main control signals

    ctrl​_we​_ooutlogic
    ctrl​_err​_storage​_iinlogic
    op​_iinaes_op_e
    mode​_iinaes_mode_e
    cipher​_op​_iinciph_op_e
    manual​_operation​_iinlogic
    start​_iinlogic
    key​_iv​_data​_in​_clear​_iinlogic
    data​_out​_clear​_iinlogic
    prng​_reseed​_iinlogic
    mux​_sel​_err​_iinlogic
    alert​_fatal​_iinlogic
    alert​_ooutlogic
    key​_init​_qe​_iin[7:0] logic [2]

    I/O register read/write enables

    iv​_qe​_iin[3:0] logic
    data​_in​_qe​_iin[3:0] logic
    data​_out​_re​_iin[3:0] logic
    data​_in​_we​_ooutlogic
    data​_out​_we​_ooutlogic
    data​_in​_prev​_sel​_ooutdip_sel_e

    Previous input data register

    data​_in​_prev​_we​_ooutlogic
    state​_in​_sel​_ooutsi_sel_e

    Cipher I/O muxes

    add​_state​_in​_sel​_ooutadd_si_sel_e
    add​_state​_out​_sel​_ooutadd_so_sel_e
    ctr​_incr​_ooutlogic

    Counter

    ctr​_ready​_iinlogic
    ctr​_we​_iin[7:0] logic
    cipher​_in​_valid​_ooutlogic

    Cipher core control and sync

    cipher​_in​_ready​_iinlogic
    cipher​_out​_valid​_iinlogic
    cipher​_out​_ready​_ooutlogic
    cipher​_crypt​_ooutlogic
    cipher​_crypt​_iinlogic
    cipher​_dec​_key​_gen​_ooutlogic
    cipher​_dec​_key​_gen​_iinlogic
    cipher​_key​_clear​_ooutlogic
    cipher​_key​_clear​_iinlogic
    cipher​_data​_out​_clear​_ooutlogic
    cipher​_data​_out​_clear​_iinlogic
    key​_init​_sel​_ooutkey_init_sel_e

    Initial key registers

    key​_init​_we​_oout[7:0] logic [2]
    iv​_sel​_ooutiv_sel_e

    IV registers

    iv​_we​_oout[7:0] logic
    prng​_data​_req​_ooutlogic

    Pseudo-random number generator interface

    prng​_data​_ack​_iinlogic
    prng​_reseed​_req​_ooutlogic
    prng​_reseed​_ack​_iinlogic
    start​_ooutlogic

    Trigger register

    start​_we​_ooutlogic
    key​_iv​_data​_in​_clear​_ooutlogic
    key​_iv​_data​_in​_clear​_we​_ooutlogic
    data​_out​_clear​_ooutlogic
    data​_out​_clear​_we​_ooutlogic
    prng​_reseed​_ooutlogic
    prng​_reseed​_we​_ooutlogic
    output​_valid​_ooutlogic

    Status register

    output​_valid​_we​_ooutlogic
    input​_ready​_ooutlogic
    input​_ready​_we​_ooutlogic
    idle​_ooutlogic
    idle​_we​_ooutlogic
    stall​_ooutlogic
    stall​_we​_ooutlogic
    output​_lost​_iinlogic
    output​_lost​_ooutlogic
    output​_lost​_we​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module aes​_ctr

    This design unit is implemented in aes​_ctr.sv

    This file depends on: prim_flop.sv, uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    StateWidthint5

    Types $ ./sparse-fsm-encode.py -d 3 -m 3 -n 5
    -s 31468618 --language=sv

    Hamming distance histogram:

    0: -- 1: -- 2: -- 3: |||||||||||||||||||| (66.67%) 4: |||||||||| (33.33%) 5: --

    Minimum Hamming distance: 3 Maximum Hamming distance: 4

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    incr​_iinlogic
    ready​_ooutlogic
    alert​_ooutlogic
    ctr​_iin[15:0] [7:0] logic

    8 times 2 bytes

    ctr​_oout[15:0] [7:0] logic

    8 times 2 bytes

    ctr​_we​_oout[7:0] logic

    Instantiations

    Block Diagram

    State Machines

    Module aes​_prng​_clearing

    This design unit is implemented in aes​_prng​_clearing.sv

    This file depends on: uvm_pkg.sv, prim_lfsr.sv, prim_cipher_pkg.sv, aes_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint64

    At the moment we just support a width of 64.

    RndCnstLfsrSeedclearing_lfsr_seed_tRndCnstClearingLfsrSeedDefault
    RndCnstLfsrPermclearing_lfsr_perm_tRndCnstClearingLfsrPermDefault

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    data​_req​_iinlogic

    Connections to AES internals, PRNG consumers

    data​_ack​_ooutlogic
    data​_oout[Width-1:0] logic
    reseed​_req​_iinlogic
    reseed​_ack​_ooutlogic
    entropy​_req​_ooutlogic

    Connections to outer world, LFSR re-seed

    entropy​_ack​_iinlogic
    entropy​_iin[Width-1:0] logic

    Instantiations

    Block Diagram

    Module aes​_sel​_buf​_chk

    This design unit is implemented in aes​_sel​_buf​_chk.sv

    This file depends on: uvm_pkg.sv, prim_buf.sv, aes_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Numint2
    Widthint1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Used for assertions only.

    rst​_niinlogic

    Used for assertions only.

    sel​_iin[Width-1:0] logic
    sel​_oout[Width-1:0] logic
    err​_ooutlogic

    Block Diagram

    Module alert​_handler​_reg​_top

    This design unit is implemented in alert​_handler​_reg​_top.sv

    This file depends on: prim_subreg_ext.sv, alert_handler_reg_pkg.sv, prim_subreg.sv, uvm_pkg.sv, tlul_gen_payload_chk.sv, tlul_adapter_reg.sv, tlul_pkg.sv, tlul_payload_chk.sv

    Parameters

    NameTypeDefault ValueDescription
    AWint10
    DWint32
    DBWintDW/8

    Byte Width

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_iintl_h2d_t

    Below Regster interface can be changed

    tl​_oouttl_d2h_t
    reg2hwoutalert_handler_reg2hw_t

    Write

    hw2reginalert_handler_hw2reg_t

    Read

    devmode​_iinlogic

    If 1, explicit error return for unmapped register access

    Instantiations

    Block Diagram

    Module csrng​_block​_encrypt

    This design unit is implemented in csrng​_block​_encrypt.sv

    This file depends on: aes_cipher_core.sv, prim_fifo_sync.sv, aes_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    SBoxImplsbox_impl_eaes_pkg::SBoxImplLut
    Cmdint3
    StateIdint4
    BlkLenint128
    KeyLenint256
    BlkEncFifoDepthint1
    BlkEncFifoWidthintBlkLen+StateId+Cmd
    NumSharesint1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    block​_encrypt​_bypass​_iinlogic
    block​_encrypt​_enable​_iinlogic
    block​_encrypt​_lc​_hw​_debug​_not​_on​_iinlogic
    block​_encrypt​_req​_iinlogic
    block​_encrypt​_rdy​_ooutlogic
    block​_encrypt​_key​_iin[KeyLen-1:0] logic
    block​_encrypt​_v​_iin[BlkLen-1:0] logic
    block​_encrypt​_cmd​_iin[Cmd-1:0] logic
    block​_encrypt​_id​_iin[StateId-1:0] logic
    block​_encrypt​_ack​_ooutlogic
    block​_encrypt​_rdy​_iinlogic
    block​_encrypt​_cmd​_oout[Cmd-1:0] logic
    block​_encrypt​_id​_oout[StateId-1:0] logic
    block​_encrypt​_v​_oout[BlkLen-1:0] logic
    block​_encrypt​_aes​_cipher​_sm​_err​_ooutlogic
    block​_encrypt​_sfifo​_blkenc​_err​_oout[2:0] logic

    Instantiations

    Block Diagram

    Module csrng​_cmd​_stage

    This design unit is implemented in csrng​_cmd​_stage.sv

    This file depends on: csrng_pkg.sv, prim_flop.sv, prim_fifo_sync.sv

    Parameters

    NameTypeDefault ValueDescription
    CmdFifoWidthint32
    CmdFifoDepthint16
    StateIdint4
    GenBitsFifoWidthint1+128
    GenBitsFifoDepthint1
    StateWidthint6

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    cs​_enable​_iinlogic

    command in

    cmd​_stage​_vld​_iinlogic
    cmd​_stage​_shid​_iin[StateId-1:0] logic
    cmd​_stage​_bus​_iin[CmdFifoWidth-1:0] logic
    cmd​_stage​_rdy​_ooutlogic
    cmd​_arb​_req​_ooutlogic

    command to arbiter

    cmd​_arb​_sop​_ooutlogic
    cmd​_arb​_mop​_ooutlogic
    cmd​_arb​_eop​_ooutlogic
    cmd​_arb​_gnt​_iinlogic
    cmd​_arb​_bus​_oout[CmdFifoWidth-1:0] logic
    cmd​_ack​_iinlogic

    ack from core

    cmd​_ack​_sts​_iinlogic
    cmd​_stage​_ack​_ooutlogic

    ack to app i/f

    cmd​_stage​_ack​_sts​_ooutlogic
    genbits​_vld​_iinlogic

    genbits from core

    genbits​_bus​_iin[127:0] logic
    genbits​_fips​_iinlogic
    genbits​_vld​_ooutlogic

    genbits to app i/f

    genbits​_rdy​_iinlogic
    genbits​_bus​_oout[127:0] logic
    genbits​_fips​_ooutlogic
    cmd​_stage​_sfifo​_cmd​_err​_oout[2:0] logic

    error indication

    cmd​_stage​_sfifo​_genbits​_err​_oout[2:0] logic
    cmd​_stage​_sm​_err​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module csrng​_ctr​_drbg​_cmd

    This design unit is implemented in csrng​_ctr​_drbg​_cmd.sv

    This file depends on: csrng_pkg.sv, prim_fifo_sync.sv

    Parameters

    NameTypeDefault ValueDescription
    Cmdint3
    StateIdint4
    BlkLenint128
    KeyLenint256
    SeedLenint384
    CtrLenint32
    CmdreqFifoDepthint1
    CmdreqFifoWidthintKeyLen+BlkLen+CtrLen+1+2*SeedLen+StateId+Cmd
    RCStageFifoDepthint1
    RCStageFifoWidthintCtrLen+1+SeedLen+Cmd
    KeyVRCFifoDepthint1
    KeyVRCFifoWidthintKeyLen+BlkLen+CtrLen+1+SeedLen+StateId+Cmd

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    ctr​_drbg​_cmd​_enable​_iinlogic
    ctr​_drbg​_cmd​_req​_iinlogic
    ctr​_drbg​_cmd​_rdy​_ooutlogic

    ready to process the req above

    ctr​_drbg​_cmd​_ccmd​_iin[Cmd-1:0] logic

    current command

    ctr​_drbg​_cmd​_inst​_id​_iin[StateId-1:0] logic

    instantance id

    ctr​_drbg​_cmd​_entropy​_iin[SeedLen-1:0] logic

    es entropy

    ctr​_drbg​_cmd​_entropy​_fips​_iinlogic

    es entropy)fips

    ctr​_drbg​_cmd​_adata​_iin[SeedLen-1:0] logic

    additional data

    ctr​_drbg​_cmd​_key​_iin[KeyLen-1:0] logic
    ctr​_drbg​_cmd​_v​_iin[BlkLen-1:0] logic
    ctr​_drbg​_cmd​_rc​_iin[CtrLen-1:0] logic
    ctr​_drbg​_cmd​_fips​_iinlogic
    ctr​_drbg​_cmd​_ack​_ooutlogic

    final ack when update process has been completed

    ctr​_drbg​_cmd​_sts​_ooutlogic

    final ack status

    ctr​_drbg​_cmd​_rdy​_iinlogic

    ready to process the ack above

    ctr​_drbg​_cmd​_ccmd​_oout[Cmd-1:0] logic
    ctr​_drbg​_cmd​_inst​_id​_oout[StateId-1:0] logic
    ctr​_drbg​_cmd​_fips​_ooutlogic
    ctr​_drbg​_cmd​_adata​_oout[SeedLen-1:0] logic
    ctr​_drbg​_cmd​_key​_oout[KeyLen-1:0] logic
    ctr​_drbg​_cmd​_v​_oout[BlkLen-1:0] logic
    ctr​_drbg​_cmd​_rc​_oout[CtrLen-1:0] logic
    cmd​_upd​_req​_ooutlogic
    upd​_cmd​_rdy​_iinlogic
    cmd​_upd​_ccmd​_oout[Cmd-1:0] logic
    cmd​_upd​_inst​_id​_oout[StateId-1:0] logic
    cmd​_upd​_pdata​_oout[SeedLen-1:0] logic
    cmd​_upd​_key​_oout[KeyLen-1:0] logic
    cmd​_upd​_v​_oout[BlkLen-1:0] logic
    upd​_cmd​_ack​_iinlogic
    cmd​_upd​_rdy​_ooutlogic
    upd​_cmd​_ccmd​_iin[Cmd-1:0] logic
    upd​_cmd​_inst​_id​_iin[StateId-1:0] logic
    upd​_cmd​_key​_iin[KeyLen-1:0] logic
    upd​_cmd​_v​_iin[BlkLen-1:0] logic
    ctr​_drbg​_cmd​_sfifo​_cmdreq​_err​_oout[2:0] logic

    misc

    ctr​_drbg​_cmd​_sfifo​_rcstage​_err​_oout[2:0] logic
    ctr​_drbg​_cmd​_sfifo​_keyvrc​_err​_oout[2:0] logic

    Instantiations

    Block Diagram

    Module csrng​_ctr​_drbg​_gen

    This design unit is implemented in csrng​_ctr​_drbg​_gen.sv

    This file depends on: csrng_pkg.sv, prim_flop.sv, prim_fifo_sync.sv

    Parameters

    NameTypeDefault ValueDescription
    Cmdint3
    StateIdint4
    BlkLenint128
    KeyLenint256
    SeedLenint384
    CtrLenint32
    GenreqFifoDepthint1
    GenreqFifoWidthintKeyLen+BlkLen+CtrLen+1+SeedLen+StateId+Cmd
    BlkEncAckFifoDepthint1
    BlkEncAckFifoWidthintBlkLen+StateId+Cmd
    AdstageFifoDepthint1
    AdstageFifoWidthintKeyLen+BlkLen+CtrLen+1+SeedLen
    RCStageFifoDepthint1
    RCStageFifoWidthintBlkLen+CtrLen+1
    GenbitsFifoDepthint1
    GenbitsFifoWidthint1+BlkLen+KeyLen+BlkLen+CtrLen+StateId+Cmd
    StateWidthint5

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    ctr​_drbg​_gen​_enable​_iinlogic
    ctr​_drbg​_gen​_req​_iinlogic
    ctr​_drbg​_gen​_rdy​_ooutlogic

    ready to process the req above

    ctr​_drbg​_gen​_ccmd​_iin[Cmd-1:0] logic

    current command

    ctr​_drbg​_gen​_inst​_id​_iin[StateId-1:0] logic

    instantance id

    ctr​_drbg​_gen​_fips​_iinlogic

    fips

    ctr​_drbg​_gen​_adata​_iin[SeedLen-1:0] logic

    additional data

    ctr​_drbg​_gen​_key​_iin[KeyLen-1:0] logic
    ctr​_drbg​_gen​_v​_iin[BlkLen-1:0] logic
    ctr​_drbg​_gen​_rc​_iin[CtrLen-1:0] logic
    ctr​_drbg​_gen​_ack​_ooutlogic

    final ack when update process has been completed

    ctr​_drbg​_gen​_sts​_ooutlogic

    final ack status

    ctr​_drbg​_gen​_rdy​_iinlogic

    ready to process the ack above

    ctr​_drbg​_gen​_ccmd​_oout[Cmd-1:0] logic
    ctr​_drbg​_gen​_inst​_id​_oout[StateId-1:0] logic
    ctr​_drbg​_gen​_key​_oout[KeyLen-1:0] logic
    ctr​_drbg​_gen​_v​_oout[BlkLen-1:0] logic
    ctr​_drbg​_gen​_rc​_oout[CtrLen-1:0] logic
    ctr​_drbg​_gen​_bits​_oout[BlkLen-1:0] logic
    ctr​_drbg​_gen​_fips​_ooutlogic
    gen​_upd​_req​_ooutlogic

    update interface

    upd​_gen​_rdy​_iinlogic
    gen​_upd​_ccmd​_oout[Cmd-1:0] logic
    gen​_upd​_inst​_id​_oout[StateId-1:0] logic
    gen​_upd​_pdata​_oout[SeedLen-1:0] logic
    gen​_upd​_key​_oout[KeyLen-1:0] logic
    gen​_upd​_v​_oout[BlkLen-1:0] logic
    upd​_gen​_ack​_iinlogic
    gen​_upd​_rdy​_ooutlogic
    upd​_gen​_ccmd​_iin[Cmd-1:0] logic
    upd​_gen​_inst​_id​_iin[StateId-1:0] logic
    upd​_gen​_key​_iin[KeyLen-1:0] logic
    upd​_gen​_v​_iin[BlkLen-1:0] logic
    block​_encrypt​_req​_ooutlogic

    block encrypt interface

    block​_encrypt​_rdy​_iinlogic
    block​_encrypt​_ccmd​_oout[Cmd-1:0] logic
    block​_encrypt​_inst​_id​_oout[StateId-1:0] logic
    block​_encrypt​_key​_oout[KeyLen-1:0] logic
    block​_encrypt​_v​_oout[BlkLen-1:0] logic
    block​_encrypt​_ack​_iinlogic
    block​_encrypt​_rdy​_ooutlogic
    block​_encrypt​_ccmd​_iin[Cmd-1:0] logic
    block​_encrypt​_inst​_id​_iin[StateId-1:0] logic
    block​_encrypt​_v​_iin[BlkLen-1:0] logic
    ctr​_drbg​_gen​_sfifo​_gbencack​_err​_oout[2:0] logic

    misc

    ctr​_drbg​_gen​_sfifo​_grcstage​_err​_oout[2:0] logic
    ctr​_drbg​_gen​_sfifo​_ggenreq​_err​_oout[2:0] logic
    ctr​_drbg​_gen​_sfifo​_gadstage​_err​_oout[2:0] logic
    ctr​_drbg​_gen​_sfifo​_ggenbits​_err​_oout[2:0] logic
    ctr​_drbg​_gen​_sm​_err​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module csrng​_ctr​_drbg​_upd

    This design unit is implemented in csrng​_ctr​_drbg​_upd.sv

    This file depends on: prim_flop.sv, prim_fifo_sync.sv

    Parameters

    NameTypeDefault ValueDescription
    Cmdint3
    StateIdint4
    BlkLenint128
    KeyLenint256
    SeedLenint384
    CtrLenint32
    UpdReqFifoDepthint1
    UpdReqFifoWidthintKeyLen+BlkLen+SeedLen+StateId+Cmd
    BlkEncReqFifoDepthint1
    BlkEncReqFifoWidthintKeyLen+BlkLen+StateId+Cmd
    BlkEncAckFifoDepthint1
    BlkEncAckFifoWidthintBlkLen+StateId+Cmd
    PDataFifoDepthint1
    PDataFifoWidthintSeedLen
    FinalFifoDepthint1
    FinalFifoWidthintKeyLen+BlkLen+StateId+Cmd
    BlkEncStateWidthint5
    OutBlkStateWidthint6

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    ctr​_drbg​_upd​_enable​_iinlogic
    ctr​_drbg​_upd​_req​_iinlogic
    ctr​_drbg​_upd​_rdy​_ooutlogic

    ready to process the req above

    ctr​_drbg​_upd​_ccmd​_iin[Cmd-1:0] logic
    ctr​_drbg​_upd​_inst​_id​_iin[StateId-1:0] logic

    instantance id

    ctr​_drbg​_upd​_pdata​_iin[SeedLen-1:0] logic

    provided_data

    ctr​_drbg​_upd​_key​_iin[KeyLen-1:0] logic
    ctr​_drbg​_upd​_v​_iin[BlkLen-1:0] logic
    ctr​_drbg​_upd​_ccmd​_oout[Cmd-1:0] logic
    ctr​_drbg​_upd​_inst​_id​_oout[StateId-1:0] logic
    ctr​_drbg​_upd​_key​_oout[KeyLen-1:0] logic
    ctr​_drbg​_upd​_v​_oout[BlkLen-1:0] logic
    ctr​_drbg​_upd​_ack​_ooutlogic

    final ack when update process has been completed

    ctr​_drbg​_upd​_rdy​_iinlogic

    readu to process the ack above

    block​_encrypt​_req​_ooutlogic
    block​_encrypt​_rdy​_iinlogic
    block​_encrypt​_ccmd​_oout[Cmd-1:0] logic
    block​_encrypt​_inst​_id​_oout[StateId-1:0] logic
    block​_encrypt​_key​_oout[KeyLen-1:0] logic
    block​_encrypt​_v​_oout[BlkLen-1:0] logic
    block​_encrypt​_ack​_iinlogic
    block​_encrypt​_rdy​_ooutlogic
    block​_encrypt​_ccmd​_iin[Cmd-1:0] logic
    block​_encrypt​_inst​_id​_iin[StateId-1:0] logic
    block​_encrypt​_v​_iin[BlkLen-1:0] logic
    ctr​_drbg​_upd​_sfifo​_updreq​_err​_oout[2:0] logic
    ctr​_drbg​_upd​_sfifo​_bencreq​_err​_oout[2:0] logic
    ctr​_drbg​_upd​_sfifo​_bencack​_err​_oout[2:0] logic
    ctr​_drbg​_upd​_sfifo​_pdata​_err​_oout[2:0] logic
    ctr​_drbg​_upd​_sfifo​_final​_err​_oout[2:0] logic
    ctr​_drbg​_updbe​_sm​_err​_ooutlogic
    ctr​_drbg​_updob​_sm​_err​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module csrng​_main​_sm

    This design unit is implemented in csrng​_main​_sm.sv

    This file depends on: csrng_pkg.sv, prim_flop.sv

    Parameters

    NameTypeDefault ValueDescription
    StateWidthint8

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    acmd​_avail​_iinlogic
    acmd​_accept​_ooutlogic
    acmd​_iin[2:0] logic
    acmd​_eop​_iinlogic
    ctr​_drbg​_cmd​_req​_rdy​_iinlogic
    flag0​_iinlogic
    cmd​_entropy​_req​_ooutlogic
    cmd​_entropy​_avail​_iinlogic
    instant​_req​_ooutlogic
    reseed​_req​_ooutlogic
    generate​_req​_ooutlogic
    update​_req​_ooutlogic
    uninstant​_req​_ooutlogic
    main​_sm​_err​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module csrng​_state​_db

    This design unit is implemented in csrng​_state​_db.sv

    This file depends on: csrng_pkg.sv, uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    NAppsint4
    StateIdint4
    BlkLenint128
    KeyLenint256
    CtrLenint32
    Cmdint3
    InternalStateWidthint2+KeyLen+BlkLen+CtrLen
    RegInternalStateWidthint30+InternalStateWidth
    RegWint32
    MaxNAppsint16

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    state​_db​_enable​_iinlogic
    state​_db​_rd​_req​_iinlogic
    state​_db​_rd​_inst​_id​_iin[StateId-1:0] logic
    state​_db​_rd​_key​_oout[KeyLen-1:0] logic
    state​_db​_rd​_v​_oout[BlkLen-1:0] logic
    state​_db​_rd​_res​_ctr​_oout[CtrLen-1:0] logic
    state​_db​_rd​_inst​_st​_ooutlogic
    state​_db​_rd​_fips​_ooutlogic
    state​_db​_wr​_req​_iinlogic

    write interface

    state​_db​_wr​_req​_rdy​_ooutlogic
    state​_db​_wr​_inst​_id​_iin[StateId-1:0] logic
    state​_db​_wr​_fips​_iinlogic
    state​_db​_wr​_ccmd​_iin[Cmd-1:0] logic
    state​_db​_wr​_key​_iin[KeyLen-1:0] logic
    state​_db​_wr​_v​_iin[BlkLen-1:0] logic
    state​_db​_wr​_res​_ctr​_iin[CtrLen-1:0] logic
    state​_db​_wr​_sts​_iinlogic
    state​_db​_lc​_en​_iinlogic

    status interface

    state​_db​_reg​_rd​_sel​_iinlogic
    state​_db​_reg​_rd​_id​_iin[StateId-1:0] logic
    state​_db​_reg​_rd​_id​_pulse​_iinlogic
    state​_db​_reg​_rd​_val​_oout[31:0] logic
    state​_db​_sts​_ack​_ooutlogic
    state​_db​_sts​_sts​_ooutlogic
    state​_db​_sts​_id​_oout[StateId-1:0] logic

    Block Diagram

    Module debug​_rom

    This design unit is implemented in debug​_rom.sv

    Description

    Auto-generated code

    Parameters

    NameTypeDefault ValueDescription
    RomSizeint19

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    req​_iinlogic
    addr​_iin[63:0] logic
    rdata​_oout[63:0] logic

    Block Diagram

    Module debug​_rom​_one​_scratch

    This design unit is implemented in debug​_rom​_one​_scratch.sv

    Description

    Auto-generated code

    Parameters

    NameTypeDefault ValueDescription
    RomSizeint13

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    req​_iinlogic
    addr​_iin[63:0] logic
    rdata​_oout[63:0] logic

    Block Diagram

    Module dmi​_cdc

    This design unit is implemented in dmi​_cdc.sv

    This file depends on: prim_fifo_async.sv, dm_pkg.sv

    Description

    Copyright 2018 ETH Zurich and University of Bologna.

    Ports

    NameDirectionTypeDescription
    tck​_iinlogic

    JTAG side (master side)

    trst​_niinlogic
    jtag​_dmi​_req​_iindmi_req_t
    jtag​_dmi​_ready​_ooutlogic
    jtag​_dmi​_valid​_iinlogic
    jtag​_dmi​_resp​_ooutdmi_resp_t
    jtag​_dmi​_valid​_ooutlogic
    jtag​_dmi​_ready​_iinlogic
    clk​_iinlogic

    core side (slave side)

    rst​_niinlogic
    core​_dmi​_req​_ooutdmi_req_t
    core​_dmi​_valid​_ooutlogic
    core​_dmi​_ready​_iinlogic
    core​_dmi​_resp​_iindmi_resp_t
    core​_dmi​_ready​_ooutlogic
    core​_dmi​_valid​_iinlogic

    Instantiations

    Block Diagram

    Module dmi​_jtag​_tap

    This design unit is implemented in dmi​_jtag​_tap.sv

    This file depends on: prim_clock_inv.sv

    Parameters

    NameTypeDefault ValueDescription
    IrLengthint5
    IdcodeValue[31:0] logic32'h00000001

    JTAG IDCODE Value

    Ports

    NameDirectionTypeDescription
    tck​_iinlogic

    JTAG test clock pad

    tms​_iinlogic

    JTAG test mode select pad

    trst​_niinlogic

    JTAG test reset pad

    td​_iinlogic

    JTAG test data input pad

    td​_ooutlogic

    JTAG test data output pad

    tdo​_oe​_ooutlogic

    Data out output enable

    testmode​_iinlogic
    test​_logic​_reset​_ooutlogic
    shift​_dr​_ooutlogic
    update​_dr​_ooutlogic
    capture​_dr​_ooutlogic
    dmi​_access​_ooutlogic

    we want to access DMI register

    dtmcs​_select​_ooutlogic

    JTAG is interested in writing the DTM CSR register

    dmi​_reset​_ooutlogic

    clear error state

    dmi​_error​_iin[1:0] logic
    dmi​_tdi​_ooutlogic

    test data to submodule

    dmi​_tdo​_iinlogic

    test data in from submodule

    Instantiations

    Block Diagram

    State Machines

    Module edn​_ack​_sm

    This design unit is implemented in edn​_ack​_sm.sv

    This file depends on: prim_flop.sv

    Parameters

    NameTypeDefault ValueDescription
    StateWidthint6

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_iinlogic
    ack​_ooutlogic
    fifo​_not​_empty​_iinlogic
    fifo​_pop​_ooutlogic
    ack​_sm​_err​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module edn​_main​_sm

    This design unit is implemented in edn​_main​_sm.sv

    This file depends on: prim_flop.sv

    Parameters

    NameTypeDefault ValueDescription
    StateWidthint6

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    auto​_req​_mode​_iinlogic
    seq​_auto​_req​_mode​_ooutlogic
    auto​_req​_mode​_end​_ooutlogic
    csrng​_cmd​_ack​_iinlogic
    capt​_gencmd​_fifo​_cnt​_ooutlogic
    send​_gencmd​_ooutlogic
    max​_reqs​_cnt​_zero​_iinlogic
    capt​_rescmd​_fifo​_cnt​_ooutlogic
    send​_rescmd​_ooutlogic
    cmd​_sent​_iinlogic
    main​_sm​_err​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module entropy​_src​_ack​_sm

    This design unit is implemented in entropy​_src​_ack​_sm.sv

    This file depends on: prim_flop.sv

    Parameters

    NameTypeDefault ValueDescription
    StateWidthint6

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_iinlogic
    ack​_ooutlogic
    fifo​_not​_empty​_iinlogic
    fifo​_pop​_ooutlogic
    ack​_sm​_err​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module entropy​_src​_adaptp​_ht

    This design unit is implemented in entropy​_src​_adaptp​_ht.sv

    Parameters

    NameTypeDefault ValueDescription
    RegWidthint16
    RngBusWidthint4

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    entropy​_bit​_iin[RngBusWidth-1:0] logic
    entropy​_bit​_vld​_iinlogic
    clear​_iinlogic
    active​_iinlogic
    thresh​_hi​_iin[RegWidth-1:0] logic
    thresh​_lo​_iin[RegWidth-1:0] logic
    window​_wrap​_pulse​_iinlogic
    test​_cnt​_oout[RegWidth-1:0] logic
    test​_fail​_hi​_pulse​_ooutlogic
    test​_fail​_lo​_pulse​_ooutlogic

    Block Diagram

    Module entropy​_src​_bucket​_ht

    This design unit is implemented in entropy​_src​_bucket​_ht.sv

    Parameters

    NameTypeDefault ValueDescription
    RegWidthint16
    RngBusWidthint4
    NUM​_BINSint2**RngBusWidth

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    entropy​_bit​_iin[RngBusWidth-1:0] logic
    entropy​_bit​_vld​_iinlogic
    clear​_iinlogic
    active​_iinlogic
    thresh​_iin[RegWidth-1:0] logic
    window​_wrap​_pulse​_iinlogic
    test​_cnt​_oout[RegWidth-1:0] logic
    test​_fail​_pulse​_ooutlogic

    Block Diagram

    Module entropy​_src​_cntr​_reg

    This design unit is implemented in entropy​_src​_cntr​_reg.sv

    Parameters

    NameTypeDefault ValueDescription
    RegWidthint16

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    clear​_iinlogic
    active​_iinlogic
    event​_iinlogic
    value​_oout[RegWidth-1:0] logic

    Block Diagram

    Module entropy​_src​_main​_sm

    This design unit is implemented in entropy​_src​_main​_sm.sv

    This file depends on: prim_flop.sv

    Parameters

    NameTypeDefault ValueDescription
    StateWidthint8

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    enable​_iinlogic
    ht​_done​_pulse​_iinlogic
    ht​_fail​_pulse​_iinlogic
    postht​_not​_empty​_iinlogic
    rst​_alert​_cntr​_ooutlogic
    bypass​_mode​_iinlogic
    rst​_bypass​_mode​_ooutlogic
    main​_stage​_rdy​_iinlogic
    bypass​_stage​_rdy​_iinlogic
    main​_stage​_pop​_ooutlogic
    bypass​_stage​_pop​_ooutlogic
    main​_sm​_err​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module entropy​_src​_markov​_ht

    This design unit is implemented in entropy​_src​_markov​_ht.sv

    Parameters

    NameTypeDefault ValueDescription
    RegWidthint16
    RngBusWidthint4

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    entropy​_bit​_iin[RngBusWidth-1:0] logic
    entropy​_bit​_vld​_iinlogic
    clear​_iinlogic
    active​_iinlogic
    thresh​_hi​_iin[RegWidth-1:0] logic
    thresh​_lo​_iin[RegWidth-1:0] logic
    window​_wrap​_pulse​_iinlogic
    test​_cnt​_hi​_oout[RegWidth-1:0] logic
    test​_cnt​_lo​_oout[RegWidth-1:0] logic
    test​_fail​_hi​_pulse​_ooutlogic
    test​_fail​_lo​_pulse​_ooutlogic

    Block Diagram

    Module entropy​_src​_repcnt​_ht

    This design unit is implemented in entropy​_src​_repcnt​_ht.sv

    Parameters

    NameTypeDefault ValueDescription
    RegWidthint16
    RngBusWidthint4

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    entropy​_bit​_iin[RngBusWidth-1:0] logic
    entropy​_bit​_vld​_iinlogic
    clear​_iinlogic
    active​_iinlogic
    thresh​_iin[RegWidth-1:0] logic
    test​_cnt​_oout[RegWidth-1:0] logic
    test​_fail​_pulse​_ooutlogic

    Block Diagram

    Module entropy​_src​_watermark​_reg

    This design unit is implemented in entropy​_src​_watermark​_reg.sv

    Parameters

    NameTypeDefault ValueDescription
    RegWidthint16
    HighWatermarkbit1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    clear​_iinlogic
    active​_iinlogic
    event​_iinlogic
    value​_iin[RegWidth-1:0] logic
    value​_oout[RegWidth-1:0] logic

    Block Diagram

    Module flash​_phy​_erase

    This design unit is implemented in flash​_phy​_erase.sv

    This file depends on: flash_phy_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    pg​_erase​_req​_iinlogic

    interface with controller

    bk​_erase​_req​_iinlogic
    ack​_ooutlogic
    pg​_erase​_req​_ooutlogic

    interface with flash

    bk​_erase​_req​_ooutlogic
    ack​_iinlogic
    done​_iinlogic

    Block Diagram

    State Machines

    Module flash​_phy​_prog

    This design unit is implemented in flash​_phy​_prog.sv

    This file depends on: uvm_pkg.sv, prim_secded_hamming_72_64_enc.sv, flash_phy_pkg.sv

    Description

    flash_phy_prog

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_iinlogic
    scramble​_iinlogic
    ecc​_iinlogic
    sel​_iin[WordSelW-1:0] logic
    data​_iin[BusWidth-1:0] logic
    last​_iinlogic
    ack​_iinlogic

    ack means request has been accepted by flash

    done​_iinlogic

    done means requested transaction has completed

    calc​_ack​_iinlogic
    scramble​_ack​_iinlogic
    mask​_iin[DataWidth-1:0] logic
    scrambled​_data​_iin[DataWidth-1:0] logic
    calc​_req​_ooutlogic
    scramble​_req​_ooutlogic
    req​_ooutlogic
    last​_ooutlogic

    last beat of an incoming transaction

    ack​_ooutlogic
    block​_data​_oout[DataWidth-1:0] logic

    block data does not contain ecc / metadata portion

    data​_oout[FullDataWidth-1:0] logic

    Instantiations

    Block Diagram

    State Machines

    Module flash​_phy​_rd

    This design unit is implemented in flash​_phy​_rd.sv

    This file depends on: prim_secded_hamming_72_64_dec.sv, uvm_pkg.sv, flash_phy_pkg.sv, flash_ctrl_pkg.sv, flash_phy_rd_buffers.sv, prim_fifo_sync.sv, prim_arbiter_tree.sv

    Description

    flash_phy_core

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    buf​_en​_iinlogic

    configuration interface from flash controller

    req​_iinlogic

    interface with arbitration unit

    descramble​_iinlogic
    ecc​_iinlogic
    prog​_iinlogic
    pg​_erase​_iinlogic
    bk​_erase​_iinlogic
    addr​_iin[BusBankAddrW-1:0] logic
    part​_iinflash_part_e
    info​_sel​_iin[InfoTypesWidth-1:0] logic
    rdy​_ooutlogic
    data​_valid​_ooutlogic
    data​_err​_ooutlogic
    data​_oout[BusWidth-1:0] logic
    idle​_ooutlogic

    the entire read pipeline is idle

    calc​_req​_ooutlogic

    interface with scramble unit

    descramble​_req​_ooutlogic
    calc​_addr​_oout[BankAddrW-1:0] logic
    scrambled​_data​_oout[DataWidth-1:0] logic
    calc​_ack​_iinlogic
    descramble​_ack​_iinlogic
    mask​_iin[DataWidth-1:0] logic
    descrambled​_data​_iin[DataWidth-1:0] logic
    req​_ooutlogic

    interface to actual flash primitive

    ack​_iinlogic

    request has been accepted

    done​_iinlogic

    actual data return

    data​_iin[FullDataWidth-1:0] logic
    ecc​_single​_err​_ooutlogic

    error status reporting

    ecc​_multi​_err​_ooutlogic
    ecc​_addr​_oout[BusBankAddrW-1:0] logic

    Instantiations

    Block Diagram

    Module flash​_phy​_scramble

    This design unit is implemented in flash​_phy​_scramble.sv

    This file depends on: prim_gf_mult.sv, flash_phy_pkg.sv, prim_prince.sv

    Description

    flash_phy_scramble

    Parameters

    NameTypeDefault ValueDescription
    AddrPadWidthintDataWidth - BankAddrW
    UnusedWidthintKeySize - AddrPadWidth

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    calc​_req​_iinlogic

    calculate galois multiplier mask

    op​_req​_iinlogic

    request primitive operation

    op​_type​_iincipher_ops_e

    sramble or de-scramble

    addr​_iin[BankAddrW-1:0] logic
    plain​_data​_iin[DataWidth-1:0] logic
    scrambled​_data​_iin[DataWidth-1:0] logic
    addr​_key​_iin[KeySize-1:0] logic
    data​_key​_iin[KeySize-1:0] logic
    calc​_ack​_ooutlogic
    op​_ack​_ooutlogic
    mask​_oout[DataWidth-1:0] logic
    plain​_data​_oout[DataWidth-1:0] logic
    scrambled​_data​_oout[DataWidth-1:0] logic

    Instantiations

    Block Diagram

    Module i2c​_fsm

    This design unit is implemented in i2c​_fsm.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    clock

    rst​_niinlogic

    active low reset

    scl​_iinlogic

    serial clock input from i2c bus

    scl​_ooutlogic

    serial clock output to i2c bus

    sda​_iinlogic

    serial data input from i2c bus

    sda​_ooutlogic

    serial data output to i2c bus

    host​_enable​_iinlogic

    enable host functionality

    target​_enable​_iinlogic

    enable target functionality

    fmt​_fifo​_rvalid​_iinlogic

    indicates there is valid data in fmt_fifo

    fmt​_fifo​_wvalid​_iinlogic

    indicates data is being put into fmt_fifo

    fmt​_fifo​_depth​_iin[5:0] logic

    fmt_fifo_depth

    fmt​_fifo​_rready​_ooutlogic

    populates fmt_fifo

    fmt​_byte​_iin[7:0] logic

    byte in fmt_fifo to be sent to target

    fmt​_flag​_start​_before​_iinlogic

    issue start before sending byte

    fmt​_flag​_stop​_after​_iinlogic

    issue stop after sending byte

    fmt​_flag​_read​_bytes​_iinlogic

    indicates byte is an number of reads

    fmt​_flag​_read​_continue​_iinlogic

    host to send Ack to final byte read

    fmt​_flag​_nak​_ok​_iinlogic

    no Ack is expected

    rx​_fifo​_wvalid​_ooutlogic

    high if there is valid data in rx_fifo

    rx​_fifo​_wdata​_oout[7:0] logic

    byte in rx_fifo read from target

    tx​_fifo​_rvalid​_iinlogic

    indicates there is valid data in tx_fifo

    tx​_fifo​_wvalid​_iinlogic

    indicates data is being put into tx_fifo

    tx​_fifo​_depth​_iin[5:0] logic

    tx_fifo_depth

    tx​_fifo​_rready​_ooutlogic

    populates tx_fifo

    tx​_fifo​_rdata​_iin[7:0] logic

    byte in tx_fifo to be sent to host

    acq​_fifo​_wready​_iinlogic

    low if acq_fifo is full

    acq​_fifo​_wvalid​_ooutlogic

    high if there is valid data in acq_fifo

    acq​_fifo​_wdata​_oout[9:0] logic

    byte and signal in acq_fifo read from target

    host​_idle​_ooutlogic

    indicates the host is idle

    target​_idle​_ooutlogic

    indicates the target is idle

    thigh​_iin[15:0] logic

    high period of the SCL in clock units

    tlow​_iin[15:0] logic

    low period of the SCL in clock units

    t​_r​_iin[15:0] logic

    rise time of both SDA and SCL in clock units

    t​_f​_iin[15:0] logic

    fall time of both SDA and SCL in clock units

    thd​_sta​_iin[15:0] logic

    hold time for (repeated) START in clock units

    tsu​_sta​_iin[15:0] logic

    setup time for repeated START in clock units

    tsu​_sto​_iin[15:0] logic

    setup time for STOP in clock units

    tsu​_dat​_iin[15:0] logic

    data setup time in clock units

    thd​_dat​_iin[15:0] logic

    data hold time in clock units

    t​_buf​_iin[15:0] logic

    bus free time between STOP and START in clock units

    stretch​_timeout​_iin[30:0] logic

    max time target may stretch the clock

    timeout​_enable​_iinlogic

    assert if target stretches clock past max

    stretch​_en​_addr​_iinlogic

    enable target stretching clock after address matching

    stretch​_en​_tx​_iinlogic

    enable target stretching clock after transmit transaction

    stretch​_en​_acq​_iinlogic

    enable target stretching clock after acquire transaction

    stretch​_stop​_iinlogic

    stop stretching clock and resume normal operation

    host​_timeout​_iin[31:0] logic

    max time target waits for host to pull clock down

    target​_address0​_iin[6:0] logic
    target​_mask0​_iin[6:0] logic
    target​_address1​_iin[6:0] logic
    target​_mask1​_iin[6:0] logic
    event​_nak​_ooutlogic

    target didn't Ack when expected

    event​_scl​_interference​_ooutlogic

    other device forcing SCL low

    event​_sda​_interference​_ooutlogic

    other device forcing SDA low

    event​_stretch​_timeout​_ooutlogic

    target stretches clock past max time

    event​_sda​_unstable​_ooutlogic

    SDA is not constant during SCL pulse

    event​_trans​_complete​_ooutlogic

    Transaction is complete

    event​_tx​_empty​_ooutlogic

    tx_fifo is empty but data is needed

    event​_tx​_nonempty​_ooutlogic

    tx_fifo is nonempty after stop

    event​_ack​_stop​_ooutlogic

    target received stop after ack

    event​_host​_timeout​_ooutlogic

    host ceased sending SCL pulses during ongoing transactn

    Block Diagram

    State Machines

    Module ibex​_cs​_registers

    This design unit is implemented in ibex​_cs​_registers.sv

    This file depends on: uvm_pkg.sv, ibex_pkg.sv, ibex_csr.sv, ibex_counter.sv

    Parameters

    NameTypeDefault ValueDescription
    DbgTriggerEnbit0
    DbgHwBreakNumint1
    DataIndTimingbit1'b0
    DummyInstructionsbit1'b0
    ShadowCSRbit1'b0
    ICachebit1'b0
    MHPMCounterNumint10
    MHPMCounterWidthint40
    PMPEnablebit0
    PMPGranularityint0
    PMPNumRegionsint4
    RV32Ebit0
    RV32Mrv32m_eibex_pkg::RV32MFast
    RV32MEnabledint(RV32M == RV32MNone) ? 0 : 1
    MISA​_VALUE[31:0] logic(0 << 0) | (1 << 2) | (0 << 3) | (32'(RV32E) << 4) | (0 << 5) | (32'(!RV32E) << 8) | (RV32MEnabled << 12) | (0 << 13) | (0 << 18) | (1 << 20) | (0 << 23) | (32'(CSR_MISA_MXL) << 30)

    M-XLEN

    MSTATUS​_RST​_VALstatus_t'{mie: 1'b0, mpie: 1'b1, mpp: PRIV_LVL_U, mprv: 1'b0, tw: 1'b0}

    MSTATUS

    DCSR​_RESET​_VALdcsr_t'{ xdebugver: XDEBUGVER_STD, cause: DBG_CAUSE_NONE, prv: PRIV_LVL_M, default: '0 }

    DCSR

    MSTACK​_RESET​_VALstatus_stk_t'{ mpie: 1'b1, mpp: PRIV_LVL_U }

    MSTACK

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock and Reset

    rst​_niinlogic
    hart​_id​_iin[31:0] logic

    Hart ID

    priv​_mode​_id​_ooutpriv_lvl_e

    Privilege mode

    priv​_mode​_if​_ooutpriv_lvl_e
    priv​_mode​_lsu​_ooutpriv_lvl_e
    csr​_mstatus​_tw​_ooutlogic
    csr​_mtvec​_oout[31:0] logic

    mtvec

    csr​_mtvec​_init​_iinlogic
    boot​_addr​_iin[31:0] logic
    csr​_access​_iinlogic

    Interface to registers (SRAM like)

    csr​_addr​_iincsr_num_e
    csr​_wdata​_iin[31:0] logic
    csr​_op​_iincsr_op_e
    csr​_op​_en​_iinlogic
    csr​_rdata​_oout[31:0] logic
    irq​_software​_iinlogic

    interrupts

    irq​_timer​_iinlogic
    irq​_external​_iinlogic
    irq​_fast​_iin[14:0] logic
    nmi​_mode​_iinlogic
    irq​_pending​_ooutlogic

    interrupt request pending

    irqs​_ooutirqs_t

    interrupt requests qualified with mie

    csr​_mstatus​_mie​_ooutlogic
    csr​_mepc​_oout[31:0] logic
    csr​_pmp​_cfg​_ooutpmp_cfg_t [PMPNumRegions]

    PMP

    csr​_pmp​_addr​_oout[33:0] logic [PMPNumRegions]
    debug​_mode​_iinlogic

    debug

    debug​_cause​_iindbg_cause_e
    debug​_csr​_save​_iinlogic
    csr​_depc​_oout[31:0] logic
    debug​_single​_step​_ooutlogic
    debug​_ebreakm​_ooutlogic
    debug​_ebreaku​_ooutlogic
    trigger​_match​_ooutlogic
    pc​_if​_iin[31:0] logic
    pc​_id​_iin[31:0] logic
    pc​_wb​_iin[31:0] logic
    data​_ind​_timing​_ooutlogic

    CPU control bits

    dummy​_instr​_en​_ooutlogic
    dummy​_instr​_mask​_oout[2:0] logic
    dummy​_instr​_seed​_en​_ooutlogic
    dummy​_instr​_seed​_oout[31:0] logic
    icache​_enable​_ooutlogic
    csr​_shadow​_err​_ooutlogic
    csr​_save​_if​_iinlogic

    Exception save/restore

    csr​_save​_id​_iinlogic
    csr​_save​_wb​_iinlogic
    csr​_restore​_mret​_iinlogic
    csr​_restore​_dret​_iinlogic
    csr​_save​_cause​_iinlogic
    csr​_mcause​_iinexc_cause_e
    csr​_mtval​_iin[31:0] logic
    illegal​_csr​_insn​_ooutlogic

    access to non-existent CSR, with wrong priviledge level, or missing write permissions

    instr​_ret​_iinlogic

    instr retired in ID/EX stage

    instr​_ret​_compressed​_iinlogic

    compressed instr retired

    iside​_wait​_iinlogic

    core waiting for the iside

    jump​_iinlogic

    jump instr seen (j, jr, jal, jalr)

    branch​_iinlogic

    branch instr seen (bf, bnf)

    branch​_taken​_iinlogic

    branch was taken

    mem​_load​_iinlogic

    load from memory in this cycle

    mem​_store​_iinlogic

    store to memory in this cycle

    dside​_wait​_iinlogic

    core waiting for the dside

    mul​_wait​_iinlogic

    core waiting for multiply

    div​_wait​_iinlogic

    core waiting for divide

    Instantiations

    Block Diagram

    Module ibex​_ex​_block

    This design unit is implemented in ibex​_ex​_block.sv

    This file depends on: ibex_alu.sv, ibex_multdiv_fast.sv, ibex_pkg.sv, ibex_multdiv_slow.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    RV32Mrv32m_eibex_pkg::RV32MFast
    RV32Brv32b_eibex_pkg::RV32BNone
    BranchTargetALUbit0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    alu​_operator​_iinalu_op_e

    ALU

    alu​_operand​_a​_iin[31:0] logic
    alu​_operand​_b​_iin[31:0] logic
    alu​_instr​_first​_cycle​_iinlogic
    bt​_a​_operand​_iin[31:0] logic

    Branch Target ALU All of these signals are unusued when BranchTargetALU == 0

    bt​_b​_operand​_iin[31:0] logic
    multdiv​_operator​_iinmd_op_e

    Multiplier/Divider

    mult​_en​_iinlogic

    dynamic enable signal, for FSM control

    div​_en​_iinlogic

    dynamic enable signal, for FSM control

    mult​_sel​_iinlogic

    static decoder output, for data muxes

    div​_sel​_iinlogic

    static decoder output, for data muxes

    multdiv​_signed​_mode​_iin[1:0] logic
    multdiv​_operand​_a​_iin[31:0] logic
    multdiv​_operand​_b​_iin[31:0] logic
    multdiv​_ready​_id​_iinlogic
    data​_ind​_timing​_iinlogic
    imd​_val​_we​_oout[1:0] logic

    intermediate val reg

    imd​_val​_d​_oout[33:0] logic [2]
    imd​_val​_q​_iin[33:0] logic [2]
    alu​_adder​_result​_ex​_oout[31:0] logic

    to LSU

    result​_ex​_oout[31:0] logic
    branch​_target​_oout[31:0] logic

    to IF

    branch​_decision​_ooutlogic

    to ID

    ex​_valid​_ooutlogic

    EX has valid output

    Instantiations

    Block Diagram

    Module ibex​_id​_stage

    This design unit is implemented in ibex​_id​_stage.sv

    This file depends on: uvm_pkg.sv, ibex_controller.sv, ibex_pkg.sv, ibex_decoder.sv

    Parameters

    NameTypeDefault ValueDescription
    RV32Ebit0
    RV32Mrv32m_eibex_pkg::RV32MFast
    RV32Brv32b_eibex_pkg::RV32BNone
    DataIndTimingbit1'b0
    BranchTargetALUbit0
    SpecBranchbit0
    WritebackStagebit0
    BranchPredictorbit0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    ctrl​_busy​_ooutlogic
    illegal​_insn​_ooutlogic
    instr​_valid​_iinlogic

    Interface to IF stage

    instr​_rdata​_iin[31:0] logic

    from IF-ID pipeline registers

    instr​_rdata​_alu​_iin[31:0] logic

    from IF-ID pipeline registers

    instr​_rdata​_c​_iin[15:0] logic

    from IF-ID pipeline registers

    instr​_is​_compressed​_iinlogic
    instr​_bp​_taken​_iinlogic
    instr​_req​_ooutlogic
    instr​_first​_cycle​_id​_ooutlogic
    instr​_valid​_clear​_ooutlogic

    kill instr in IF-ID reg

    id​_in​_ready​_ooutlogic

    ID stage is ready for next instr

    icache​_inval​_ooutlogic
    branch​_decision​_iinlogic

    Jumps and branches

    pc​_set​_ooutlogic

    IF and ID stage signals

    pc​_set​_spec​_ooutlogic
    pc​_mux​_ooutpc_sel_e
    nt​_branch​_mispredict​_ooutlogic
    exc​_pc​_mux​_ooutexc_pc_sel_e
    exc​_cause​_ooutexc_cause_e
    illegal​_c​_insn​_iinlogic
    instr​_fetch​_err​_iinlogic
    instr​_fetch​_err​_plus2​_iinlogic
    pc​_id​_iin[31:0] logic
    ex​_valid​_iinlogic

    EX stage has valid output

    lsu​_resp​_valid​_iinlogic

    LSU has valid output, or is done

    alu​_operator​_ex​_ooutalu_op_e

    ALU

    alu​_operand​_a​_ex​_oout[31:0] logic
    alu​_operand​_b​_ex​_oout[31:0] logic
    imd​_val​_we​_ex​_iin[1:0] logic

    Multicycle Operation Stage Register

    imd​_val​_d​_ex​_iin[33:0] logic [2]
    imd​_val​_q​_ex​_oout[33:0] logic [2]
    bt​_a​_operand​_oout[31:0] logic

    Branch target ALU

    bt​_b​_operand​_oout[31:0] logic
    mult​_en​_ex​_ooutlogic

    MUL, DIV

    div​_en​_ex​_ooutlogic
    mult​_sel​_ex​_ooutlogic
    div​_sel​_ex​_ooutlogic
    multdiv​_operator​_ex​_ooutmd_op_e
    multdiv​_signed​_mode​_ex​_oout[1:0] logic
    multdiv​_operand​_a​_ex​_oout[31:0] logic
    multdiv​_operand​_b​_ex​_oout[31:0] logic
    multdiv​_ready​_id​_ooutlogic
    csr​_access​_ooutlogic

    CSR

    csr​_op​_ooutcsr_op_e
    csr​_op​_en​_ooutlogic
    csr​_save​_if​_ooutlogic
    csr​_save​_id​_ooutlogic
    csr​_save​_wb​_ooutlogic
    csr​_restore​_mret​_id​_ooutlogic
    csr​_restore​_dret​_id​_ooutlogic
    csr​_save​_cause​_ooutlogic
    csr​_mtval​_oout[31:0] logic
    priv​_mode​_iinpriv_lvl_e
    csr​_mstatus​_tw​_iinlogic
    illegal​_csr​_insn​_iinlogic
    data​_ind​_timing​_iinlogic
    lsu​_req​_ooutlogic

    Interface to load store unit

    lsu​_we​_ooutlogic
    lsu​_type​_oout[1:0] logic
    lsu​_sign​_ext​_ooutlogic
    lsu​_wdata​_oout[31:0] logic
    lsu​_req​_done​_iinlogic

    Data req to LSU is complete and instruction can move to writeback (only relevant where writeback stage is present)

    lsu​_addr​_incr​_req​_iinlogic
    lsu​_addr​_last​_iin[31:0] logic
    csr​_mstatus​_mie​_iinlogic

    Interrupt signals

    irq​_pending​_iinlogic
    irqs​_iinirqs_t
    irq​_nm​_iinlogic
    nmi​_mode​_ooutlogic
    lsu​_load​_err​_iinlogic
    lsu​_store​_err​_iinlogic
    debug​_mode​_ooutlogic

    Debug Signal

    debug​_cause​_ooutdbg_cause_e
    debug​_csr​_save​_ooutlogic
    debug​_req​_iinlogic
    debug​_single​_step​_iinlogic
    debug​_ebreakm​_iinlogic
    debug​_ebreaku​_iinlogic
    trigger​_match​_iinlogic
    result​_ex​_iin[31:0] logic

    Write back signal

    csr​_rdata​_iin[31:0] logic
    rf​_raddr​_a​_oout[4:0] logic

    Register file read

    rf​_rdata​_a​_iin[31:0] logic
    rf​_raddr​_b​_oout[4:0] logic
    rf​_rdata​_b​_iin[31:0] logic
    rf​_ren​_a​_ooutlogic
    rf​_ren​_b​_ooutlogic
    rf​_waddr​_id​_oout[4:0] logic

    Register file write (via writeback)

    rf​_wdata​_id​_oout[31:0] logic
    rf​_we​_id​_ooutlogic
    rf​_rd​_a​_wb​_match​_ooutlogic
    rf​_rd​_b​_wb​_match​_ooutlogic
    rf​_waddr​_wb​_iin[4:0] logic

    Register write information from writeback (for resolving data hazards)

    rf​_wdata​_fwd​_wb​_iin[31:0] logic
    rf​_write​_wb​_iinlogic
    en​_wb​_ooutlogic
    instr​_type​_wb​_ooutwb_instr_type_e
    ready​_wb​_iinlogic
    outstanding​_load​_wb​_iinlogic
    outstanding​_store​_wb​_iinlogic
    perf​_jump​_ooutlogic

    executing a jump instr

    perf​_branch​_ooutlogic

    executing a branch instr

    perf​_tbranch​_ooutlogic

    executing a taken branch instr

    perf​_dside​_wait​_ooutlogic

    instruction in ID/EX is awaiting memory access to finish before proceeding

    perf​_mul​_wait​_ooutlogic
    perf​_div​_wait​_ooutlogic
    instr​_id​_done​_ooutlogic
    instr​_id​_done​_compressed​_ooutlogic

    Instantiations

    Block Diagram

    State Machines

    Module ibex​_if​_stage

    This design unit is implemented in ibex​_if​_stage.sv

    This file depends on: ibex_dummy_instr.sv, ibex_branch_predict.sv, uvm_pkg.sv, ibex_pkg.sv, ibex_prefetch_buffer.sv, ibex_icache.sv, ibex_compressed_decoder.sv

    Parameters

    NameTypeDefault ValueDescription
    DmHaltAddrint32'h1A110800
    DmExceptionAddrint32'h1A110808
    DummyInstructionsbit1'b0
    ICachebit1'b0
    ICacheECCbit1'b0
    PCIncrCheckbit1'b0
    BranchPredictorbit1'b0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    boot​_addr​_iin[31:0] logic

    also used for mtvec

    req​_iinlogic

    instruction request control

    instr​_req​_ooutlogic

    instruction cache interface

    instr​_addr​_oout[31:0] logic
    instr​_gnt​_iinlogic
    instr​_rvalid​_iinlogic
    instr​_rdata​_iin[31:0] logic
    instr​_err​_iinlogic
    instr​_pmp​_err​_iinlogic
    instr​_valid​_id​_ooutlogic

    instr in IF-ID is valid

    instr​_new​_id​_ooutlogic

    instr in IF-ID is new

    instr​_rdata​_id​_oout[31:0] logic

    instr for ID stage

    instr​_rdata​_alu​_id​_oout[31:0] logic

    replicated instr for ID stage to reduce fan-out

    instr​_rdata​_c​_id​_oout[15:0] logic

    compressed instr for ID stage (mtval), meaningful only if instr_is_compressed_id_o = 1'b1

    instr​_is​_compressed​_id​_ooutlogic

    compressed decoder thinks this is a compressed instr

    instr​_bp​_taken​_ooutlogic

    instruction was predicted to be a taken branch

    instr​_fetch​_err​_ooutlogic

    bus error on fetch

    instr​_fetch​_err​_plus2​_ooutlogic

    bus error misaligned

    illegal​_c​_insn​_id​_ooutlogic

    compressed decoder thinks this is an invalid instr

    dummy​_instr​_id​_ooutlogic

    Instruction is a dummy

    pc​_if​_oout[31:0] logic
    pc​_id​_oout[31:0] logic
    instr​_valid​_clear​_iinlogic

    clear instr valid bit in IF-ID

    pc​_set​_iinlogic

    set the PC to a new value

    pc​_set​_spec​_iinlogic
    pc​_mux​_iinpc_sel_e

    selector for PC multiplexer

    nt​_branch​_mispredict​_iinlogic

    Not-taken branch in ID/EX was mispredicted (predicted taken)

    exc​_pc​_mux​_iinexc_pc_sel_e

    selects ISR address

    exc​_causeinexc_cause_e

    selects ISR address for vectorized interrupt lines

    dummy​_instr​_en​_iinlogic
    dummy​_instr​_mask​_iin[2:0] logic
    dummy​_instr​_seed​_en​_iinlogic
    dummy​_instr​_seed​_iin[31:0] logic
    icache​_enable​_iinlogic
    icache​_inval​_iinlogic
    branch​_target​_ex​_iin[31:0] logic

    branch/jump target address

    csr​_mepc​_iin[31:0] logic

    PC to restore after handling the interrupt/exception

    csr​_depc​_iin[31:0] logic

    PC to restore after handling the debug request

    csr​_mtvec​_iin[31:0] logic

    base PC to jump to on exception

    csr​_mtvec​_init​_ooutlogic

    tell CS regfile to init mtvec

    id​_in​_ready​_iinlogic

    ID stage is ready for new instr

    pc​_mismatch​_alert​_ooutlogic

    misc signals

    if​_busy​_ooutlogic

    IF stage is busy fetching instr

    Instantiations

    Block Diagram

    Module ibex​_load​_store​_unit

    This design unit is implemented in ibex​_load​_store​_unit.sv

    This file depends on: uvm_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    data​_req​_ooutlogic

    data interface

    data​_gnt​_iinlogic
    data​_rvalid​_iinlogic
    data​_err​_iinlogic
    data​_pmp​_err​_iinlogic
    data​_addr​_oout[31:0] logic
    data​_we​_ooutlogic
    data​_be​_oout[3:0] logic
    data​_wdata​_oout[31:0] logic
    data​_rdata​_iin[31:0] logic
    lsu​_we​_iinlogic

    write enable -> from ID/EX

    lsu​_type​_iin[1:0] logic

    data type: word, half word, byte -> from ID/EX

    lsu​_wdata​_iin[31:0] logic

    data to write to memory -> from ID/EX

    lsu​_sign​_ext​_iinlogic

    sign extension -> from ID/EX

    lsu​_rdata​_oout[31:0] logic

    requested data -> to ID/EX

    lsu​_rdata​_valid​_ooutlogic
    lsu​_req​_iinlogic

    data request -> from ID/EX

    adder​_result​_ex​_iin[31:0] logic

    address computed in ALU -> from ID/EX

    addr​_incr​_req​_ooutlogic

    request address increment for misaligned accesses -> to ID/EX

    addr​_last​_oout[31:0] logic

    address of last transaction -> to controller -> mtval -> AGU for misaligned accesses

    lsu​_req​_done​_ooutlogic

    Signals that data request is complete (only need to await final data response) -> to ID/EX

    lsu​_resp​_valid​_ooutlogic

    LSU has response from transaction -> to ID/EX

    load​_err​_ooutlogic

    exception signals

    store​_err​_ooutlogic
    busy​_ooutlogic
    perf​_load​_ooutlogic
    perf​_store​_ooutlogic

    Block Diagram

    State Machines

    Module ibex​_pmp

    This design unit is implemented in ibex​_pmp.sv

    This file depends on: ibex_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    PMPGranularityint0

    Granularity of NAPOT access, 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.

    PMPNumChanint2

    Number of access channels (e.g. i-side + d-side)

    PMPNumRegionsint4

    Number of implemented regions

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock and Reset

    rst​_niinlogic
    csr​_pmp​_cfg​_iinpmp_cfg_t [PMPNumRegions]

    Interface to CSRs

    csr​_pmp​_addr​_iin[33:0] logic [PMPNumRegions]
    priv​_mode​_iinpriv_lvl_e [PMPNumChan]
    pmp​_req​_addr​_iin[33:0] logic [PMPNumChan]

    Access checking channels

    pmp​_req​_type​_iinpmp_req_e [PMPNumChan]
    pmp​_req​_err​_ooutlogic [PMPNumChan]

    Block Diagram

    Module ibex​_register​_file​_ff

    This design unit is implemented in ibex​_register​_file​_ff.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    RV32Ebit0
    DataWidthint32
    DummyInstructionsbit0
    ADDR​_WIDTHintRV32E ? 4 : 5
    NUM​_WORDSint2**ADDR_WIDTH

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock and Reset

    rst​_niinlogic
    test​_en​_iinlogic
    dummy​_instr​_id​_iinlogic
    raddr​_a​_iin[4:0] logic

    Read port R1

    rdata​_a​_oout[DataWidth-1:0] logic
    raddr​_b​_iin[4:0] logic

    Read port R2

    rdata​_b​_oout[DataWidth-1:0] logic
    waddr​_a​_iin[4:0] logic

    Write port W1

    wdata​_a​_iin[DataWidth-1:0] logic
    we​_a​_iinlogic

    Block Diagram

    Module ibex​_register​_file​_fpga

    This design unit is implemented in ibex​_register​_file​_fpga.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    RV32Ebit0
    DataWidthint32
    DummyInstructionsbit0
    ADDR​_WIDTHintRV32E ? 4 : 5
    NUM​_WORDSint2**ADDR_WIDTH

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock and Reset

    rst​_niinlogic
    test​_en​_iinlogic
    dummy​_instr​_id​_iinlogic
    raddr​_a​_iin[4:0] logic

    Read port R1

    rdata​_a​_oout[DataWidth-1:0] logic
    raddr​_b​_iin[4:0] logic

    Read port R2

    rdata​_b​_oout[DataWidth-1:0] logic
    waddr​_a​_iin[4:0] logic

    Write port W1

    wdata​_a​_iin[DataWidth-1:0] logic
    we​_a​_iinlogic

    Block Diagram

    Module ibex​_register​_file​_latch

    This design unit is implemented in ibex​_register​_file​_latch.sv

    This file depends on: prim_clock_gating.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    RV32Ebit0
    DataWidthint32
    DummyInstructionsbit0
    ADDR​_WIDTHintRV32E ? 4 : 5
    NUM​_WORDSint2**ADDR_WIDTH

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock and Reset

    rst​_niinlogic
    test​_en​_iinlogic
    dummy​_instr​_id​_iinlogic
    raddr​_a​_iin[4:0] logic

    Read port R1

    rdata​_a​_oout[DataWidth-1:0] logic
    raddr​_b​_iin[4:0] logic

    Read port R2

    rdata​_b​_oout[DataWidth-1:0] logic
    waddr​_a​_iin[4:0] logic

    Write port W1

    wdata​_a​_iin[DataWidth-1:0] logic
    we​_a​_iinlogic

    Instantiations

    Block Diagram

    Package ibex​_tracer​_pkg

    This design unit is implemented in ibex​_tracer​_pkg.sv

    This file depends on: ibex_pkg.sv

    Module ibex​_wb​_stage

    This design unit is implemented in ibex​_wb​_stage.sv

    This file depends on: uvm_pkg.sv, ibex_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    WritebackStagebit1'b0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    en​_wb​_iinlogic
    instr​_type​_wb​_iinwb_instr_type_e
    pc​_id​_iin[31:0] logic
    ready​_wb​_ooutlogic
    rf​_write​_wb​_ooutlogic
    outstanding​_load​_wb​_ooutlogic
    outstanding​_store​_wb​_ooutlogic
    pc​_wb​_oout[31:0] logic
    rf​_waddr​_id​_iin[4:0] logic
    rf​_wdata​_id​_iin[31:0] logic
    rf​_we​_id​_iinlogic
    rf​_wdata​_lsu​_iin[31:0] logic
    rf​_we​_lsu​_iinlogic
    rf​_wdata​_fwd​_wb​_oout[31:0] logic
    rf​_waddr​_wb​_oout[4:0] logic
    rf​_wdata​_wb​_oout[31:0] logic
    rf​_we​_wb​_ooutlogic
    lsu​_resp​_valid​_iinlogic
    instr​_done​_wb​_ooutlogic

    Block Diagram

    Module IOBUF

    This design unit is implemented in IOBUF.v

    Parameters

    NameTypeDefault ValueDescription
    CAPACITANCEunknown"DONT_CARE"
    DRIVEinteger12
    IBUF​_DELAY​_VALUEunknown"0"
    IBUF​_LOW​_PWRunknown"TRUE"
    IFD​_DELAY​_VALUEunknown"AUTO"
    IOSTANDARDunknown"DEFAULT"
    SLEWunknown"SLOW"

    Ports

    NameDirectionTypeDescription
    Ooutlogic
    IOinoutlogic
    Iinlogic
    Tinlogic

    Block Diagram

    Module keccak​_round

    This design unit is implemented in keccak​_round.sv

    This file depends on: keccak_2share.sv, uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint1600

    b= {25, 50, 100, 200, 400, 800, 1600}

    WintWidth/25

    Derived

    Lint$clog2(W)
    MaxRoundint12 + 2*L

    Keccak-f only

    RndWint$clog2(MaxRound+1)

    Representing up to MaxRound-1

    DInWidthint64

    currently only 64bit supported

    DInEntryintWidth / DInWidth
    DInAddrint$clog2(DInEntry)
    EnMaskingbit0

    Enable secure hardening

    ShareintEnMasking ? 2 : 1
    ReuseShareint0

    Re-use adjacent share for entropy

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    valid​_iinlogic

    Message Feed

    addr​_iin[DInAddr-1:0] logic
    data​_iin[DInWidth-1:0] logic [Share]
    ready​_ooutlogic
    run​_iinlogic

    Pulse signal to initiates Keccak full round

    rand​_valid​_iinlogic
    rand​_data​_iin[Width-1:0] logic
    rand​_consumed​_ooutlogic
    complete​_ooutlogic

    Indicates full round is done

    state​_oout[Width-1:0] logic [Share]

    State out. This can be used as Digest

    clear​_iinlogic

    Clear internal state to '0

    Instantiations

    Block Diagram

    State Machines

    Module keymgr​_sideload​_key

    This design unit is implemented in keymgr​_sideload​_key.sv

    This file depends on: keymgr_pkg.sv

    Description

    keymgr_sideload_key

    Parameters

    NameTypeDefault ValueDescription
    EntropyCopiesintKeyWidth / 32

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    en​_iinlogic
    set​_en​_iinlogic
    set​_iinlogic
    clr​_iinlogic
    entropy​_iin[RandWidth-1:0] [Shares-1:0] logic
    key​_iin[KeyWidth-1:0] [Shares-1:0] logic
    key​_oouthw_key_req_t

    Block Diagram

    Module lc​_ctrl​_signal​_decode

    This design unit is implemented in lc​_ctrl​_signal​_decode.sv

    This file depends on: prim_lc_sender.sv, uvm_pkg.sv, lc_ctrl_state_pkg.sv, lc_ctrl_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    RndCnstLcKeymgrDivInvalidlc_keymgr_div_tLcKeymgrDivWidth'(0)

    Random netlist constants SCRAP, RAW, TEST_LOCKED*, INVALID

    RndCnstLcKeymgrDivTestDevRmalc_keymgr_div_tLcKeymgrDivWidth'(1)

    TEST_UNLOCKED*, DEV, RMA

    RndCnstLcKeymgrDivProductionlc_keymgr_div_tLcKeymgrDivWidth'(2)

    PROD, PROD_END

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    lc​_state​_valid​_iinlogic

    Life cycle state vector.

    lc​_state​_iinlc_state_e
    lc​_id​_state​_iinlc_id_state_e
    fsm​_state​_iinfsm_state_e
    esc​_wipe​_secrets​_iinlogic

    Escalation enable from escalation receiver.

    lc​_dft​_en​_ooutlc_tx_t

    Life cycle broadcast outputs.

    lc​_nvm​_debug​_en​_ooutlc_tx_t
    lc​_hw​_debug​_en​_ooutlc_tx_t
    lc​_cpu​_en​_ooutlc_tx_t
    lc​_creator​_seed​_sw​_rw​_en​_ooutlc_tx_t
    lc​_owner​_seed​_sw​_rw​_en​_ooutlc_tx_t
    lc​_iso​_part​_sw​_rd​_en​_ooutlc_tx_t
    lc​_iso​_part​_sw​_wr​_en​_ooutlc_tx_t
    lc​_seed​_hw​_rd​_en​_ooutlc_tx_t
    lc​_keymgr​_en​_ooutlc_tx_t
    lc​_escalate​_en​_ooutlc_tx_t
    lc​_keymgr​_div​_ooutlc_keymgr_div_t

    State group diversification value for keymgr

    Instantiations

    Block Diagram

    Module lc​_ctrl​_state​_decode

    This design unit is implemented in lc​_ctrl​_state​_decode.sv

    This file depends on: lc_ctrl_state_pkg.sv, lc_ctrl_pkg.sv

    Ports

    NameDirectionTypeDescription
    lc​_state​_valid​_iinlogic

    Life cycle state vector.

    lc​_state​_iinlc_state_e
    lc​_id​_state​_iinlc_id_state_e
    lc​_cnt​_iinlc_cnt_e
    fsm​_state​_iinfsm_state_e

    Main FSM state.

    dec​_lc​_state​_ooutdec_lc_state_e

    Decoded state vector.

    dec​_lc​_id​_state​_ooutdec_lc_id_state_e
    dec​_lc​_cnt​_ooutdec_lc_cnt_t
    state​_invalid​_error​_ooutlogic

    Block Diagram

    Module lc​_ctrl​_state​_transition

    This design unit is implemented in lc​_ctrl​_state​_transition.sv

    This file depends on: lc_ctrl_state_pkg.sv, lc_ctrl_pkg.sv

    Ports

    NameDirectionTypeDescription
    lc​_state​_iinlc_state_e

    Life cycle state vector.

    lc​_cnt​_iinlc_cnt_e
    fsm​_state​_iinfsm_state_e

    Main FSM state.

    dec​_lc​_state​_iindec_lc_state_e

    Decoded lc state input

    trans​_target​_iindec_lc_state_e

    Transition target.

    next​_lc​_state​_ooutlc_state_e

    Updated state vector.

    next​_lc​_cnt​_ooutlc_cnt_e
    trans​_cnt​_oflw​_error​_ooutlogic

    If the transition counter is maxed out

    trans​_invalid​_error​_ooutlogic

    Block Diagram

    State Machines

    Module otbn​_alu​_base

    This design unit is implemented in otbn​_alu​_base.sv

    This file depends on: otbn_pkg.sv

    Description

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Block is combinatorial; clk/rst are for assertions only.

    rst​_niinlogic
    operation​_iinalu_base_operation_t
    comparison​_iinalu_base_comparison_t
    operation​_result​_oout[31:0] logic
    comparison​_result​_ooutlogic

    Block Diagram

    Module otbn​_alu​_bignum

    This design unit is implemented in otbn​_alu​_bignum.sv

    This file depends on: uvm_pkg.sv, otbn_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    operation​_iinalu_bignum_operation_t
    operation​_result​_oout[WLEN-1:0] logic
    ispr​_addr​_iinispr_e
    ispr​_base​_wdata​_iin[31:0] logic
    ispr​_base​_wr​_en​_iin[BaseWordsPerWLEN-1:0] logic
    ispr​_bignum​_wdata​_iin[WLEN-1:0] logic
    ispr​_bignum​_wr​_en​_iinlogic
    ispr​_rdata​_oout[WLEN-1:0] logic
    ispr​_acc​_iin[WLEN-1:0] logic
    ispr​_acc​_wr​_data​_oout[WLEN-1:0] logic
    ispr​_acc​_wr​_en​_ooutlogic
    mac​_operation​_flags​_iinflags_t
    mac​_operation​_flags​_en​_iinflags_t
    rnd​_iin[WLEN-1:0] logic

    Block Diagram

    Module otbn​_controller

    This design unit is implemented in otbn​_controller.sv

    This file depends on: uvm_pkg.sv, otbn_loop_controller.sv, prim_util_pkg.sv, otbn_pkg.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    ImemSizeByteint4096

    Size of the instruction memory, in bytes

    DmemSizeByteint4096

    Size of the data memory, in bytes

    ImemAddrWidthintprim_util_pkg::vbits(ImemSizeByte)
    DmemAddrWidthintprim_util_pkg::vbits(DmemSizeByte)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    start​_iinlogic

    start the processing at start_addr_i

    done​_ooutlogic

    processing done, signaled by ECALL or error occurring

    err​_bits​_oouterr_bits_t

    valid when done_o is asserted

    start​_addr​_iin[ImemAddrWidth-1:0] logic
    insn​_fetch​_req​_valid​_ooutlogic

    Next instruction selection (to instruction fetch)

    insn​_fetch​_req​_addr​_oout[ImemAddrWidth-1:0] logic
    insn​_fetch​_err​_iinlogic

    Error from fetch requested last cycle

    insn​_valid​_iinlogic

    Fetched/decoded instruction

    insn​_illegal​_iinlogic
    insn​_addr​_iin[ImemAddrWidth-1:0] logic
    insn​_dec​_base​_iininsn_dec_base_t

    Decoded instruction data, matching the "Decoding" section of the specification.

    insn​_dec​_bignum​_iininsn_dec_bignum_t
    insn​_dec​_shared​_iininsn_dec_shared_t
    rf​_base​_wr​_addr​_oout[4:0] logic

    Base register file

    rf​_base​_wr​_en​_ooutlogic
    rf​_base​_wr​_commit​_ooutlogic
    rf​_base​_wr​_data​_oout[31:0] logic
    rf​_base​_rd​_addr​_a​_oout[4:0] logic
    rf​_base​_rd​_en​_a​_ooutlogic
    rf​_base​_rd​_data​_a​_iin[31:0] logic
    rf​_base​_rd​_addr​_b​_oout[4:0] logic
    rf​_base​_rd​_en​_b​_ooutlogic
    rf​_base​_rd​_data​_b​_iin[31:0] logic
    rf​_base​_rd​_commit​_ooutlogic
    rf​_base​_call​_stack​_err​_iinlogic
    rf​_bignum​_wr​_addr​_oout[4:0] logic

    Bignum register file (WDRs)

    rf​_bignum​_wr​_en​_oout[1:0] logic
    rf​_bignum​_wr​_data​_oout[WLEN-1:0] logic
    rf​_bignum​_rd​_addr​_a​_oout[4:0] logic
    rf​_bignum​_rd​_data​_a​_iin[WLEN-1:0] logic
    rf​_bignum​_rd​_addr​_b​_oout[4:0] logic
    rf​_bignum​_rd​_data​_b​_iin[WLEN-1:0] logic
    alu​_base​_operation​_ooutalu_base_operation_t

    Base ALU

    alu​_base​_comparison​_ooutalu_base_comparison_t
    alu​_base​_operation​_result​_iin[31:0] logic
    alu​_base​_comparison​_result​_iinlogic
    alu​_bignum​_operation​_ooutalu_bignum_operation_t

    Bignum ALU

    alu​_bignum​_operation​_result​_iin[WLEN-1:0] logic
    mac​_bignum​_operation​_ooutmac_bignum_operation_t

    Bignum MAC

    mac​_bignum​_operation​_result​_iin[WLEN-1:0] logic
    mac​_bignum​_en​_ooutlogic
    lsu​_load​_req​_ooutlogic

    LSU

    lsu​_store​_req​_ooutlogic
    lsu​_req​_subset​_ooutinsn_subset_e
    lsu​_addr​_oout[DmemAddrWidth-1:0] logic
    lsu​_base​_wdata​_oout[31:0] logic
    lsu​_bignum​_wdata​_oout[WLEN-1:0] logic
    lsu​_base​_rdata​_iin[31:0] logic
    lsu​_bignum​_rdata​_iin[WLEN-1:0] logic
    lsu​_rdata​_err​_iinlogic
    ispr​_addr​_ooutispr_e

    Internal Special-Purpose Registers (ISPRs)

    ispr​_base​_wdata​_oout[31:0] logic
    ispr​_base​_wr​_en​_oout[BaseWordsPerWLEN-1:0] logic
    ispr​_bignum​_wdata​_oout[WLEN-1:0] logic
    ispr​_bignum​_wr​_en​_ooutlogic
    ispr​_rdata​_iin[WLEN-1:0] logic

    Instantiations

    Block Diagram

    State Machines

    Module otbn​_decoder

    This design unit is implemented in otbn​_decoder.sv

    This file depends on: uvm_pkg.sv, otbn_pkg.sv

    Description

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    For assertions only.

    rst​_niinlogic
    insn​_fetch​_resp​_data​_iin[31:0] logic

    instruction data to be decoded

    insn​_fetch​_resp​_valid​_iinlogic
    insn​_valid​_ooutlogic

    Decoded instruction

    insn​_illegal​_ooutlogic
    insn​_dec​_base​_ooutinsn_dec_base_t
    insn​_dec​_bignum​_ooutinsn_dec_bignum_t
    insn​_dec​_shared​_ooutinsn_dec_shared_t

    Block Diagram

    Module otbn​_instruction​_fetch

    This design unit is implemented in otbn​_instruction​_fetch.sv

    This file depends on: prim_util_pkg.sv, otbn_pkg.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    ImemSizeByteint4096
    ImemAddrWidthintprim_util_pkg::vbits(ImemSizeByte)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    imem​_req​_ooutlogic

    Instruction memory (IMEM) interface. Read-only.

    imem​_addr​_oout[ImemAddrWidth-1:0] logic
    imem​_rdata​_iin[31:0] logic
    imem​_rvalid​_iinlogic
    imem​_rerror​_iinlogic
    insn​_fetch​_req​_valid​_iinlogic

    Next instruction selection (to instruction fetch)

    insn​_fetch​_req​_addr​_iin[ImemAddrWidth-1:0] logic
    insn​_fetch​_resp​_valid​_ooutlogic

    Decoded instruction

    insn​_fetch​_resp​_addr​_oout[ImemAddrWidth-1:0] logic
    insn​_fetch​_resp​_data​_oout[31:0] logic
    insn​_fetch​_err​_ooutlogic

    ECC error seen in instruction fetch

    Block Diagram

    Module otbn​_lsu

    This design unit is implemented in otbn​_lsu.sv

    This file depends on: uvm_pkg.sv, prim_util_pkg.sv, otbn_pkg.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    DmemSizeByteint4096
    DmemAddrWidthintprim_util_pkg::vbits(DmemSizeByte)
    BaseWordsPerWLenintWLEN / 32
    BaseWordAddrWintprim_util_pkg::vbits(WLEN/8)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    dmem​_req​_ooutlogic

    Data memory (DMEM) interface

    dmem​_write​_ooutlogic
    dmem​_addr​_oout[DmemAddrWidth-1:0] logic
    dmem​_wdata​_oout[WLEN-1:0] logic
    dmem​_wmask​_oout[WLEN-1:0] logic
    dmem​_rdata​_iin[WLEN-1:0] logic
    dmem​_rvalid​_iinlogic
    dmem​_rerror​_iinlogic
    lsu​_load​_req​_iinlogic
    lsu​_store​_req​_iinlogic
    lsu​_req​_subset​_iininsn_subset_e
    lsu​_addr​_iin[DmemAddrWidth-1:0] logic
    lsu​_base​_wdata​_iin[31:0] logic
    lsu​_bignum​_wdata​_iin[WLEN-1:0] logic
    lsu​_base​_rdata​_oout[31:0] logic
    lsu​_bignum​_rdata​_oout[WLEN-1:0] logic
    lsu​_rdata​_err​_ooutlogic

    Block Diagram

    Module otbn​_mac​_bignum

    This design unit is implemented in otbn​_mac​_bignum.sv

    This file depends on: uvm_pkg.sv, otbn_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    QWLENintWLEN / 4

    The MAC operates on quarter-words, QWLEN gives the number of bits in a quarter-word.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    operation​_iinmac_bignum_operation_t
    mac​_en​_iinlogic
    operation​_result​_oout[WLEN-1:0] logic
    operation​_flags​_ooutflags_t
    operation​_flags​_en​_ooutflags_t
    ispr​_acc​_oout[WLEN-1:0] logic
    ispr​_acc​_wr​_data​_iin[WLEN-1:0] logic
    ispr​_acc​_wr​_en​_iinlogic

    Block Diagram

    Module otbn​_rf​_base

    This design unit is implemented in otbn​_rf​_base.sv

    This file depends on: otbn_rf_base_fpga.sv, otbn_rf_base_ff.sv, otbn_stack.sv, otbn_pkg.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    RegFileregfile_eRegFileFF

    Register file implementation selection, see otbn_pkg.sv.

    CallStackRegIndexint1
    CallStackDepthint8

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wr​_addr​_iin[4:0] logic
    wr​_en​_iinlogic
    wr​_data​_iin[31:0] logic
    wr​_commit​_iinlogic
    rd​_addr​_a​_iin[4:0] logic
    rd​_en​_a​_iinlogic
    rd​_data​_a​_oout[31:0] logic
    rd​_addr​_b​_iin[4:0] logic
    rd​_en​_b​_iinlogic
    rd​_data​_b​_oout[31:0] logic
    rd​_commit​_iinlogic
    call​_stack​_err​_ooutlogic

    Instantiations

    Block Diagram

    Module otbn​_rf​_bignum​_ff

    This design unit is implemented in otbn​_rf​_bignum​_ff.sv

    This file depends on: otbn_pkg.sv

    Description

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wr​_addr​_iin[WdrAw-1:0] logic
    wr​_en​_iin[1:0] logic
    wr​_data​_iin[WLEN-1:0] logic
    rd​_addr​_a​_iin[WdrAw-1:0] logic
    rd​_data​_a​_oout[WLEN-1:0] logic
    rd​_addr​_b​_iin[WdrAw-1:0] logic
    rd​_data​_b​_oout[WLEN-1:0] logic

    Block Diagram

    Module otbn​_rf​_bignum​_fpga

    This design unit is implemented in otbn​_rf​_bignum​_fpga.sv

    This file depends on: otbn_pkg.sv

    Description

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wr​_addr​_iin[WdrAw-1:0] logic
    wr​_en​_iin[1:0] logic
    wr​_data​_iin[WLEN-1:0] logic
    rd​_addr​_a​_iin[WdrAw-1:0] logic
    rd​_data​_a​_oout[WLEN-1:0] logic
    rd​_addr​_b​_iin[WdrAw-1:0] logic
    rd​_data​_b​_oout[WLEN-1:0] logic

    Block Diagram

    Module otp​_ctrl​_ecc​_reg

    This design unit is implemented in otp​_ctrl​_ecc​_reg.sv

    This file depends on: prim_secded_72_64_dec.sv, uvm_pkg.sv, prim_secded_72_64_enc.sv, prim_util_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint64

    bit

    Depthint128
    Awintprim_util_pkg::vbits(Depth)

    derived parameter

    EccWidthint8

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wren​_iinlogic
    addr​_iin[Aw-1:0] logic
    wdata​_iin[Width-1:0] logic
    data​_oout[Width-1:0] [Depth-1:0] logic

    Concurrent output of the register state.

    ecc​_err​_ooutlogic

    Concurrent ECC check error is flagged via this signal.

    Instantiations

    Block Diagram

    Module pattgen​_chan

    This design unit is implemented in pattgen​_chan.sv

    This file depends on: pattgen_ctrl_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    ctrl​_iinpattgen_chan_ctrl_t
    pda​_ooutlogic
    pcl​_ooutlogic
    event​_done​_ooutlogic

    Block Diagram

    Package pattgen​_ctrl​_pkg

    This design unit is implemented in pattgen​_ctrl​_pkg.sv

    Module pinmux​_jtag​_buf

    This design unit is implemented in pinmux​_jtag​_buf.sv

    This file depends on: jtag_pkg.sv, prim_buf.sv, prim_clock_buf.sv

    Ports

    NameDirectionTypeDescription
    req​_iinjtag_req_t
    req​_ooutjtag_req_t
    rsp​_iinjtag_rsp_t
    rsp​_ooutjtag_rsp_t

    Instantiations

    Block Diagram

    Module prim​_arbiter​_ppc

    This design unit is implemented in prim​_arbiter​_ppc.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Nint8
    DWint32
    EnDataPortbit1

    Configurations EnDataPort: {0, 1}, if 0, input data will be ignored

    EnReqStabAbit1

    Non-functional parameter to switch on the request stability assertion

    IdxWint$clog2(N)

    Derived parameters

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_iin[N-1:0] logic
    data​_iin[DW-1:0] logic [N]
    gnt​_oout[N-1:0] logic
    idx​_oout[IdxW-1:0] logic
    valid​_ooutlogic
    data​_oout[DW-1:0] logic
    ready​_iinlogic

    Block Diagram

    Module prim​_buf

    This design unit is implemented in prim​_buf.sv

    This file depends on: prim_xilinx_buf.sv, prim_generic_buf.sv, prim_pkg.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    Implimpl_eprim_pkg::ImplGeneric

    Ports

    NameDirectionTypeDescription
    in​_iinlogic
    out​_ooutlogic

    Block Diagram

    Package prim​_cipher​_pkg

    This design unit is implemented in prim​_cipher​_pkg.sv

    Module prim​_diff​_decode

    This design unit is implemented in prim​_diff​_decode.sv

    This file depends on: prim_flop_2sync.sv, uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    AsyncOnbit1'b0

    enables additional synchronization logic

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    diff​_piinlogic

    input diff pair

    diff​_niinlogic
    level​_ooutlogic

    logical level and detected edges

    rise​_ooutlogic
    fall​_ooutlogic
    event​_ooutlogic

    either rise or fall

    sigint​_ooutlogic

    signal integrity issue detected

    Block Diagram

    State Machines

    Module prim​_filter

    This design unit is implemented in prim​_filter.sv

    Parameters

    NameTypeDefault ValueDescription
    Cyclesint4

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    enable​_iinlogic
    filter​_iinlogic
    filter​_ooutlogic

    Block Diagram

    Module prim​_generic​_clock​_buf

    This design unit is implemented in prim​_generic​_clock​_buf.sv

    Description

    prim_generic_clock_buf

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    clk​_ooutlogic

    Block Diagram

    Module prim​_generic​_clock​_gating

    This design unit is implemented in prim​_generic​_clock​_gating.sv

    Parameters

    NameTypeDefault ValueDescription
    NoFpgaGatebit1'b0

    this parameter has no function in generic

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    en​_iinlogic
    test​_en​_iinlogic
    clk​_ooutlogic

    Block Diagram

    Module prim​_generic​_clock​_inv

    This design unit is implemented in prim​_generic​_clock​_inv.sv

    This file depends on: prim_clock_mux2.sv

    Parameters

    NameTypeDefault ValueDescription
    HasScanModebit1'b1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    scanmode​_iinlogic
    clk​_nooutlogic

    Inverted

    Block Diagram

    Module prim​_generic​_clock​_mux2

    This design unit is implemented in prim​_generic​_clock​_mux2.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    NoFpgaBufGbit1'b0

    this parameter serves no function in the generic model

    Ports

    NameDirectionTypeDescription
    clk0​_iinlogic
    clk1​_iinlogic
    sel​_iinlogic
    clk​_ooutlogic

    Block Diagram

    Module prim​_generic​_flash

    This design unit is implemented in prim​_generic​_flash.sv

    This file depends on: tlul_adapter_sram.sv, flash_phy_pkg.sv, flash_ctrl_pkg.sv, tlul_pkg.sv, lc_ctrl_pkg.sv, prim_generic_flash_bank.sv, prim_ram_1p.sv

    Description

    prim_generic_flash

    Parameters

    NameTypeDefault ValueDescription
    NumBanksint2

    number of banks

    InfosPerBankint1

    info pages per bank

    InfoTypesint1

    different info types

    InfoTypesWidthint1

    different info types

    PagesPerBankint256

    data pages per bank

    WordsPerPageint256

    words per page

    DataWidthint32

    bits per word

    MetaDataWidthint12

    metadata such as ECC

    TestModeWidthint4
    CfgRegsint21
    CfgAddrWidthint$clog2(CfgRegs)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    flash​_req​_iin[NumBanks-1:0] flash_phy_prim_flash_req_t
    flash​_rsp​_oout[NumBanks-1:0] flash_phy_prim_flash_rsp_t
    prog​_type​_avail​_oout[flash_phy_pkg::ProgTypes-1:0] logic
    init​_busy​_ooutlogic
    tck​_iinlogic
    tdi​_iinlogic
    tms​_iinlogic
    tdo​_ooutlogic
    bist​_enable​_iinlc_tx_t
    scanmode​_iinlc_tx_t
    scan​_en​_iinlogic
    scan​_rst​_niinlogic
    flash​_power​_ready​_h​_iinlogic
    flash​_power​_down​_h​_iinlogic
    flash​_test​_mode​_a​_iin[TestModeWidth-1:0] logic
    flash​_test​_voltage​_h​_iinlogic
    flash​_err​_ooutlogic
    flash​_alert​_pooutlogic
    flash​_alert​_nooutlogic
    flash​_alert​_ack​_iinlogic
    flash​_alert​_trig​_iinlogic
    tl​_iintl_h2d_t
    tl​_oouttl_d2h_t
    devmode​_iinlogic

    Instantiations

    Block Diagram

    Module prim​_generic​_flop

    This design unit is implemented in prim​_generic​_flop.sv

    Description

    prim_generic_flop

    Parameters

    NameTypeDefault ValueDescription
    Widthint1
    WidthSubOneintWidth-1
    ResetValue[WidthSubOne:0] logic0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    d​_iin[Width-1:0] logic
    q​_oout[Width-1:0] logic

    Block Diagram

    Module prim​_generic​_otp

    This design unit is implemented in prim​_generic​_otp.sv

    This file depends on: tlul_adapter_sram.sv, prim_flop.sv, uvm_pkg.sv, prim_ram_1p_adv.sv, prim_util_pkg.sv, prim_otp_pkg.sv, tlul_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint16

    Native OTP word size. This determines the size_i granule.

    Depthint1024
    SizeWidthint2

    This determines the maximum number of native words that can be transferred accross the interface in one cycle.

    PwrSeqWidthint2

    Width of the power sequencing signal.

    TlDepthint16

    Number of Test TL-UL words

    AddrWidthintprim_util_pkg::vbits(Depth)

    Derived parameters

    IfWidthint2**SizeWidth*Width
    MemInitFileunknown""

    VMEM file to initialize the memory with

    TlAddrWidthintprim_util_pkg::vbits(TlDepth)

    Put down a register that can be used to test the TL interface. TODO: this emulation may need to be adjusted, once closed source wrapper is implemented.

    StateWidthint10

    Encoding generated with ./sparse-fsm-encode.py -d 5 -m 8 -n 10 Hamming distance histogram:

    0: -- 1: -- 2: -- 3: -- 4: -- 5: |||||||||||||||||||| (53.57%) 6: ||||||||||||| (35.71%) 7: | (3.57%) 8: || (7.14%) 9: -- 10: --

    Minimum Hamming distance: 5 Maximum Hamming distance: 8

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    pwr​_seq​_oout[PwrSeqWidth-1:0] logic

    Macro-specific power sequencing signals to/from AST

    pwr​_seq​_h​_iin[PwrSeqWidth-1:0] logic
    test​_tl​_iintl_h2d_t

    Test interface

    test​_tl​_oouttl_d2h_t
    ready​_ooutlogic

    Ready valid handshake for read/write command

    valid​_iinlogic
    size​_iin[SizeWidth-1:0] logic

    #(Native words)-1, e.g. size == 0 for 1 native word.

    cmd​_iincmd_e

    00: read command, 01: write command, 11: init command

    addr​_iin[AddrWidth-1:0] logic
    wdata​_iin[IfWidth-1:0] logic
    valid​_ooutlogic

    Response channel

    rdata​_oout[IfWidth-1:0] logic
    err​_oouterr_e

    Instantiations

    Block Diagram

    State Machines

    Module prim​_generic​_rom

    This design unit is implemented in prim​_generic​_rom.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint32
    Depthint2048

    8kB default

    MemInitFileunknown""

    VMEM file to initialize the memory with

    Awint$clog2(Depth)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    req​_iinlogic
    addr​_iin[Aw-1:0] logic
    rdata​_oout[Width-1:0] logic

    Block Diagram

    Module prim​_present

    This design unit is implemented in prim​_present.sv

    This file depends on: uvm_pkg.sv, prim_cipher_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    DataWidthint64

    {32, 64}

    KeyWidthint128

    {64, 80, 128}

    NumRoundsint31

    Number of rounds to perform in total (>0)

    NumPhysRoundsintNumRounds

    Number of physically instantiated PRESENT rounds. This can be used to construct e.g. an iterative full-round implementation that only has one physical round instance by setting NumRounds = 31 and NumPhysRounds = 1. Note that NumPhysRounds needs to divide NumRounds.

    Decryptbit0

    0: encrypt, 1: decrypt

    LastRoundIdxint(Decrypt != 0 || NumRounds == 31) ? 0 : NumRounds+1

    This only needs to be applied after the last round. Note that for a full-round implementation the output index will be 0 for enc/dec for the last round (either due to wraparound or subtraction).

    Ports

    NameDirectionTypeDescription
    data​_iin[DataWidth-1:0] logic
    key​_iin[KeyWidth-1:0] logic
    idx​_iin[4:0] logic

    Starting round index for keyschedule 1 ... 31. Set this to 5'd1 for a fully unrolled encryption, and 5'd31 for a fully unrolled decryption.

    data​_oout[DataWidth-1:0] logic
    key​_oout[KeyWidth-1:0] logic
    idx​_oout[4:0] logic

    Next round index for keyschedule (Enc: idx_i + NumPhysRounds, Dec: idx_i - NumPhysRounds) Can be ignored for a fully unrolled implementation.

    Block Diagram

    Module prim​_ram​_1p

    This design unit is implemented in prim​_ram​_1p.sv

    This file depends on: prim_generic_ram_1p.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    Widthint32

    bit

    Depthint128
    DataBitsPerMaskint1

    Number of data bits per bit of write mask

    MemInitFileunknown""

    VMEM file to initialize the memory with

    Awint$clog2(Depth)

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    req​_iinlogic
    write​_iinlogic
    addr​_iin[Aw-1:0] logic
    wdata​_iin[Width-1:0] logic
    wmask​_iin[Width-1:0] logic
    rdata​_oout[Width-1:0] logic

    Read data. Data is returned one cycle after req_i is high.

    Block Diagram

    Module prim​_ram​_2p

    This design unit is implemented in prim​_ram​_2p.sv

    This file depends on: prim_generic_ram_2p.sv

    Description

    This is to prevent AscentLint warnings in the generated abstract prim wrapper. These warnings occur due to the .* use. TODO: we may want to move these inline waivers into a separate, generated waiver file for consistency. ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ

    Parameters

    NameTypeDefault ValueDescription
    Widthint32

    bit

    Depthint128
    DataBitsPerMaskint1

    Number of data bits per bit of write mask

    MemInitFileunknown""

    VMEM file to initialize the memory with

    Awint$clog2(Depth)

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_a​_iinlogic
    clk​_b​_iinlogic
    a​_req​_iinlogic
    a​_write​_iinlogic
    a​_addr​_iin[Aw-1:0] logic
    a​_wdata​_iin[Width-1:0] logic
    a​_wmask​_iin[Width-1:0] logic
    a​_rdata​_oout[Width-1:0] logic
    b​_req​_iinlogic
    b​_write​_iinlogic
    b​_addr​_iin[Aw-1:0] logic
    b​_wdata​_iin[Width-1:0] logic
    b​_wmask​_iin[Width-1:0] logic
    b​_rdata​_oout[Width-1:0] logic

    Block Diagram

    Module prim​_secded​_22​_16​_dec

    This design unit is implemented in prim​_secded​_22​_16​_dec.sv

    Ports

    NameDirectionTypeDescription
    inin[21:0] logic
    d​_oout[15:0] logic
    syndrome​_oout[5:0] logic
    err​_oout[1:0] logic

    Block Diagram

    Module prim​_secded​_22​_16​_enc

    This design unit is implemented in prim​_secded​_22​_16​_enc.sv

    Ports

    NameDirectionTypeDescription
    inin[15:0] logic
    outout[21:0] logic

    Block Diagram

    Module prim​_secded​_39​_32​_dec

    This design unit is implemented in prim​_secded​_39​_32​_dec.sv

    Ports

    NameDirectionTypeDescription
    inin[38:0] logic
    d​_oout[31:0] logic
    syndrome​_oout[6:0] logic
    err​_oout[1:0] logic

    Block Diagram

    Module prim​_secded​_39​_32​_enc

    This design unit is implemented in prim​_secded​_39​_32​_enc.sv

    Ports

    NameDirectionTypeDescription
    inin[31:0] logic
    outout[38:0] logic

    Block Diagram

    Module prim​_secded​_64​_57​_enc

    This design unit is implemented in prim​_secded​_64​_57​_enc.sv

    Ports

    NameDirectionTypeDescription
    inin[56:0] logic
    outout[63:0] logic

    Block Diagram

    Module prim​_secded​_hamming​_22​_16​_dec

    This design unit is implemented in prim​_secded​_hamming​_22​_16​_dec.sv

    Ports

    NameDirectionTypeDescription
    inin[21:0] logic
    d​_oout[15:0] logic
    syndrome​_oout[5:0] logic
    err​_oout[1:0] logic

    Block Diagram

    Module prim​_secded​_hamming​_22​_16​_enc

    This design unit is implemented in prim​_secded​_hamming​_22​_16​_enc.sv

    Ports

    NameDirectionTypeDescription
    inin[15:0] logic
    outout[21:0] logic

    Block Diagram

    Module prim​_secded​_hamming​_39​_32​_dec

    This design unit is implemented in prim​_secded​_hamming​_39​_32​_dec.sv

    Ports

    NameDirectionTypeDescription
    inin[38:0] logic
    d​_oout[31:0] logic
    syndrome​_oout[6:0] logic
    err​_oout[1:0] logic

    Block Diagram

    Module prim​_secded​_hamming​_39​_32​_enc

    This design unit is implemented in prim​_secded​_hamming​_39​_32​_enc.sv

    Ports

    NameDirectionTypeDescription
    inin[31:0] logic
    outout[38:0] logic

    Block Diagram

    Module prim​_slicer

    This design unit is implemented in prim​_slicer.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    InWint64
    OutWint8
    IndexWint4
    UnrollWintOutW*(2**IndexW)

    Ports

    NameDirectionTypeDescription
    sel​_iin[IndexW-1:0] logic
    data​_iin[InW-1:0] logic
    data​_oout[OutW-1:0] logic

    Block Diagram

    Module prim​_subreg​_arb

    This design unit is implemented in prim​_subreg​_arb.sv

    Parameters

    NameTypeDefault ValueDescription
    DWint32
    SWACCESSunknown"RW"

    {RW, RO, WO, W1C, W1S, W0C, RC}

    Ports

    NameDirectionTypeDescription
    weinlogic

    From SW: valid for RW, WO, W1C, W1S, W0C, RC. In case of RC, top connects read pulse to we.

    wdin[DW-1:0] logic
    deinlogic

    From HW: valid for HRW, HWO.

    din[DW-1:0] logic
    qin[DW-1:0] logic

    From register: actual reg value.

    wr​_enoutlogic

    To register: actual write enable and write data.

    wr​_dataout[DW-1:0] logic

    Block Diagram

    Module prim​_subreg​_ext

    This design unit is implemented in prim​_subreg​_ext.sv

    Parameters

    NameTypeDefault ValueDescription
    DWint32

    Ports

    NameDirectionTypeDescription
    reinlogic
    weinlogic
    wdin[DW-1:0] logic
    din[DW-1:0] logic
    qeoutlogic

    output to HW and Reg Read

    qreoutlogic
    qout[DW-1:0] logic
    qsout[DW-1:0] logic

    Block Diagram

    Module prim​_subreg​_shadow

    This design unit is implemented in prim​_subreg​_shadow.sv

    This file depends on: prim_subreg_arb.sv, prim_subreg.sv

    Parameters

    NameTypeDefault ValueDescription
    DWint32
    SWACCESSunknown"RW"

    {RW, RO, WO, W1C, W1S, W0C, RC}

    RESVAL[DW-1:0] logic'0

    reset value

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    reinlogic

    From SW: valid for RW, WO, W1C, W1S, W0C, RC. SW reads clear phase unless SWACCESS is RO.

    weinlogic

    In case of RC, top connects read pulse to we.

    wdin[DW-1:0] logic
    deinlogic

    From HW: valid for HRW, HWO.

    din[DW-1:0] logic
    qeoutlogic

    Output to HW and Reg Read

    qout[DW-1:0] logic
    qsout[DW-1:0] logic
    err​_updateoutlogic

    Error conditions

    err​_storageoutlogic

    Instantiations

    Block Diagram

    Module prim​_sync​_reqack

    This design unit is implemented in prim​_sync​_reqack.sv

    This file depends on: prim_flop_2sync.sv, uvm_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_src​_iinlogic

    REQ side, SRC domain

    rst​_src​_niinlogic

    REQ side, SRC domain

    clk​_dst​_iinlogic

    ACK side, DST domain

    rst​_dst​_niinlogic

    ACK side, DST domain

    src​_req​_iinlogic

    REQ side, SRC domain

    src​_ack​_ooutlogic

    REQ side, SRC domain

    dst​_req​_ooutlogic

    ACK side, DST domain

    dst​_ack​_iinlogic

    ACK side, DST domain

    Instantiations

    Block Diagram

    State Machines

    Module prim​_xilinx​_clock​_buf

    This design unit is implemented in prim​_xilinx​_clock​_buf.sv

    This file depends on: BUFG.v

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    clk​_ooutlogic

    Instantiations

    Block Diagram

    Module prim​_xilinx​_clock​_gating

    This design unit is implemented in prim​_xilinx​_clock​_gating.sv

    This file depends on: BUFGCE.v

    Parameters

    NameTypeDefault ValueDescription
    NoFpgaGatebit1'b0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    en​_iinlogic
    test​_en​_iinlogic
    clk​_ooutlogic

    Block Diagram

    Module prim​_xilinx​_clock​_mux2

    This design unit is implemented in prim​_xilinx​_clock​_mux2.sv

    This file depends on: uvm_pkg.sv, BUFGMUX.v

    Parameters

    NameTypeDefault ValueDescription
    NoFpgaBufGbit1'b0

    Ports

    NameDirectionTypeDescription
    clk0​_iinlogic
    clk1​_iinlogic
    sel​_iinlogic
    clk​_ooutlogic

    Block Diagram

    Module prim​_xilinx​_flop

    This design unit is implemented in prim​_xilinx​_flop.sv

    Description

    prim_xilinx_flop

    Parameters

    NameTypeDefault ValueDescription
    Widthint1
    WidthSubOneintWidth-1
    ResetValue[WidthSubOne:0] logic0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    d​_iin[Width-1:0] logic
    q​_oout[Width-1:0] logic

    Prevent Vivado from optimizing this signal away.

    Block Diagram

    Module sha2​_pad

    This design unit is implemented in sha2​_pad.sv

    This file depends on: hmac_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wipe​_secretinlogic
    wipe​_vinsha_word_t
    fifo​_rvalidinlogic

    To actual FIFO

    fifo​_rdatainsha_fifo_t
    fifo​_rreadyoutlogic
    shaf​_rvalidoutlogic

    from SHA2 compress engine

    shaf​_rdataoutsha_word_t
    shaf​_rreadyinlogic
    sha​_eninlogic
    hash​_startinlogic
    hash​_processinlogic
    hash​_doneinlogic
    message​_lengthin[63:0] logic

    of bytes in bits (8 bits granularity)

    msg​_feed​_completeoutlogic

    Indicates, all message is feeded

    Block Diagram

    State Machines

    Module sha3pad

    This design unit is implemented in sha3pad.sv

    This file depends on: prim_slicer.sv, uvm_pkg.sv, sha3_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    EnMaskingbit0
    Shareint(EnMasking) ? 2 : 1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    msg​_valid​_iinlogic

    Message interface (FIFO)

    msg​_data​_iin[MsgWidth-1:0] logic [Share]
    msg​_strb​_iin[MsgStrbW-1:0] logic

    one strobe for shares

    msg​_ready​_ooutlogic
    ns​_data​_iin[NSRegisterSize*8-1:0] logic

    See sha3_pkg for details

    keccak​_valid​_ooutlogic

    output to keccak_round: message path

    keccak​_addr​_oout[KeccakMsgAddrW-1:0] logic
    keccak​_data​_oout[MsgWidth-1:0] logic [Share]
    keccak​_ready​_iinlogic
    keccak​_run​_ooutlogic

    keccak_round control and status run initiates the keccak_round to process full keccak_f (24rounds). complete is an input from keccak round showing the current keccak_f is completed.

    keccak​_complete​_iinlogic
    mode​_iinsha3_mode_e

    configurations

    strength​_iinkeccak_strength_e

    strength_i is used in bytepad operation. bytepad() is used in cSHAKE only. SHA3, SHAKE doesn't have encode_N,S

    start​_iinlogic

    control signal start_i is a pulse signal triggers the padding logic (and the rest of SHA) to accept the incoming messages. This signal is used in the pad module, to initiate the prefix transmitting to keccak_round

    process​_iinlogic

    process_i is a pulse signal triggers the pad logic to stop receiving the message from MSG_FIFO and pad the trailing bits specified in the SHA3 standard. Look at funcpad signal for the values.

    done​_iinlogic

    done_i is a pulse signal to make the pad logic to clear internal variables and to move back to the Idle state for next hashing process. done_i may not needed if sw controls the keccak_round directly.

    absorbed​_ooutlogic

    Indication of the Keccak Sponge Absorbing is complete, it is time for SW to control the Keccak-round if it needs more digest, or complete by asserting done_i

    Instantiations

    Block Diagram

    State Machines

    Module tlul​_err​_resp

    This design unit is implemented in tlul​_err​_resp.sv

    This file depends on: top_pkg.sv, tlul_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tl​_h​_iintl_h2d_t
    tl​_h​_oouttl_d2h_t

    Block Diagram

    Module tlul​_gen​_payload​_chk

    This design unit is implemented in tlul​_gen​_payload​_chk.sv

    This file depends on: prim_secded_64_57_enc.sv, uvm_pkg.sv, tlul_pkg.sv

    Description

    tlul_payload_chk

    Ports

    NameDirectionTypeDescription
    tl​_iintl_d2h_t

    TL-UL interface

    tl​_oouttl_d2h_t

    Instantiations

    Block Diagram

    Module tlul​_payload​_chk

    This design unit is implemented in tlul​_payload​_chk.sv

    This file depends on: uvm_pkg.sv, prim_secded_64_57_dec.sv, tlul_pkg.sv

    Description

    tlul_payload_chk

    Ports

    NameDirectionTypeDescription
    tl​_iintl_h2d_t

    TL-UL interface

    err​_ooutlogic

    error output

    Instantiations

    Block Diagram

    Module uart​_rx

    This design unit is implemented in uart​_rx.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    rx​_enableinlogic
    tick​_baud​_x16inlogic
    parity​_enableinlogic
    parity​_oddinlogic
    tick​_baudoutlogic
    rx​_validoutlogic
    rx​_dataout[7:0] logic
    idleoutlogic
    frame​_erroutlogic
    rx​_parity​_erroutlogic
    rxinlogic

    Block Diagram

    Module uart​_tx

    This design unit is implemented in uart​_tx.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    tx​_enableinlogic
    tick​_baud​_x16inlogic
    parity​_enableinlogic
    wrinlogic
    wr​_parityinlogic
    wr​_datain[7:0] logic
    idleoutlogic
    txoutlogic

    Block Diagram

    Module usb​_fs​_nb​_pe

    This design unit is implemented in usb​_fs​_nb​_pe.sv

    This file depends on: usb_fs_tx_mux.sv, usb_fs_nb_in_pe.sv, usb_fs_nb_out_pe.sv, usb_consts_pkg.sv, usb_fs_tx.sv, usb_fs_rx.sv

    Parameters

    NameTypeDefault ValueDescription
    NumOutEpsint2
    NumInEpsint2
    MaxPktSizeByteint32
    PktWint$clog2(MaxPktSizeByte)

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_48mhz​_iinlogic
    rst​_niinlogic

    Async. reset, active low

    link​_reset​_iinlogic

    USB reset, sync to 48 MHz, active high

    dev​_addr​_iin[6:0] logic
    cfg​_eop​_single​_bit​_iinlogic

    1: detect a single SE0 bit as EOP

    cfg​_rx​_differential​_iinlogic

    1: use differential rx data on usb_d_i

    tx​_osc​_test​_mode​_iinlogic

    Oscillator test mode (constantly output JK)

    data​_toggle​_clear​_iin[NumOutEps-1:0] logic

    Clear the data toggles for an EP

    out​_ep​_current​_oout[3:0] logic

    Other signals address to this ep

    out​_ep​_data​_put​_ooutlogic

    put the data (put addr advances after)

    out​_ep​_put​_addr​_oout[PktW - 1:0] logic

    Offset to put data (0..pktlen)

    out​_ep​_data​_oout[7:0] logic
    out​_ep​_newpkt​_ooutlogic

    New OUT pkt start (with in_ep_current_o update)

    out​_ep​_acked​_ooutlogic

    good termination, device has acked

    out​_ep​_rollback​_ooutlogic

    bad termination, discard data

    out​_ep​_setup​_oout[NumOutEps-1:0] logic
    out​_ep​_full​_iin[NumOutEps-1:0] logic

    Cannot accept data

    out​_ep​_stall​_iin[NumOutEps-1:0] logic

    Stalled

    out​_ep​_iso​_iin[NumOutEps-1:0] logic

    Configure endpoint in isochronous mode

    in​_ep​_current​_oout[3:0] logic

    Other signals addressed to this ep

    in​_ep​_rollback​_ooutlogic

    Bad termination, rollback transaction

    in​_ep​_xfr​_end​_ooutlogic

    good termination, transaction complete

    in​_ep​_get​_addr​_oout[PktW - 1:0] logic

    Offset requested (0..pktlen)

    in​_ep​_data​_get​_ooutlogic

    Accept data (get_addr advances too)

    in​_ep​_newpkt​_ooutlogic

    New IN pkt start (with in_ep_current_o update)

    in​_ep​_stall​_iin[NumInEps-1:0] logic

    Endpoint in a stall state

    in​_ep​_has​_data​_iin[NumInEps-1:0] logic

    Endpoint has data to supply

    in​_ep​_data​_iin[7:0] logic

    Data for current get_addr

    in​_ep​_data​_done​_iin[NumInEps-1:0] logic

    Set when out of data

    in​_ep​_iso​_iin[NumInEps-1:0] logic

    Configure endpoint in isochronous mode

    sof​_valid​_ooutlogic

    sof interface

    frame​_index​_oout[10:0] logic
    rx​_jjj​_det​_ooutlogic

    RX line status

    rx​_crc​_err​_ooutlogic

    RX errors

    rx​_pid​_err​_ooutlogic
    rx​_bitstuff​_err​_ooutlogic
    usb​_d​_iinlogic

    USB RX Interface (synchronous) //

    usb​_dp​_iinlogic
    usb​_dn​_iinlogic
    usb​_d​_ooutlogic

    USB TX Interface (synchronous) //

    usb​_se0​_ooutlogic
    usb​_oe​_ooutlogic

    Instantiations

    Block Diagram

    Module usbdev​_linkstate

    This design unit is implemented in usbdev​_linkstate.sv

    This file depends on: prim_filter.sv

    Parameters

    NameTypeDefault ValueDescription
    SUSPEND​_TIMEOUT[11:0] logic12'd3000

    3ms by spec

    RESET​_TIMEOUT[2:0] logic3'd3

    3us. Can be 2.5us - 10ms by spec

    Ports

    NameDirectionTypeDescription
    clk​_48mhz​_iinlogic
    rst​_niinlogic
    us​_tick​_iinlogic
    usb​_sense​_iinlogic
    usb​_dp​_iinlogic
    usb​_dn​_iinlogic
    usb​_oe​_iinlogic
    rx​_jjj​_det​_iinlogic
    sof​_valid​_iinlogic
    link​_disconnect​_ooutlogic

    level

    link​_connect​_ooutlogic

    level

    link​_reset​_ooutlogic

    level

    link​_active​_ooutlogic

    level

    link​_suspend​_ooutlogic

    level

    link​_resume​_ooutlogic

    pulse

    host​_lost​_ooutlogic

    level

    link​_state​_oout[2:0] logic

    Instantiations

    Block Diagram

    State Machines

    Module aes​_cipher​_control

    This design unit is implemented in aes​_cipher​_control.sv

    This file depends on: prim_flop.sv, uvm_pkg.sv, aes_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Maskingbit0
    SBoxImplsbox_impl_eSBoxImplLut
    StateWidthint6

    Types $ ./sparse-fsm-encode.py -d 3 -m 7 -n 6
    -s 31468618 --language=sv

    Hamming distance histogram:

    0: -- 1: -- 2: -- 3: |||||||||||||||||||| (57.14%) 4: ||||||||||||||| (42.86%) 5: -- 6: --

    Minimum Hamming distance: 3 Maximum Hamming distance: 4

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    in​_valid​_iinlogic

    Input handshake signals

    in​_ready​_ooutlogic
    out​_valid​_ooutlogic

    Output handshake signals

    out​_ready​_iinlogic
    cfg​_valid​_iinlogic

    Control and sync signals

    op​_iinciph_op_e
    key​_len​_iinkey_len_e
    crypt​_iinlogic
    crypt​_ooutlogic
    dec​_key​_gen​_iinlogic
    dec​_key​_gen​_ooutlogic
    key​_clear​_iinlogic
    key​_clear​_ooutlogic
    data​_out​_clear​_iinlogic
    data​_out​_clear​_ooutlogic
    mux​_sel​_err​_iinlogic
    alert​_ooutlogic
    prng​_update​_ooutlogic

    Control signals for masking PRNG

    prng​_reseed​_req​_ooutlogic
    prng​_reseed​_ack​_iinlogic
    state​_sel​_ooutstate_sel_e

    Control and sync signals for cipher data path

    state​_we​_ooutlogic
    sub​_bytes​_en​_ooutlogic
    sub​_bytes​_out​_req​_iinlogic
    sub​_bytes​_out​_ack​_ooutlogic
    add​_rk​_sel​_ooutadd_rk_sel_e
    key​_expand​_op​_ooutciph_op_e

    Control and sync signals for key expand data path

    key​_full​_sel​_ooutkey_full_sel_e
    key​_full​_we​_ooutlogic
    key​_dec​_sel​_ooutkey_dec_sel_e
    key​_dec​_we​_ooutlogic
    key​_expand​_en​_ooutlogic
    key​_expand​_out​_req​_iinlogic
    key​_expand​_out​_ack​_ooutlogic
    key​_expand​_clear​_ooutlogic
    key​_expand​_round​_oout[3:0] logic
    key​_words​_sel​_ooutkey_words_sel_e
    round​_key​_sel​_ooutround_key_sel_e

    Instantiations

    Block Diagram

    State Machines

    Module aes​_key​_expand

    This design unit is implemented in aes​_key​_expand.sv

    This file depends on: uvm_pkg.sv, aes_sbox.sv, aes_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    AES192Enablebit1
    Maskingbit0
    SBoxImplsbox_impl_eSBoxImplLut
    NumSharesintMasking ? 2 : 1

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    cfg​_valid​_iinlogic
    op​_iinciph_op_e
    en​_iinlogic
    out​_req​_ooutlogic
    out​_ack​_iinlogic
    clear​_iinlogic
    round​_iin[3:0] logic
    key​_len​_iinkey_len_e
    key​_iin[31:0] [7:0] logic [NumShares]
    key​_oout[31:0] [7:0] logic [NumShares]
    prd​_iin[WidthPRDKey-1:0] logic

    Block Diagram

    Module aes​_mix​_columns

    This design unit is implemented in aes​_mix​_columns.sv

    This file depends on: aes_pkg.sv, aes_mix_single_column.sv

    Ports

    NameDirectionTypeDescription
    op​_iinciph_op_e
    data​_iin[7:0] [3:0] [3:0] logic
    data​_oout[7:0] [3:0] [3:0] logic

    Block Diagram

    Module aes​_prng​_masking

    This design unit is implemented in aes​_prng​_masking.sv

    This file depends on: uvm_pkg.sv, prim_lfsr.sv, prim_cipher_pkg.sv, aes_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    WidthintWidthPRDMasking

    Must be divisble by ChunkSize and 8.

    ChunkSizeintChunkSizePRDMasking

    width of the LFSR primitives

    NumChunksintWidth/ChunkSize

    derived parameter

    SecAllowForcingMasksbit0

    Allow forcing masks to 0 using force_zero_masks_i. Useful for SCA only.

    RndCnstLfsrSeedmasking_lfsr_seed_tRndCnstMaskingLfsrSeedDefault
    RndCnstChunkLfsrPermmskg_chunk_lfsr_perm_tRndCnstMskgChunkLfsrPermDefault
    NumBytesintWidth/8

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    force​_zero​_masks​_iinlogic
    data​_update​_iinlogic

    Connections to AES internals, PRNG consumers

    data​_oout[Width-1:0] logic
    reseed​_req​_iinlogic
    reseed​_ack​_ooutlogic
    entropy​_req​_ooutlogic

    Connections to outer world, LFSR reseeding

    entropy​_ack​_iinlogic
    entropy​_iin[Width-1:0] logic

    Block Diagram

    Module aes​_reg​_status

    This design unit is implemented in aes​_reg​_status.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    we​_iin[Width-1:0] logic
    use​_iinlogic
    clear​_iinlogic
    arm​_iinlogic
    new​_ooutlogic
    clean​_ooutlogic

    Block Diagram

    Module aes​_shift​_rows

    This design unit is implemented in aes​_shift​_rows.sv

    This file depends on: aes_pkg.sv

    Ports

    NameDirectionTypeDescription
    op​_iinciph_op_e
    data​_iin[7:0] [3:0] [3:0] logic
    data​_oout[7:0] [3:0] [3:0] logic

    Block Diagram

    Module aes​_sub​_bytes

    This design unit is implemented in aes​_sub​_bytes.sv

    This file depends on: aes_sbox.sv, aes_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    SBoxImplsbox_impl_eSBoxImplLut

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    en​_iinlogic
    out​_req​_ooutlogic
    out​_ack​_iinlogic
    op​_iinciph_op_e
    data​_iin[7:0] [3:0] [3:0] logic
    mask​_iin[7:0] [3:0] [3:0] logic
    prd​_iin[WidthPRDSBox-1:0] [3:0] [3:0] logic
    data​_oout[7:0] [3:0] [3:0] logic
    mask​_oout[7:0] [3:0] [3:0] logic

    Block Diagram

    Module BUFG

    This design unit is implemented in BUFG.v

    Ports

    NameDirectionTypeDescription
    Ooutlogic
    Iinlogic

    Block Diagram

    Module BUFGCE

    This design unit is implemented in BUFGCE.v

    Ports

    NameDirectionTypeDescription
    Ooutlogic
    CEinlogic
    Iinlogic

    Block Diagram

    Module BUFGMUX

    This design unit is implemented in BUFGMUX.v

    Parameters

    NameTypeDefault ValueDescription
    CLK​_SEL​_TYPEunknown"SYNC"

    Ports

    NameDirectionTypeDescription
    Ooutlogic
    I0inlogic
    I1inlogic
    Sinlogic

    Block Diagram

    Module flash​_phy​_rd​_buffers

    This design unit is implemented in flash​_phy​_rd​_buffers.sv

    This file depends on: flash_phy_pkg.sv, flash_ctrl_pkg.sv

    Description

    flash_phy_rd_buffers

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    en​_iinlogic
    alloc​_iinlogic
    update​_iinlogic
    wipe​_iinlogic
    addr​_iin[BankAddrW-1:0] logic
    part​_iinlogic
    info​_sel​_iin[InfoTypesWidth-1:0] logic
    data​_iin[DataWidth-1:0] logic
    out​_ooutrd_buf_t

    Block Diagram

    Module ibex​_alu

    This design unit is implemented in ibex​_alu.sv

    This file depends on: ibex_pkg.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    RV32Brv32b_eibex_pkg::RV32BNone

    Ports

    NameDirectionTypeDescription
    operator​_iinalu_op_e
    operand​_a​_iin[31:0] logic
    operand​_b​_iin[31:0] logic
    instr​_first​_cycle​_iinlogic
    multdiv​_operand​_a​_iin[32:0] logic
    multdiv​_operand​_b​_iin[32:0] logic
    multdiv​_sel​_iinlogic
    imd​_val​_q​_iin[31:0] logic [2]
    imd​_val​_d​_oout[31:0] logic [2]
    imd​_val​_we​_oout[1:0] logic
    adder​_result​_oout[31:0] logic
    adder​_result​_ext​_oout[33:0] logic
    result​_oout[31:0] logic
    comparison​_result​_ooutlogic
    is​_equal​_result​_ooutlogic

    Block Diagram

    Module ibex​_branch​_predict

    This design unit is implemented in ibex​_branch​_predict.sv

    This file depends on: uvm_pkg.sv, ibex_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    fetch​_rdata​_iin[31:0] logic

    Instruction from fetch stage

    fetch​_pc​_iin[31:0] logic
    fetch​_valid​_iinlogic
    predict​_branch​_taken​_ooutlogic

    Prediction for supplied instruction

    predict​_branch​_pc​_oout[31:0] logic

    Block Diagram

    Module ibex​_compressed​_decoder

    This design unit is implemented in ibex​_compressed​_decoder.sv

    This file depends on: uvm_pkg.sv, ibex_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    valid​_iinlogic
    instr​_iin[31:0] logic
    instr​_oout[31:0] logic
    is​_compressed​_ooutlogic
    illegal​_instr​_ooutlogic

    Block Diagram

    Module ibex​_controller

    This design unit is implemented in ibex​_controller.sv

    This file depends on: uvm_pkg.sv, ibex_pkg.sv, ibex_id_stage.sv, ibex_core.sv

    Parameters

    NameTypeDefault ValueDescription
    WritebackStagebit0
    BranchPredictorbit0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    ctrl​_busy​_ooutlogic

    core is busy processing instrs

    illegal​_insn​_iinlogic

    decoder has an invalid instr

    ecall​_insn​_iinlogic

    decoder has ECALL instr

    mret​_insn​_iinlogic

    decoder has MRET instr

    dret​_insn​_iinlogic

    decoder has DRET instr

    wfi​_insn​_iinlogic

    decoder has WFI instr

    ebrk​_insn​_iinlogic

    decoder has EBREAK instr

    csr​_pipe​_flush​_iinlogic

    do CSR-related pipeline flush

    instr​_valid​_iinlogic

    instr is valid

    instr​_iin[31:0] logic

    uncompressed instr data for mtval

    instr​_compressed​_iin[15:0] logic

    instr compressed data for mtval

    instr​_is​_compressed​_iinlogic

    instr is compressed

    instr​_bp​_taken​_iinlogic

    instr was predicted taken branch

    instr​_fetch​_err​_iinlogic

    instr has error

    instr​_fetch​_err​_plus2​_iinlogic

    instr error is x32

    pc​_id​_iin[31:0] logic

    instr address

    instr​_valid​_clear​_ooutlogic

    kill instr in IF-ID reg

    id​_in​_ready​_ooutlogic

    ID stage is ready for new instr

    controller​_run​_ooutlogic

    Controller is in standard instruction run mode

    instr​_req​_ooutlogic

    start fetching instructions

    pc​_set​_ooutlogic

    jump to address set by pc_mux

    pc​_set​_spec​_ooutlogic

    speculative branch

    pc​_mux​_ooutpc_sel_e

    IF stage fetch address selector (boot, normal, exception...)

    nt​_branch​_mispredict​_ooutlogic

    Not-taken branch in ID/EX was mispredicted (predicted taken)

    exc​_pc​_mux​_ooutexc_pc_sel_e

    IF stage selector for exception PC

    exc​_cause​_ooutexc_cause_e

    for IF stage, CSRs

    lsu​_addr​_last​_iin[31:0] logic

    for mtval

    load​_err​_iinlogic
    store​_err​_iinlogic
    wb​_exception​_ooutlogic

    Instruction in WB taking an exception

    branch​_set​_iinlogic

    branch set signal (branch definitely taken)

    branch​_set​_spec​_iinlogic

    speculative branch signal (branch may be taken)

    branch​_not​_set​_iinlogic

    branch is definitely not taken

    jump​_set​_iinlogic

    jump taken set signal

    csr​_mstatus​_mie​_iinlogic

    M-mode interrupt enable bit

    irq​_pending​_iinlogic

    interrupt request pending

    irqs​_iinirqs_t

    interrupt requests qualified with mie CSR

    irq​_nm​_iinlogic

    non-maskeable interrupt

    nmi​_mode​_ooutlogic

    core executing NMI handler

    debug​_req​_iinlogic

    debug signals

    debug​_cause​_ooutdbg_cause_e
    debug​_csr​_save​_ooutlogic
    debug​_mode​_ooutlogic
    debug​_single​_step​_iinlogic
    debug​_ebreakm​_iinlogic
    debug​_ebreaku​_iinlogic
    trigger​_match​_iinlogic
    csr​_save​_if​_ooutlogic
    csr​_save​_id​_ooutlogic
    csr​_save​_wb​_ooutlogic
    csr​_restore​_mret​_id​_ooutlogic
    csr​_restore​_dret​_id​_ooutlogic
    csr​_save​_cause​_ooutlogic
    csr​_mtval​_oout[31:0] logic
    priv​_mode​_iinpriv_lvl_e
    csr​_mstatus​_tw​_iinlogic
    stall​_id​_iinlogic

    stall & flush signals

    stall​_wb​_iinlogic
    flush​_id​_ooutlogic
    ready​_wb​_iinlogic
    perf​_jump​_ooutlogic

    we are executing a jump instruction (j, jr, jal, jalr)

    perf​_tbranch​_ooutlogic

    we are executing a taken branch instruction

    Block Diagram

    State Machines

    Module ibex​_counter

    This design unit is implemented in ibex​_counter.sv

    Parameters

    NameTypeDefault ValueDescription
    CounterWidthint32

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    counter​_inc​_iinlogic
    counterh​_we​_iinlogic
    counter​_we​_iinlogic
    counter​_val​_iin[31:0] logic
    counter​_val​_oout[63:0] logic

    Block Diagram

    Module ibex​_csr

    This design unit is implemented in ibex​_csr.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint32
    ShadowCopybit1'b0
    ResetValue[Width-1:0] bit'0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wr​_data​_iin[Width-1:0] logic
    wr​_en​_iinlogic
    rd​_data​_oout[Width-1:0] logic
    rd​_error​_ooutlogic

    Block Diagram

    Module ibex​_decoder

    This design unit is implemented in ibex​_decoder.sv

    This file depends on: uvm_pkg.sv, ibex_pkg.sv

    Description

    controller

    Parameters

    NameTypeDefault ValueDescription
    RV32Ebit0
    RV32Mrv32m_eibex_pkg::RV32MFast
    RV32Brv32b_eibex_pkg::RV32BNone
    BranchTargetALUbit0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    illegal​_insn​_ooutlogic

    illegal instr encountered

    ebrk​_insn​_ooutlogic

    trap instr encountered

    mret​_insn​_ooutlogic

    return from exception instr encountered

    dret​_insn​_ooutlogic

    return from debug instr encountered

    ecall​_insn​_ooutlogic

    syscall instr encountered

    wfi​_insn​_ooutlogic

    wait for interrupt instr encountered

    jump​_set​_ooutlogic

    jump taken set signal

    branch​_taken​_iinlogic

    registered branch decision

    icache​_inval​_ooutlogic
    instr​_first​_cycle​_iinlogic

    instruction read is in its first cycle

    instr​_rdata​_iin[31:0] logic

    instruction read from memory/cache

    instr​_rdata​_alu​_iin[31:0] logic

    instruction read from memory/cache replicated to ease fan-out)

    illegal​_c​_insn​_iinlogic

    compressed instruction decode failed

    imm​_a​_mux​_sel​_ooutimm_a_sel_e

    immediate selection for operand a

    imm​_b​_mux​_sel​_ooutimm_b_sel_e

    immediate selection for operand b

    bt​_a​_mux​_sel​_ooutop_a_sel_e

    branch target selection operand a

    bt​_b​_mux​_sel​_ooutimm_b_sel_e

    branch target selection operand b

    imm​_i​_type​_oout[31:0] logic
    imm​_s​_type​_oout[31:0] logic
    imm​_b​_type​_oout[31:0] logic
    imm​_u​_type​_oout[31:0] logic
    imm​_j​_type​_oout[31:0] logic
    zimm​_rs1​_type​_oout[31:0] logic
    rf​_wdata​_sel​_ooutrf_wd_sel_e

    RF write data selection

    rf​_we​_ooutlogic

    write enable for regfile

    rf​_raddr​_a​_oout[4:0] logic
    rf​_raddr​_b​_oout[4:0] logic
    rf​_waddr​_oout[4:0] logic
    rf​_ren​_a​_ooutlogic

    Instruction reads from RF addr A

    rf​_ren​_b​_ooutlogic

    Instruction reads from RF addr B

    alu​_operator​_ooutalu_op_e

    ALU operation selection

    alu​_op​_a​_mux​_sel​_ooutop_a_sel_e

    operand a selection: reg value, PC, immediate or zero

    alu​_op​_b​_mux​_sel​_ooutop_b_sel_e

    operand b selection: reg value or immediate

    alu​_multicycle​_ooutlogic

    ternary bitmanip instruction

    mult​_en​_ooutlogic

    perform integer multiplication

    div​_en​_ooutlogic

    perform integer division or remainder

    mult​_sel​_ooutlogic

    as above but static, for data muxes

    div​_sel​_ooutlogic

    as above but static, for data muxes

    multdiv​_operator​_ooutmd_op_e
    multdiv​_signed​_mode​_oout[1:0] logic
    csr​_access​_ooutlogic

    access to CSR

    csr​_op​_ooutcsr_op_e

    operation to perform on CSR

    data​_req​_ooutlogic

    start transaction to data memory

    data​_we​_ooutlogic

    write enable

    data​_type​_oout[1:0] logic

    size of transaction: byte, half word or word

    data​_sign​_extension​_ooutlogic

    sign extension for data read from memory

    jump​_in​_dec​_ooutlogic

    jump is being calculated in ALU

    branch​_in​_dec​_ooutlogic

    Block Diagram

    Module ibex​_dummy​_instr

    This design unit is implemented in ibex​_dummy​_instr.sv

    This file depends on: prim_lfsr.sv

    Parameters

    NameTypeDefault ValueDescription
    TIMEOUT​_CNT​_Wint5
    OP​_Wint5
    LFSR​_OUT​_Wint$bits(lfsr_data_t)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock and reset

    rst​_niinlogic
    dummy​_instr​_en​_iinlogic

    Interface to CSRs

    dummy​_instr​_mask​_iin[2:0] logic
    dummy​_instr​_seed​_en​_iinlogic
    dummy​_instr​_seed​_iin[31:0] logic
    fetch​_valid​_iinlogic

    Interface to IF stage

    id​_in​_ready​_iinlogic
    insert​_dummy​_instr​_ooutlogic
    dummy​_instr​_data​_oout[31:0] logic

    Instantiations

    Block Diagram

    Module ibex​_icache

    This design unit is implemented in ibex​_icache.sv

    This file depends on: prim_secded_28_22_enc.sv, prim_secded_72_64_dec.sv, uvm_pkg.sv, prim_secded_28_22_dec.sv, prim_secded_72_64_enc.sv, prim_ram_1p.sv

    Parameters

    NameTypeDefault ValueDescription
    BusWidthint32

    Cache arrangement parameters

    CacheSizeBytesint4*1024
    ICacheECCbit1'b0
    LineSizeint64
    NumWaysint2
    SpecRequestbit1'b0

    Always make speculative bus requests in parallel with lookups

    BranchCachebit1'b0

    Only cache branch targets

    ADDR​_Wint32

    Local constants

    NUM​_FBint4

    Number of fill buffers (must be >= 2)

    FB​_THRESHOLDintNUM_FB - 2

    Request throttling threshold

    LINE​_SIZE​_ECCintICacheECC ? (LineSize + 8) : LineSize

    Derived parameters

    LINE​_SIZE​_BYTESintLineSize/8
    LINE​_Wint$clog2(LINE_SIZE_BYTES)
    BUS​_BYTESintBusWidth/8
    BUS​_Wint$clog2(BUS_BYTES)
    LINE​_BEATSintLINE_SIZE_BYTES / BUS_BYTES
    LINE​_BEATS​_Wint$clog2(LINE_BEATS)
    NUM​_LINESintCacheSizeBytes / NumWays / LINE_SIZE_BYTES
    INDEX​_Wint$clog2(NUM_LINES)
    INDEX​_HIintINDEX_W + LINE_W - 1
    TAG​_SIZEintADDR_W - INDEX_W - LINE_W + 1

    1 valid bit

    TAG​_SIZE​_ECCintICacheECC ? (TAG_SIZE + 6) : TAG_SIZE
    OUTPUT​_BEATSint(BUS_BYTES / 2)

    number of halfwords

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    Clock and reset

    rst​_niinlogic
    req​_iinlogic

    Signal that the core would like instructions

    branch​_iinlogic

    Set the cache's address counter

    branch​_spec​_iinlogic
    addr​_iin[31:0] logic
    ready​_iinlogic

    IF stage interface: Pass fetched instructions to the core

    valid​_ooutlogic
    rdata​_oout[31:0] logic
    addr​_oout[31:0] logic
    err​_ooutlogic
    err​_plus2​_ooutlogic
    instr​_req​_ooutlogic

    Instruction memory / interconnect interface: Fetch instruction data from memory

    instr​_gnt​_iinlogic
    instr​_addr​_oout[31:0] logic
    instr​_rdata​_iin[BusWidth-1:0] logic
    instr​_err​_iinlogic
    instr​_pmp​_err​_iinlogic
    instr​_rvalid​_iinlogic
    icache​_enable​_iinlogic

    Cache status

    icache​_inval​_iinlogic
    busy​_ooutlogic

    Block Diagram

    Module ibex​_multdiv​_fast

    This design unit is implemented in ibex​_multdiv​_fast.sv

    This file depends on: uvm_pkg.sv, ibex_pkg.sv

    Description

    ibex_mult

    Parameters

    NameTypeDefault ValueDescription
    RV32Mrv32m_eibex_pkg::RV32MFast

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    mult​_en​_iinlogic

    dynamic enable signal, for FSM control

    div​_en​_iinlogic

    dynamic enable signal, for FSM control

    mult​_sel​_iinlogic

    static decoder output, for data muxes

    div​_sel​_iinlogic

    static decoder output, for data muxes

    operator​_iinmd_op_e
    signed​_mode​_iin[1:0] logic
    op​_a​_iin[31:0] logic
    op​_b​_iin[31:0] logic
    alu​_adder​_ext​_iin[33:0] logic
    alu​_adder​_iin[31:0] logic
    equal​_to​_zero​_iinlogic
    data​_ind​_timing​_iinlogic
    alu​_operand​_a​_oout[32:0] logic
    alu​_operand​_b​_oout[32:0] logic
    imd​_val​_q​_iin[33:0] logic [2]
    imd​_val​_d​_oout[33:0] logic [2]
    imd​_val​_we​_oout[1:0] logic
    multdiv​_ready​_id​_iinlogic
    multdiv​_result​_oout[31:0] logic
    valid​_ooutlogic

    Block Diagram

    State Machines

    Module ibex​_multdiv​_slow

    This design unit is implemented in ibex​_multdiv​_slow.sv

    This file depends on: uvm_pkg.sv, ibex_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    mult​_en​_iinlogic

    dynamic enable signal, for FSM control

    div​_en​_iinlogic

    dynamic enable signal, for FSM control

    mult​_sel​_iinlogic

    static decoder output, for data muxes

    div​_sel​_iinlogic

    static decoder output, for data muxes

    operator​_iinmd_op_e
    signed​_mode​_iin[1:0] logic
    op​_a​_iin[31:0] logic
    op​_b​_iin[31:0] logic
    alu​_adder​_ext​_iin[33:0] logic
    alu​_adder​_iin[31:0] logic
    equal​_to​_zero​_iinlogic
    data​_ind​_timing​_iinlogic
    alu​_operand​_a​_oout[32:0] logic
    alu​_operand​_b​_oout[32:0] logic
    imd​_val​_q​_iin[33:0] logic [2]
    imd​_val​_d​_oout[33:0] logic [2]
    imd​_val​_we​_oout[1:0] logic
    multdiv​_ready​_id​_iinlogic
    multdiv​_result​_oout[31:0] logic
    valid​_ooutlogic

    Block Diagram

    State Machines

    Module ibex​_prefetch​_buffer

    This design unit is implemented in ibex​_prefetch​_buffer.sv

    This file depends on: ibex_fetch_fifo.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    BranchPredictorbit1'b0
    NUM​_REQSint2

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_iinlogic
    branch​_iinlogic
    branch​_spec​_iinlogic
    predicted​_branch​_iinlogic
    branch​_mispredict​_iinlogic
    addr​_iin[31:0] logic
    ready​_iinlogic
    valid​_ooutlogic
    rdata​_oout[31:0] logic
    addr​_oout[31:0] logic
    err​_ooutlogic
    err​_plus2​_ooutlogic
    instr​_req​_ooutlogic

    goes to instruction memory / instruction cache

    instr​_gnt​_iinlogic
    instr​_addr​_oout[31:0] logic
    instr​_rdata​_iin[31:0] logic
    instr​_err​_iinlogic
    instr​_pmp​_err​_iinlogic
    instr​_rvalid​_iinlogic
    busy​_ooutlogic

    Prefetch Buffer Status

    Instantiations

    Block Diagram

    Module keccak​_2share

    This design unit is implemented in keccak​_2share.sv

    This file depends on: prim_dom_and_2share.sv, uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint1600

    b= {25, 50, 100, 200, 400, 800, 1600}

    WintWidth/25

    Derived

    Lint$clog2(W)
    MaxRoundint12 + 2*L

    Keccak-f only

    RndWint$clog2(MaxRound+1)

    Representing up to MaxRound

    EnMaskingbit0

    Enable secure hardening

    ShareintEnMasking ? 2 : 1
    RhoOffsetint [25]'{ 0, 36, 3, 105, 210, 1, 300, 10, 45, 66, 190, 6, 171, 15, 253, 28, 55, 153, 21, 120, 91, 276, 231, 136, 78 }

    Rho ====================================================================== As RhoOffsetx is considered as variable int in VCS, it is replaced with generate statement. Revised to meet verilator lint. Now RhoOffset is 1-D array

    ThetaIndexX1int [5]'{4, 0, 1, 2, 3}

    (x-1)%5

    ThetaIndexX2int [5]'{1, 2, 3, 4, 0}

    (x+1)%5

    PiRotateint [5] [5]'{ '{ 0, 3, 1, 4, 2}, '{ 1, 4, 2, 0, 3}, '{ 2, 0, 3, 1, 4}, '{ 3, 1, 4, 2, 0}, '{ 4, 2, 0, 3, 1} }

    pi rearrange the position of lanes pix,y,z = state(x+3y),x,z

    ChiIndexX1int [5]'{1, 2, 3, 4, 0}

    (x+1)%5

    ChiIndexX2int [5]'{2, 3, 4, 0, 1}

    (x+2)%5

    RC[63:0] logic [24]'{ 64'h 0000_0000_0000_0001, 64'h 0000_0000_0000_8082, 64'h 8000_0000_0000_808A, 64'h 8000_0000_8000_8000, 64'h 0000_0000_0000_808B, 64'h 0000_0000_8000_0001, 64'h 8000_0000_8000_8081, 64'h 8000_0000_0000_8009, 64'h 0000_0000_0000_008A, 64'h 0000_0000_0000_0088, 64'h 0000_0000_8000_8009, 64'h 0000_0000_8000_000A, 64'h 0000_0000_8000_808B, 64'h 8000_0000_0000_008B, 64'h 8000_0000_0000_8089, 64'h 8000_0000_0000_8003, 64'h 8000_0000_0000_8002, 64'h 8000_0000_0000_0080, 64'h 0000_0000_0000_800A, 64'h 8000_0000_8000_000A, 64'h 8000_0000_8000_8081, 64'h 8000_0000_0000_8080, 64'h 0000_0000_8000_0001, 64'h 8000_0000_8000_8008 }

    RC parameter: Precomputed by util/keccak_rc.py. Only up-to 0..L-1 is used RC = '0 RC[2**j-1] = rc(j+7*rnd) rc(t) =

    1. t%255 == 0 -> 1

    2. R0:7 = 'b10000000

    3. for i = 1..t%255 a. R = 0 || R b. R0 = R0 ^ R8 c. R4 = R4 ^ R8 d. R5 = R5 ^ R8 e. R6 = R6 ^ R8 f. R = R0:7

    4. return R0 RC has L = 0..6 for lower L case, only chopping lower part of 64bit RC is sufficient.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    rnd​_iin[RndW-1:0] logic

    Current Round

    rand​_valid​_iinlogic
    rand​_iin[Width-1:0] logic

    Random values. Used when 2Share enabled

    sel​_iinlogic

    Select input/output mux. Used when EnMasking := 1

    s​_iin[Width-1:0] logic [Share]
    s​_oout[Width-1:0] logic [Share]

    Block Diagram

    Module otbn​_loop​_controller

    This design unit is implemented in otbn​_loop​_controller.sv

    This file depends on: uvm_pkg.sv, otbn_stack.sv, otbn_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    ImemAddrWidthint12
    LoopStackDepthint7

    The loop controller has a current loop and then a stack of outer loops, this sets the size of the stack so maximum loop nesting depth is LoopStackDepth + 1.

    LoopEndAddrWidthintImemAddrWidth < 14 ? 14 : ImemAddrWidth

    ISA has a fixed 12 bits for loop_bodysize. When IMEM size is less than 16 kB (ImemAddrWidth < 14) some of these bits are ignored as a loop body cannot be greater than the IMEM size.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    insn​_valid​_iinlogic
    insn​_addr​_iin[ImemAddrWidth-1:0] logic
    next​_insn​_addr​_iin[ImemAddrWidth-1:0] logic
    loop​_start​_req​_iinlogic
    loop​_start​_commit​_iinlogic
    loop​_bodysize​_iin[11:0] logic
    loop​_iterations​_iin[31:0] logic
    loop​_jump​_ooutlogic
    loop​_jump​_addr​_oout[ImemAddrWidth-1:0] logic
    loop​_err​_ooutlogic
    branch​_taken​_iinlogic
    otbn​_stall​_iinlogic

    Instantiations

    Block Diagram

    Module otbn​_rf​_base​_ff

    This design unit is implemented in otbn​_rf​_base​_ff.sv

    This file depends on: otbn_pkg.sv

    Description

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wr​_addr​_iin[4:0] logic
    wr​_en​_iinlogic
    wr​_data​_iin[31:0] logic
    rd​_addr​_a​_iin[4:0] logic
    rd​_data​_a​_oout[31:0] logic
    rd​_addr​_b​_iin[4:0] logic
    rd​_data​_b​_oout[31:0] logic

    Block Diagram

    Module otbn​_rf​_base​_fpga

    This design unit is implemented in otbn​_rf​_base​_fpga.sv

    This file depends on: otbn_pkg.sv

    Description

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    wr​_addr​_iin[4:0] logic
    wr​_en​_iinlogic
    wr​_data​_iin[31:0] logic
    rd​_addr​_a​_iin[4:0] logic
    rd​_data​_a​_oout[31:0] logic
    rd​_addr​_b​_iin[4:0] logic
    rd​_data​_b​_oout[31:0] logic

    Block Diagram

    Module otbn​_stack

    This design unit is implemented in otbn​_stack.sv

    This file depends on: prim_util_pkg.sv, otbn_pkg.sv

    Description

    Parameters

    NameTypeDefault ValueDescription
    StackWidthint32
    StackDepthint4
    StackDepthWintprim_util_pkg::vbits(StackDepth)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    full​_ooutlogic

    Stack is full

    push​_iinlogic

    Push the data

    push​_data​_iin[StackWidth-1:0] logic

    Data to push

    pop​_iinlogic

    Pop top of the stack

    top​_data​_oout[StackWidth-1:0] logic

    Data on top of the stack

    top​_valid​_ooutlogic

    Stack is non empty (top_data_o is valid)

    Block Diagram

    Module prim​_generic​_buf

    This design unit is implemented in prim​_generic​_buf.sv

    Ports

    NameDirectionTypeDescription
    in​_iinlogic
    out​_ooutlogic

    Block Diagram

    Module prim​_generic​_flash​_bank

    This design unit is implemented in prim​_generic​_flash​_bank.sv

    This file depends on: flash_ctrl_pkg.sv, prim_fifo_sync.sv, prim_ram_1p.sv

    Description

    prim_generic_flash

    Parameters

    NameTypeDefault ValueDescription
    InfosPerBankint1

    info pages per bank

    InfoTypesint1

    different info types

    InfoTypesWidthint1

    different info types

    PagesPerBankint256

    data pages per bank

    WordsPerPageint256

    words per page

    DataWidthint32

    bits per word

    MetaDataWidthint12

    this is a temporary parameter to work around ECC issues

    PageWint$clog2(PagesPerBank)

    Derived parameters

    WordWint$clog2(WordsPerPage)
    AddrWintPageW + WordW
    ReadCyclesint1

    Emulated flash macro values

    ProgCyclesint50
    PgEraseCyclesint200
    BkEraseCyclesint2000
    InitCyclesint100
    WordsPerBankintPagesPerBank * WordsPerPage

    Locally derived values

    WordsPerInfoBankintInfosPerBank * WordsPerPage
    InfoAddrWint$clog2(WordsPerInfoBank)
    MemWidthintDataWidth - MetaDataWidth

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    rd​_iinlogic
    prog​_iinlogic
    prog​_last​_iinlogic
    prog​_type​_iinflash_prog_e

    the generic model does not make use of program types

    pg​_erase​_iinlogic
    bk​_erase​_iinlogic
    erase​_suspend​_req​_iinlogic
    he​_iinlogic
    addr​_iin[AddrW-1:0] logic
    part​_iinflash_part_e
    info​_sel​_iin[InfoTypesWidth-1:0] logic
    prog​_data​_iin[DataWidth-1:0] logic
    ack​_ooutlogic
    done​_ooutlogic
    rd​_data​_oout[DataWidth-1:0] logic
    init​_iinlogic
    init​_busy​_ooutlogic
    flash​_power​_ready​_h​_iinlogic
    flash​_power​_down​_h​_iinlogic

    Instantiations

    Block Diagram

    State Machines

    Module prim​_generic​_ram​_1p

    This design unit is implemented in prim​_generic​_ram​_1p.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint32

    bit

    Depthint128
    DataBitsPerMaskint1

    Number of data bits per bit of write mask

    MemInitFileunknown""

    VMEM file to initialize the memory with

    Awint$clog2(Depth)

    derived parameter

    MaskWidthintWidth / DataBitsPerMask

    Width of internal write mask. Note wmask_i input into the module is always assumed to be the full bit mask

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    req​_iinlogic
    write​_iinlogic
    addr​_iin[Aw-1:0] logic
    wdata​_iin[Width-1:0] logic
    wmask​_iin[Width-1:0] logic
    rdata​_oout[Width-1:0] logic

    Read data. Data is returned one cycle after req_i is high.

    Block Diagram

    Module prim​_generic​_ram​_2p

    This design unit is implemented in prim​_generic​_ram​_2p.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    Widthint32

    bit

    Depthint128
    DataBitsPerMaskint1

    Number of data bits per bit of write mask

    MemInitFileunknown""

    VMEM file to initialize the memory with

    Awint$clog2(Depth)

    derived parameter

    MaskWidthintWidth / DataBitsPerMask

    Width of internal write mask. Note *_wmask_i input into the module is always assumed to be the full bit mask.

    Ports

    NameDirectionTypeDescription
    clk​_a​_iinlogic
    clk​_b​_iinlogic
    a​_req​_iinlogic
    a​_write​_iinlogic
    a​_addr​_iin[Aw-1:0] logic
    a​_wdata​_iin[Width-1:0] logic
    a​_wmask​_iin[Width-1:0] logic
    a​_rdata​_oout[Width-1:0] logic
    b​_req​_iinlogic
    b​_write​_iinlogic
    b​_addr​_iin[Aw-1:0] logic
    b​_wdata​_iin[Width-1:0] logic
    b​_wmask​_iin[Width-1:0] logic
    b​_rdata​_oout[Width-1:0] logic

    Block Diagram

    Module prim​_gf​_mult

    This design unit is implemented in prim​_gf​_mult.sv

    This file depends on: uvm_pkg.sv

    Description

    prim_gf_mult

    Parameters

    NameTypeDefault ValueDescription
    Widthint32
    StagesPerCycleintWidth
    IPoly[Width-1:0] logic1'b1 << 15 | 1'b1 << 9 | 1'b1 << 7 | 1'b1 << 4 | 1'b1 << 3 | 1'b1 << 0

    The field-generating, irreducible polynomial of degree Width. Can for example be a Conway polynomial, see http://www.math.rwth-aachen.de/~Frank.Luebeck/data/ConwayPol/CP2.html For Width = 33, the Conway polynomial hast bits 32, 15, 9, 7, 4, 3, 0 set to one.

    LoopsintWidth / StagesPerCycle
    CntWidthint(Loops == 1) ? 1 : $clog2(Loops)

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    req​_iinlogic
    operand​_a​_iin[Width-1:0] logic
    operand​_b​_iin[Width-1:0] logic
    ack​_ooutlogic
    prod​_oout[Width-1:0] logic

    Block Diagram

    Module prim​_secded​_64​_57​_dec

    This design unit is implemented in prim​_secded​_64​_57​_dec.sv

    Ports

    NameDirectionTypeDescription
    inin[63:0] logic
    d​_oout[56:0] logic
    syndrome​_oout[6:0] logic
    err​_oout[1:0] logic

    Block Diagram

    Module prim​_secded​_72​_64​_dec

    This design unit is implemented in prim​_secded​_72​_64​_dec.sv

    Ports

    NameDirectionTypeDescription
    inin[71:0] logic
    d​_oout[63:0] logic
    syndrome​_oout[7:0] logic
    err​_oout[1:0] logic

    Block Diagram

    Module prim​_secded​_72​_64​_enc

    This design unit is implemented in prim​_secded​_72​_64​_enc.sv

    Ports

    NameDirectionTypeDescription
    inin[63:0] logic
    outout[71:0] logic

    Block Diagram

    Module prim​_secded​_hamming​_72​_64​_dec

    This design unit is implemented in prim​_secded​_hamming​_72​_64​_dec.sv

    Ports

    NameDirectionTypeDescription
    inin[71:0] logic
    d​_oout[63:0] logic
    syndrome​_oout[7:0] logic
    err​_oout[1:0] logic

    Block Diagram

    Module prim​_secded​_hamming​_72​_64​_enc

    This design unit is implemented in prim​_secded​_hamming​_72​_64​_enc.sv

    Ports

    NameDirectionTypeDescription
    inin[63:0] logic
    outout[71:0] logic

    Block Diagram

    Module prim​_xilinx​_buf

    This design unit is implemented in prim​_xilinx​_buf.sv

    Ports

    NameDirectionTypeDescription
    in​_iinlogic
    out​_ooutlogic

    Block Diagram

    Package usb​_consts​_pkg

    This design unit is implemented in usb​_consts​_pkg.sv

    Module usb​_fs​_nb​_in​_pe

    This design unit is implemented in usb​_fs​_nb​_in​_pe.sv

    This file depends on: usb_consts_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    NumInEps[4:0] logic12
    MaxInPktSizeByteint32
    InEpWint$clog2(NumInEps)

    derived parameter

    PktWint$clog2(MaxInPktSizeByte)

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_48mhz​_iinlogic
    rst​_niinlogic
    link​_reset​_iinlogic
    dev​_addr​_iin[6:0] logic
    in​_ep​_current​_oout[3:0] logic

    Other signals addressed to this ep

    in​_ep​_rollback​_ooutlogic

    Bad termination, rollback transaction

    in​_ep​_xfr​_end​_ooutlogic

    good termination, transaction complete

    in​_ep​_get​_addr​_oout[PktW - 1:0] logic

    Offset requested (0..pktlen)

    in​_ep​_data​_get​_ooutlogic

    Accept data (get_addr advances too)

    in​_ep​_newpkt​_ooutlogic

    New IN packet starting (updates in_ep_current_o)

    in​_ep​_stall​_iin[NumInEps-1:0] logic

    Endpoint in a stall state

    in​_ep​_has​_data​_iin[NumInEps-1:0] logic

    Endpoint has data to supply

    in​_ep​_data​_iin[7:0] logic

    Data for current get_addr

    in​_ep​_data​_done​_iin[NumInEps-1:0] logic

    Set when out of data

    in​_ep​_iso​_iin[NumInEps-1:0] logic

    Configure endpoint in isochronous mode

    data​_toggle​_clear​_iin[NumInEps-1:0] logic

    Clear the data toggles for an EP

    rx​_pkt​_start​_iinlogic

    Strobed on reception of packet.

    rx​_pkt​_end​_iinlogic
    rx​_pkt​_valid​_iinlogic
    rx​_pid​_iin[3:0] logic

    Most recent packet received.

    rx​_addr​_iin[6:0] logic
    rx​_endp​_iin[3:0] logic
    tx​_pkt​_start​_ooutlogic

    Strobe to send new packet.

    tx​_pkt​_end​_iinlogic
    tx​_pid​_oout[3:0] logic

    Packet type to send

    tx​_data​_avail​_ooutlogic

    Data payload to send if any

    tx​_data​_get​_iinlogic
    tx​_data​_oout[7:0] logic

    Block Diagram

    State Machines

    Module usb​_fs​_nb​_out​_pe

    This design unit is implemented in usb​_fs​_nb​_out​_pe.sv

    This file depends on: usb_consts_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    NumOutEps[4:0] logic2
    MaxOutPktSizeByteint32
    OutEpWint$clog2(NumOutEps)

    derived parameter

    PktWint$clog2(MaxOutPktSizeByte)

    derived parameter

    Ports

    NameDirectionTypeDescription
    clk​_48mhz​_iinlogic
    rst​_niinlogic
    link​_reset​_iinlogic
    dev​_addr​_iin[6:0] logic
    out​_ep​_current​_oout[3:0] logic

    Other signals address to this ep, stable for several cycles

    out​_ep​_data​_put​_ooutlogic

    put the data (put addr advances after)

    out​_ep​_put​_addr​_oout[PktW - 1:0] logic

    Offset to put data (0..pktlen)

    out​_ep​_data​_oout[7:0] logic
    out​_ep​_newpkt​_ooutlogic

    new packed, current was set

    out​_ep​_acked​_ooutlogic

    good termination, device has acked

    out​_ep​_rollback​_ooutlogic

    bad termination, discard data

    out​_ep​_setup​_oout[NumOutEps-1:0] logic
    out​_ep​_full​_iin[NumOutEps-1:0] logic

    Cannot accept data

    out​_ep​_stall​_iin[NumOutEps-1:0] logic

    Stalled

    out​_ep​_iso​_iin[NumOutEps-1:0] logic

    Configure endpoint in isochronous mode

    data​_toggle​_clear​_iin[NumOutEps-1:0] logic

    Clear the data toggles for an EP

    rx​_pkt​_start​_iinlogic

    Strobed on reception of packet.

    rx​_pkt​_end​_iinlogic
    rx​_pkt​_valid​_iinlogic
    rx​_pid​_iin[3:0] logic

    Most recent packet received.

    rx​_addr​_iin[6:0] logic
    rx​_endp​_iin[3:0] logic
    rx​_data​_put​_iinlogic

    rx_data is pushed into endpoint controller.

    rx​_data​_iin[7:0] logic
    tx​_pkt​_start​_ooutlogic

    Strobe to send new packet.

    tx​_pkt​_end​_iinlogic
    tx​_pid​_oout[3:0] logic

    Block Diagram

    State Machines

    Module usb​_fs​_rx

    This design unit is implemented in usb​_fs​_rx.sv

    Description

    usb_fs_rx

    Parameters

    NameTypeDefault ValueDescription
    DT[2:0] logic3'b100

    transition state

    DJ[2:0] logic3'b010

    J - idle line state

    DK[2:0] logic3'b001

    K - inverse of J

    SE0[2:0] logic3'b000

    single-ended 0 - end of packet or detached

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    A 48MHz clock is required to recover the clock from the incoming data.

    rst​_niinlogic
    link​_reset​_iinlogic
    cfg​_eop​_single​_bit​_iinlogic

    configuration

    cfg​_rx​_differential​_iinlogic
    usb​_d​_iinlogic

    USB data+ and data- lines (synchronous)

    usb​_dp​_iinlogic
    usb​_dn​_iinlogic
    tx​_en​_iinlogic

    Transmit enable disables the receier

    bit​_strobe​_ooutlogic

    pulse on every bit transition.

    pkt​_start​_ooutlogic

    Pulse on beginning of new packet.

    pkt​_end​_ooutlogic

    Pulse on end of current packet.

    pid​_oout[3:0] logic

    Most recent packet decoded.

    addr​_oout[6:0] logic
    endp​_oout[3:0] logic
    frame​_num​_oout[10:0] logic
    rx​_data​_put​_ooutlogic

    Pulse on valid data on rx_data.

    rx​_data​_oout[7:0] logic
    valid​_packet​_ooutlogic

    Most recent packet passes PID and CRC checks

    rx​_jjj​_det​_ooutlogic

    line status for the status detection (actual rx bits after clock recovery)

    crc​_error​_ooutlogic

    Error detection

    pid​_error​_ooutlogic
    bitstuff​_error​_ooutlogic

    Block Diagram

    Module usb​_fs​_tx

    This design unit is implemented in usb​_fs​_tx.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic

    A 48MHz clock is required to receive USB data at 12MHz it's simpler to juse use 48MHz everywhere

    rst​_niinlogic

    asyc reset

    link​_reset​_iinlogic

    USB reset, sync to 48 MHz, active high

    tx​_osc​_test​_mode​_iinlogic

    Oscillator test mode (constantly output JK)

    bit​_strobe​_iinlogic

    bit strobe from rx to align with senders clock

    usb​_oe​_ooutlogic

    output enable to take ownership of bus and data out

    usb​_d​_ooutlogic
    usb​_se0​_ooutlogic
    pkt​_start​_iinlogic

    pulse to initiate new packet transmission

    pkt​_end​_ooutlogic
    pid​_iin[3:0] logic

    pid_i to send

    tx​_data​_avail​_iinlogic

    tx logic pulls data until there is nothing available

    tx​_data​_get​_ooutlogic
    tx​_data​_iin[7:0] logic

    Block Diagram

    State Machines

    Module usb​_fs​_tx​_mux

    This design unit is implemented in usb​_fs​_tx​_mux.sv

    Ports

    NameDirectionTypeDescription
    in​_tx​_pkt​_start​_iinlogic

    interface to IN Protocol Engine

    in​_tx​_pid​_iin[3:0] logic
    out​_tx​_pkt​_start​_iinlogic

    interface to OUT Protocol Engine

    out​_tx​_pid​_iin[3:0] logic
    tx​_pkt​_start​_ooutlogic

    interface to tx module

    tx​_pid​_oout[3:0] logic

    Block Diagram

    Module aes​_mix​_single​_column

    This design unit is implemented in aes​_mix​_single​_column.sv

    This file depends on: aes_pkg.sv

    Ports

    NameDirectionTypeDescription
    op​_iinciph_op_e
    data​_iin[7:0] [3:0] logic
    data​_oout[7:0] [3:0] logic

    Block Diagram

    Module aes​_sbox

    This design unit is implemented in aes​_sbox.sv

    This file depends on: aes_sbox_dom.sv, uvm_pkg.sv, aes_sbox_lut.sv, aes_sbox_canright_masked.sv, aes_sbox_canright.sv, aes_pkg.sv, aes_sbox_canright_masked_noreuse.sv

    Parameters

    NameTypeDefault ValueDescription
    SBoxImplsbox_impl_eSBoxImplLut
    SBoxMaskedbit(SBoxImpl == SBoxImplCanrightMasked || SBoxImpl == SBoxImplCanrightMaskedNoreuse || SBoxImpl == SBoxImplDom) ? 1'b1 : 1'b0
    SBoxSingleCyclebit(SBoxImpl == SBoxImplDom) ? 1'b0 : 1'b1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    en​_iinlogic
    out​_req​_ooutlogic
    out​_ack​_iinlogic
    op​_iinciph_op_e
    data​_iin[7:0] logic
    mask​_iin[7:0] logic
    prd​_iin[WidthPRDSBox-1:0] logic
    data​_oout[7:0] logic
    mask​_oout[7:0] logic

    Block Diagram

    Module ibex​_fetch​_fifo

    This design unit is implemented in ibex​_fetch​_fifo.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    NUM​_REQSint2
    DEPTHintNUM_REQS+1

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    clear​_iinlogic

    clears the contents of the FIFO

    busy​_oout[NUM_REQS-1:0] logic
    in​_valid​_iinlogic

    input port

    in​_addr​_iin[31:0] logic
    in​_rdata​_iin[31:0] logic
    in​_err​_iinlogic
    out​_valid​_ooutlogic

    output port

    out​_ready​_iinlogic
    out​_addr​_oout[31:0] logic
    out​_addr​_next​_oout[31:0] logic
    out​_rdata​_oout[31:0] logic
    out​_err​_ooutlogic
    out​_err​_plus2​_ooutlogic

    Block Diagram

    Module prim​_dom​_and​_2share

    This design unit is implemented in prim​_dom​_and​_2share.sv

    This file depends on: uvm_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    DWint64

    Input width

    EnNegedgeint0

    Enable negedge of clk for register

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    a0​_iin[DW-1:0] logic

    share0 of a

    a1​_iin[DW-1:0] logic

    share1 of a

    b0​_iin[DW-1:0] logic

    share0 of b

    b1​_iin[DW-1:0] logic

    share1 of b

    c​_valid​_iinlogic

    random number input validity

    c0​_iin[DW-1:0] logic

    share0 of random number

    c1​_iin[DW-1:0] logic

    share1 of random number

    q0​_oout[DW-1:0] logic

    share0 of q

    q1​_oout[DW-1:0] logic

    share1 of q

    Block Diagram

    Module prim​_secded​_28​_22​_dec

    This design unit is implemented in prim​_secded​_28​_22​_dec.sv

    Ports

    NameDirectionTypeDescription
    inin[27:0] logic
    d​_oout[21:0] logic
    syndrome​_oout[5:0] logic
    err​_oout[1:0] logic

    Block Diagram

    Module prim​_secded​_28​_22​_enc

    This design unit is implemented in prim​_secded​_28​_22​_enc.sv

    Ports

    NameDirectionTypeDescription
    inin[21:0] logic
    outout[27:0] logic

    Block Diagram

    Module aes​_dom​_dep​_mul​_gf2pn

    This design unit is implemented in aes​_sbox​_dom.sv

    This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv

    Description

    DOM-dep GF(2^N) multiplier, first-order masked. Computes (a_q ^ b_q) = (a_x ^ b_x) * (a_y ^ b_y), i.e. q = x * y using first-order domain-oriented masking. The sharings of x and y are NOT required to be independent from each other. This is the optimized version consuming 2 instead of 3 times N bits of randomness for blinding and resharing. See Formula 12 in 1.

    Parameters

    NameTypeDefault ValueDescription
    NPowerint4
    Pipelinebit1'b0
    PreDomIndepbit1'b0

    1'b0: Not followed by an un-pipelined DOM-indep multiplier, this enables additional area optimizations 1'b1: Directly followed by an un-pipelined DOM-indep multiplier, this is the version discussed in 1.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    we​_iinlogic
    a​_xin[NPower-1:0] logic

    Share a of x

    a​_yin[NPower-1:0] logic

    Share a of y

    b​_xin[NPower-1:0] logic

    Share b of x

    b​_yin[NPower-1:0] logic

    Share b of y

    z​_0in[NPower-1:0] logic

    Randomness for blinding

    z​_1in[NPower-1:0] logic

    Randomness for resharing

    a​_qout[NPower-1:0] logic

    Share a of q

    b​_qout[NPower-1:0] logic

    Share b of q

    Block Diagram

    Module aes​_dom​_dep​_mul​_gf2pn​_unopt

    This design unit is implemented in aes​_sbox​_dom.sv

    This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv

    Description

    DOM-dep GF(2^N) multiplier, first-order masked. Computes (a_q ^ b_q) = (a_x ^ b_x) * (a_y ^ b_y), i.e. q = x * y using first-order domain-oriented masking. The sharings of x and y are NOT required to be independent from each other. This is the un-optimized version consuming 3 times N bits of randomness for blinding and resharing. It is not used in the design but we keep it for reference. See Fig. 4 and Formulas 8 - 11 in 1.

    Parameters

    NameTypeDefault ValueDescription
    NPowerint4
    Pipelinebit1'b0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    we​_iinlogic
    a​_xin[NPower-1:0] logic

    Share a of x

    a​_yin[NPower-1:0] logic

    Share a of y

    b​_xin[NPower-1:0] logic

    Share b of x

    b​_yin[NPower-1:0] logic

    Share b of y

    a​_zin[NPower-1:0] logic

    Randomness for blinding

    b​_zin[NPower-1:0] logic

    Randomness for blinding

    z​_0in[NPower-1:0] logic

    Randomness for resharing

    a​_qout[NPower-1:0] logic

    Share a of q

    b​_qout[NPower-1:0] logic

    Share b of q

    Instantiations

    Block Diagram

    Module aes​_dom​_indep​_mul​_gf2pn

    This design unit is implemented in aes​_sbox​_dom.sv

    This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv

    Description

    DOM-indep GF(2^N) multiplier, first-order masked. Computes (a_q ^ b_q) = (a_x ^ b_x) * (a_y ^ b_y), i.e. q = x * y using first-order domain-oriented masking. The sharings of x and y are required to be uniformly random and independent from each other. See Fig. 2 in 1.

    Parameters

    NameTypeDefault ValueDescription
    NPowerint4
    Pipelinebit1'b0

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    we​_iinlogic
    a​_xin[NPower-1:0] logic

    Share a of x

    a​_yin[NPower-1:0] logic

    Share a of y

    b​_xin[NPower-1:0] logic

    Share b of x

    b​_yin[NPower-1:0] logic

    Share b of y

    z​_0in[NPower-1:0] logic

    Randomness for resharing

    a​_qout[NPower-1:0] logic

    Share a of q

    b​_qout[NPower-1:0] logic

    Share b of q

    Block Diagram

    Module aes​_dom​_inverse​_gf2p4

    This design unit is implemented in aes​_sbox​_dom.sv

    This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv

    Description

    Inverse in GF(2^4) using first-order domain-oriented masking and normal basis z^4, z. See Fig. 6 in 2 (grey block, Stages 2 and 3) and Formulas 6, 13, 14, 15, 16, 17 in 2.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    we​_iin[1:0] logic
    a​_gammain[3:0] logic
    b​_gammain[3:0] logic
    prd​_2in[3:0] logic
    prd​_3in[7:0] logic
    a​_gamma​_invout[3:0] logic
    b​_gamma​_invout[3:0] logic

    Instantiations

    Block Diagram

    Module aes​_dom​_inverse​_gf2p8

    This design unit is implemented in aes​_sbox​_dom.sv

    This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv

    Description

    Inverse in GF(2^8) using first-order domain-oriented masking and normal basis y^16, y. See Fig. 6 in 1 and Formulas 3, 12, 18 and 19 in 2.

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    we​_iin[3:0] logic
    a​_yin[7:0] logic

    input data masked by b_y

    b​_yin[7:0] logic

    input mask

    prdinprd_t

    pseudo-random data, e.g. for intermediate masks

    a​_y​_invout[7:0] logic

    output data masked by b_y_inv

    b​_y​_invout[7:0] logic

    output mask

    Instantiations

    Block Diagram

    Module aes​_masked​_inverse​_gf2p4

    This design unit is implemented in aes​_sbox​_canright​_masked.sv

    This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv

    Description

    Masked inverse in GF(2^4), using normal basis z^4, z (see Formulas 6, 13, 14, 15, 21, 22, 23, 24 in the paper)

    Ports

    NameDirectionTypeDescription
    bin[3:0] logic
    qin[3:0] logic
    rin[1:0] logic
    m1in[3:0] logic
    b​_invout[3:0] logic

    Block Diagram

    Module aes​_masked​_inverse​_gf2p4​_noreuse

    This design unit is implemented in aes​_sbox​_canright​_masked​_noreuse.sv

    This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv

    Description

    Masked inverse in GF(2^4), using normal basis z^4, z (see Formulas 6, 13, 14, 15, 16, 17 in the paper)

    Ports

    NameDirectionTypeDescription
    bin[3:0] logic
    qin[3:0] logic
    rin[1:0] logic
    tin[3:0] logic
    b​_invout[3:0] logic

    Block Diagram

    Module aes​_masked​_inverse​_gf2p8

    This design unit is implemented in aes​_sbox​_canright​_masked.sv

    This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv

    Description

    Masked inverse in GF(2^8), using normal basis y^16, y (see Formulas 3, 12, 25, 26 and 27 in the paper)

    Ports

    NameDirectionTypeDescription
    ain[7:0] logic
    min[7:0] logic
    nin[7:0] logic
    a​_invout[7:0] logic

    Instantiations

    Block Diagram

    Module aes​_masked​_inverse​_gf2p8​_noreuse

    This design unit is implemented in aes​_sbox​_canright​_masked​_noreuse.sv

    This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv

    Description

    Masked inverse in GF(2^8), using normal basis y^16, y (see Formulas 3, 12, 18 and 19 in the paper)

    Ports

    NameDirectionTypeDescription
    ain[7:0] logic

    input data masked by m

    min[7:0] logic

    input mask

    nin[7:0] logic

    output mask

    prdin[9:0] logic

    pseudo-random data, e.g. for intermediate masks

    a​_invout[7:0] logic

    output data masked by n

    Instantiations

    Block Diagram

    Module aes​_sbox​_canright

    This design unit is implemented in aes​_sbox​_canright.sv

    This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv

    Ports

    NameDirectionTypeDescription
    op​_iinciph_op_e
    data​_iin[7:0] logic
    data​_oout[7:0] logic

    Block Diagram

    Module aes​_sbox​_canright​_masked

    This design unit is implemented in aes​_sbox​_canright​_masked.sv

    This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv

    Ports

    NameDirectionTypeDescription
    op​_iinciph_op_e
    data​_iin[7:0] logic

    masked, the actual input data is data_i ^ mask_i

    mask​_iin[7:0] logic

    input mask, independent from actual input data

    prd​_iin[7:0] logic

    pseudo-random data for remasking, independent of input mask

    data​_oout[7:0] logic

    masked, the actual output data is data_o ^ mask_o

    mask​_oout[7:0] logic

    output mask

    Instantiations

    Block Diagram

    Module aes​_sbox​_canright​_masked​_noreuse

    This design unit is implemented in aes​_sbox​_canright​_masked​_noreuse.sv

    This file depends on: aes_sbox_canright_pkg.sv, aes_pkg.sv

    Ports

    NameDirectionTypeDescription
    op​_iinciph_op_e
    data​_iin[7:0] logic

    masked, the actual input data is data_i ^ mask_i

    mask​_iin[7:0] logic

    input mask, independent from actual input data

    prd​_iin[17:0] logic

    pseudo-random data, for remasking and for intermediate masks, must be independent of input mask

    data​_oout[7:0] logic

    masked, the actual output data is data_o ^ mask_o

    mask​_oout[7:0] logic

    output mask

    Instantiations

    Block Diagram

    Module aes​_sbox​_dom

    This design unit is implemented in aes​_sbox​_dom.sv

    This file depends on: uvm_pkg.sv, aes_sbox_canright_pkg.sv, aes_pkg.sv

    Ports

    NameDirectionTypeDescription
    clk​_iinlogic
    rst​_niinlogic
    en​_iinlogic
    out​_req​_ooutlogic
    out​_ack​_iinlogic
    op​_iinciph_op_e
    data​_iin[7:0] logic

    masked, the actual input data is data_i ^ mask_i

    mask​_iin[7:0] logic

    input mask

    prd​_iin[7:0] logic

    pseudo-random data for remasking, in total we need 28 bits of PRD per evaluation, but at most 8 bits per cycle

    data​_oout[7:0] logic

    masked, the actual output data is data_o ^ mask_o

    mask​_oout[7:0] logic

    output mask

    Instantiations

    Block Diagram

    Module aes​_sbox​_lut

    This design unit is implemented in aes​_sbox​_lut.sv

    This file depends on: aes_pkg.sv

    Parameters

    NameTypeDefault ValueDescription
    SBOX​_FWD[7:0] logic [256]'{ 8'h63, 8'h7C, 8'h77, 8'h7B, 8'hF2, 8'h6B, 8'h6F, 8'hC5, 8'h30, 8'h01, 8'h67, 8'h2B, 8'hFE, 8'hD7, 8'hAB, 8'h76, 8'hCA, 8'h82, 8'hC9, 8'h7D, 8'hFA, 8'h59, 8'h47, 8'hF0, 8'hAD, 8'hD4, 8'hA2, 8'hAF, 8'h9C, 8'hA4, 8'h72, 8'hC0, 8'hB7, 8'hFD, 8'h93, 8'h26, 8'h36, 8'h3F, 8'hF7, 8'hCC, 8'h34, 8'hA5, 8'hE5, 8'hF1, 8'h71, 8'hD8, 8'h31, 8'h15, 8'h04, 8'hC7, 8'h23, 8'hC3, 8'h18, 8'h96, 8'h05, 8'h9A, 8'h07, 8'h12, 8'h80, 8'hE2, 8'hEB, 8'h27, 8'hB2, 8'h75, 8'h09, 8'h83, 8'h2C, 8'h1A, 8'h1B, 8'h6E, 8'h5A, 8'hA0, 8'h52, 8'h3B, 8'hD6, 8'hB3, 8'h29, 8'hE3, 8'h2F, 8'h84, 8'h53, 8'hD1, 8'h00, 8'hED, 8'h20, 8'hFC, 8'hB1, 8'h5B, 8'h6A, 8'hCB, 8'hBE, 8'h39, 8'h4A, 8'h4C, 8'h58, 8'hCF, 8'hD0, 8'hEF, 8'hAA, 8'hFB, 8'h43, 8'h4D, 8'h33, 8'h85, 8'h45, 8'hF9, 8'h02, 8'h7F, 8'h50, 8'h3C, 8'h9F, 8'hA8, 8'h51, 8'hA3, 8'h40, 8'h8F, 8'h92, 8'h9D, 8'h38, 8'hF5, 8'hBC, 8'hB6, 8'hDA, 8'h21, 8'h10, 8'hFF, 8'hF3, 8'hD2, 8'hCD, 8'h0C, 8'h13, 8'hEC, 8'h5F, 8'h97, 8'h44, 8'h17, 8'hC4, 8'hA7, 8'h7E, 8'h3D, 8'h64, 8'h5D, 8'h19, 8'h73, 8'h60, 8'h81, 8'h4F, 8'hDC, 8'h22, 8'h2A, 8'h90, 8'h88, 8'h46, 8'hEE, 8'hB8, 8'h14, 8'hDE, 8'h5E, 8'h0B, 8'hDB, 8'hE0, 8'h32, 8'h3A, 8'h0A, 8'h49, 8'h06, 8'h24, 8'h5C, 8'hC2, 8'hD3, 8'hAC, 8'h62, 8'h91, 8'h95, 8'hE4, 8'h79, 8'hE7, 8'hC8, 8'h37, 8'h6D, 8'h8D, 8'hD5, 8'h4E, 8'hA9, 8'h6C, 8'h56, 8'hF4, 8'hEA, 8'h65, 8'h7A, 8'hAE, 8'h08, 8'hBA, 8'h78, 8'h25, 8'h2E, 8'h1C, 8'hA6, 8'hB4, 8'hC6, 8'hE8, 8'hDD, 8'h74, 8'h1F, 8'h4B, 8'hBD, 8'h8B, 8'h8A, 8'h70, 8'h3E, 8'hB5, 8'h66, 8'h48, 8'h03, 8'hF6, 8'h0E, 8'h61, 8'h35, 8'h57, 8'hB9, 8'h86, 8'hC1, 8'h1D, 8'h9E, 8'hE1, 8'hF8, 8'h98, 8'h11, 8'h69, 8'hD9, 8'h8E, 8'h94, 8'h9B, 8'h1E, 8'h87, 8'hE9, 8'hCE, 8'h55, 8'h28, 8'hDF, 8'h8C, 8'hA1, 8'h89, 8'h0D, 8'hBF, 8'hE6, 8'h42, 8'h68, 8'h41, 8'h99, 8'h2D, 8'h0F, 8'hB0, 8'h54, 8'hBB, 8'h16 }

    Define the LUTs

    SBOX​_INV[7:0] logic [256]'{ 8'h52, 8'h09, 8'h6a, 8'hd5, 8'h30, 8'h36, 8'ha5, 8'h38, 8'hbf, 8'h40, 8'ha3, 8'h9e, 8'h81, 8'hf3, 8'hd7, 8'hfb, 8'h7c, 8'he3, 8'h39, 8'h82, 8'h9b, 8'h2f, 8'hff, 8'h87, 8'h34, 8'h8e, 8'h43, 8'h44, 8'hc4, 8'hde, 8'he9, 8'hcb, 8'h54, 8'h7b, 8'h94, 8'h32, 8'ha6, 8'hc2, 8'h23, 8'h3d, 8'hee, 8'h4c, 8'h95, 8'h0b, 8'h42, 8'hfa, 8'hc3, 8'h4e, 8'h08, 8'h2e, 8'ha1, 8'h66, 8'h28, 8'hd9, 8'h24, 8'hb2, 8'h76, 8'h5b, 8'ha2, 8'h49, 8'h6d, 8'h8b, 8'hd1, 8'h25, 8'h72, 8'hf8, 8'hf6, 8'h64, 8'h86, 8'h68, 8'h98, 8'h16, 8'hd4, 8'ha4, 8'h5c, 8'hcc, 8'h5d, 8'h65, 8'hb6, 8'h92, 8'h6c, 8'h70, 8'h48, 8'h50, 8'hfd, 8'hed, 8'hb9, 8'hda, 8'h5e, 8'h15, 8'h46, 8'h57, 8'ha7, 8'h8d, 8'h9d, 8'h84, 8'h90, 8'hd8, 8'hab, 8'h00, 8'h8c, 8'hbc, 8'hd3, 8'h0a, 8'hf7, 8'he4, 8'h58, 8'h05, 8'hb8, 8'hb3, 8'h45, 8'h06, 8'hd0, 8'h2c, 8'h1e, 8'h8f, 8'hca, 8'h3f, 8'h0f, 8'h02, 8'hc1, 8'haf, 8'hbd, 8'h03, 8'h01, 8'h13, 8'h8a, 8'h6b, 8'h3a, 8'h91, 8'h11, 8'h41, 8'h4f, 8'h67, 8'hdc, 8'hea, 8'h97, 8'hf2, 8'hcf, 8'hce, 8'hf0, 8'hb4, 8'he6, 8'h73, 8'h96, 8'hac, 8'h74, 8'h22, 8'he7, 8'had, 8'h35, 8'h85, 8'he2, 8'hf9, 8'h37, 8'he8, 8'h1c, 8'h75, 8'hdf, 8'h6e, 8'h47, 8'hf1, 8'h1a, 8'h71, 8'h1d, 8'h29, 8'hc5, 8'h89, 8'h6f, 8'hb7, 8'h62, 8'h0e, 8'haa, 8'h18, 8'hbe, 8'h1b, 8'hfc, 8'h56, 8'h3e, 8'h4b, 8'hc6, 8'hd2, 8'h79, 8'h20, 8'h9a, 8'hdb, 8'hc0, 8'hfe, 8'h78, 8'hcd, 8'h5a, 8'hf4, 8'h1f, 8'hdd, 8'ha8, 8'h33, 8'h88, 8'h07, 8'hc7, 8'h31, 8'hb1, 8'h12, 8'h10, 8'h59, 8'h27, 8'h80, 8'hec, 8'h5f, 8'h60, 8'h51, 8'h7f, 8'ha9, 8'h19, 8'hb5, 8'h4a, 8'h0d, 8'h2d, 8'he5, 8'h7a, 8'h9f, 8'h93, 8'hc9, 8'h9c, 8'hef, 8'ha0, 8'he0, 8'h3b, 8'h4d, 8'hae, 8'h2a, 8'hf5, 8'hb0, 8'hc8, 8'heb, 8'hbb, 8'h3c, 8'h83, 8'h53, 8'h99, 8'h61, 8'h17, 8'h2b, 8'h04, 8'h7e, 8'hba, 8'h77, 8'hd6, 8'h26, 8'he1, 8'h69, 8'h14, 8'h63, 8'h55, 8'h21, 8'h0c, 8'h7d }

    Ports

    NameDirectionTypeDescription
    op​_iinciph_op_e
    data​_iin[7:0] logic
    data​_oout[7:0] logic

    Block Diagram

    Package aes​_sbox​_canright​_pkg

    This design unit is implemented in aes​_sbox​_canright​_pkg.sv